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samples: benchmarks: coremark: add support for nRF54LM20 PDK
Added the support for the nRF54LM20 PDK board target in the CoreMark sample. Jira: NCSDK-34047 Signed-off-by: Jan Zyczkowski <[email protected]>
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‎samples/benchmarks/coremark/boards/nrf54l15dk_nrf54l15_cpuapp.overlay‎

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#include "app_aliases_common.overlay"
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/* The following configuration is required to run the CPUFLPR core.
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* It is imported from the nordic-flpr snippet.
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* It is imported from the nordic-flpr snippet in the sdk-zephyr repository.
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*/
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/ {
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soc {

‎samples/benchmarks/coremark/boards/nrf54lm20pdk_nrf54lm20a_cpuapp.conf‎

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#
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# Copyright (c) 2025 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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CONFIG_COREMARK_ITERATIONS=4000
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CONFIG_LOG_MODE_IMMEDIATE=y

‎samples/benchmarks/coremark/boards/nrf54lm20pdk_nrf54lm20a_cpuapp.overlay‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#include "app_aliases_common.overlay"
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/* The following configuration is required to run the CPUFLPR core.
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* It is imported from the nordic-flpr snippet in the sdk-nrf repository.
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*/
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/ {
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soc {
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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cpuflpr_code_partition: image@1e5000 {
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/* FLPR core code partition */
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reg = <0x1e5000 DT_SIZE_K(96)>;
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};
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};
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cpuflpr_sram_code_data: memory@20067c00 {
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compatible = "mmio-sram";
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reg = <0x20067c00 DT_SIZE_K(96)>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x20067c00 DT_SIZE_K(96)>;
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};
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};
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};
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&cpuapp_sram {
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reg = <0x20000000 DT_SIZE_K(415)>;
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ranges = <0x0 0x20000000 DT_SIZE_K(415)>;
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};
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&uart30 {
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status = "reserved";
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};
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&cpuflpr_vpr {
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status = "okay";
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execution-memory = <&cpuflpr_sram_code_data>;
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source-memory = <&cpuflpr_code_partition>;
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};
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&cpuapp_vevif_tx {
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status = "okay";
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};
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/* The same set of GPIO and GPIOTE DTS nodes are enabled in the cpuapp and the cpuflpr targets.
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* This is done to allow control over one Button and one LED in each core. The benchmark code is
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* responsible for ensuring that each core exclusively uses the individual GPIO pin and the GPIOTE
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* instance that may be used with the GPIO pin (Button).
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*/

‎samples/benchmarks/coremark/boards/nrf54lm20pdk_nrf54lm20a_cpuflpr.conf‎

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#
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# Copyright (c) 2025 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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CONFIG_COREMARK_ITERATIONS=4000
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CONFIG_LOG_MODE_IMMEDIATE=y

‎samples/benchmarks/coremark/boards/nrf54lm20pdk_nrf54lm20a_cpuflpr.overlay‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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/ {
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aliases {
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button = &button3;
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led = &led3;
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};
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};
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/* The same set of GPIO and GPIOTE DTS nodes are enabled in the cpuapp and the cpuflpr targets.
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* This is done to allow control over one Button and one LED in each core. The benchmark code is
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* responsible for ensuring that each core exclusively uses the individual GPIO pin and the GPIOTE
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* instance that may be used with the GPIO pin (Button).
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*/

‎samples/benchmarks/coremark/sample.yaml‎

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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- nrf54h20dk/nrf54h20/cpuapp
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integration_platforms:
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- nrf52840dk/nrf52840
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- nrf54h20dk/nrf54h20/cpuapp
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tags:
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- ci_build
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- nrf54h20dk/nrf54h20/cpuapp
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integration_platforms:
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- nrf52840dk/nrf52840
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- nrf54h20dk/nrf54h20/cpuapp
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tags:
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- ci_build
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- nrf54h20dk/nrf54h20/cpuapp
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integration_platforms:
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- nrf52840dk/nrf52840
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- nrf54h20dk/nrf54h20/cpuapp
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tags:
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- ci_build
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- nrf54h20dk/nrf54h20/cpuapp
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integration_platforms:
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- nrf52840dk/nrf52840
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- nrf54h20dk/nrf54h20/cpuapp
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tags:
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- ci_build
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- nrf54h20dk/nrf54h20/cpuapp
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integration_platforms:
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- nrf52840dk/nrf52840
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- nrf54h20dk/nrf54h20/cpuapp
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tags:
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- ci_build

‎scripts/quarantine_integration.yaml‎

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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- [email protected]/nrf54h20/cpuapp
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comment: "Configurations excluded to limit resources usage in integration builds"
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- [email protected]/nrf54h20/cpuapp
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comment: "Configurations excluded to limit resources usage in integration builds"
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- nrf54l15dk/nrf54l05/cpuapp
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- nrf54l15dk/nrf54l10/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54lm20pdk/nrf54lm20a/cpuapp
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- [email protected]/nrf54h20/cpuapp
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comment: "Configurations excluded to limit resources usage in integration builds"
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