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boards: Added nrf54h20dk/nrf54h20/cpuapp/iron/b0/mcuboot variant
Added as an extension to the nrf54h20dk board. Signed-off-by: Artur Hadasz <[email protected]>
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‎CODEOWNERS‎

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/boards/nordic/nrf54l*/ @nrfconnect/ncs-co-boards @kl-cruz
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/boards/nordic/nrf52* @nrfconnect/ncs-co-boards @nrfconnect/ncs-si-bluebagel
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/boards/nordic/thingy91* @nrfconnect/ncs-co-boards @nrfconnect/ncs-cia
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/boards/nordic/nrf54h20dk/ @nrfconnect/ncs-charon
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/boards/shields/coverage_support/ @nrfconnect/ncs-low-level-test
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/boards/shields/nrf2220ek/ @nrfconnect/ncs-radio-sw
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/boards/shields/nrf2240ek/ @nrfconnect/ncs-radio-sw

‎boards/nordic/nrf54h20dk/Kconfig.defconfig‎

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# Copyright (c) 2025 Nordic Semiconductor
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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if BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON_B0_MCUBOOT
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config ROM_START_OFFSET
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default 0x800 if BOOTLOADER_MCUBOOT || (MCUBOOT && SECURE_BOOT)
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endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON_B0_MCUBOOT

‎boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk‎

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# Copyright (c) 2025 Nordic Semiconductor
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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config BOARD_NRF54H20DK
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select SOC_NRF54H20_CPUAPP if (BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON_B0_MCUBOOT)
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select SOC_NRF54H20_IRON if (BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON_B0_MCUBOOT)

‎boards/nordic/nrf54h20dk/Kconfig.sysbuild‎

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# Copyright (c) 2025 Nordic Semiconductor
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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config SECURE_BOOT_APPCORE
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default y if BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON_B0_MCUBOOT
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choice BOOTLOADER
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default BOOTLOADER_MCUBOOT if BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON_B0_MCUBOOT
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endchoice

‎boards/nordic/nrf54h20dk/board.cmake‎

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#
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# Copyright (c) 2025 Nordic Semiconductor
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
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if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON_B0_MCUBOOT)
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if(CONFIG_SOC_NRF54H20_CPUAPP)
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set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuapp.JLinkScript)
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else()
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set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpurad.JLinkScript)
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endif()
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board_runner_args(jlink "--device=CORTEX-M33" "--speed=4000" "--tool-opt=-jlinkscriptfile ${JLINKSCRIPTFILE}")
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include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake)
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endif()

‎boards/nordic/nrf54h20dk/board.yml‎

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board:
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extend: nrf54h20dk
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variants:
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- name: b0/mcuboot
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qualifier: nrf54h20/cpuapp/iron

‎boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map_iron_b0_mcuboot.dtsi‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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/* This file is to be merged with the original memory_map.dtsi in the future.
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* The following nodes will be replaced:
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*/
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/delete-node/ &cpuapp_cpusec_ipc_shm;
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/delete-node/ &cpuapp_cpusys_ipc_shm;
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/delete-node/ &cpurad_cpusec_ipc_shm;
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/delete-node/ &cpurad_cpusys_ipc_shm;
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/delete-node/ &cpusec_cpuapp_ipc_shm;
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/delete-node/ &cpusec_cpurad_ipc_shm;
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/delete-node/ &cpusys_cpuapp_ipc_shm;
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/delete-node/ &cpusys_cpurad_ipc_shm;
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/delete-node/ &cpuapp_rw_partitions;
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/delete-node/ &cpuapp_rx_partitions;
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/delete-node/ &cpurad_rx_partitions;
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/ {
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reserved-memory {
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cpuapp_cpusys_ipc_shm: memory@2f88f600 {
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reg = <0x2f88f600 0x80>;
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};
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cpusys_cpuapp_ipc_shm: memory@2f88f680 {
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reg = <0x2f88f680 0x80>;
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};
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cpurad_cpusys_ipc_shm: memory@2f88f700 {
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reg = <0x2f88f700 0x80>;
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};
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cpusys_cpurad_ipc_shm: memory@2f88f780 {
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reg = <0x2f88f780 0x80>;
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};
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cpusec_cpurad_ipc_shm: memory@2f88f800 {
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reg = <0x2f88f800 0x80>;
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};
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cpurad_ironside_se_event_report: memory@2f88f880 {
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reg = <0x2f88f880 0x100>;
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};
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cpurad_ironside_se_boot_report: memory@2f88f980 {
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reg = <0x2f88f980 0x200>;
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};
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cpusec_cpuapp_ipc_shm: memory@2f88fb80 {
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reg = <0x2f88fb80 0x80>;
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};
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cpuapp_ironside_se_event_report: memory@2f88fc00 {
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reg = <0x2f88fc00 0x100>;
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};
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cpuapp_ironside_se_boot_report: memory@2f88fd00 {
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reg = <0x2f88fd00 0x200>;
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};
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};
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};
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&mram1x {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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cpuapp_b0_partition: partition@2c000 {
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reg = <0x2c000 DT_SIZE_K(62)>;
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};
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cpuapp_provision_partition: partition@3b800 {
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reg = <0x3b800 DT_SIZE_K(2)>;
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};
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cpuapp_s0_partition: partition@3c000 {
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reg = <0x3c000 DT_SIZE_K(64)>;
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};
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cpuapp_s1_partition: partition@4c000 {
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reg = <0x4c000 DT_SIZE_K(64)>;
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};
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cpuapp_slot0_partition: partition@5c000 {
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reg = <0x5c000 DT_SIZE_K(336)>;
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};
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cpurad_slot0_partition: partition@b0000 {
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reg = <0xb0000 DT_SIZE_K(272)>;
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};
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cpuppr_code_partition: partition@f4000 {
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reg = <0xf4000 DT_SIZE_K(64)>;
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};
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cpuflpr_code_partition: partition@104000 {
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reg = <0x104000 DT_SIZE_K(48)>;
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};
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cpuapp_slot1_partition: partition@110000 {
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reg = <0x110000 DT_SIZE_K(336)>;
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};
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cpurad_slot1_partition: partition@164000 {
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reg = <0x164000 DT_SIZE_K(272)>;
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};
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storage_partition: partition@1a8000 {
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reg = <0x1a8000 DT_SIZE_K(40)>;
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};
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};
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};

‎boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_b0_mcuboot.dts‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#include "../../../../zephyr/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp.dts"
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#include "../../../../zephyr/boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf_iron.dtsi"
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#include "nrf54h20dk_nrf54h20-memory_map_iron_b0_mcuboot.dtsi"
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/delete-node/ &cpusec_cpurad_ipc;
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/ {
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chosen {
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zephyr,code-partition = &slot0_partition;
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zephyr,uart-mcumgr = &uart136;
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};
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};
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&cpusec_bellboard {
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status = "okay";
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};
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&cpusec_cpuapp_ipc {
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mbox-names = "tx", "rx";
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status = "okay";
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};
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b0_partition: &cpuapp_b0_partition {
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label = "b0";
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};
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provision_partition: &cpuapp_provision_partition {
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label = "provision";
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};
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s0_partition: &cpuapp_s0_partition {
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};
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s1_partition: &cpuapp_s1_partition {
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label = "s1-image";
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};
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slot0_partition: &cpuapp_slot0_partition {
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label = "image-0";
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};
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slot1_partition: &cpuapp_slot1_partition {
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label = "image-1";
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};
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boot_partition: &s0_partition {
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label = "mcuboot";
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};

‎boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_b0_mcuboot_0_9_0.yaml‎

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# Copyright (c) 2025 Nordic Semiconductor
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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identifier: nrf54h20dk/nrf54h20/cpuapp/iron/b0/mcuboot
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name: nRF54H20-DK-nRF54H20-Application (IRONside compatible) with MCUBOOT and NSIB (revision 0.9.0)
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type: mcu
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arch: arm
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toolchain:
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- gnuarmemb
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- xtools
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- zephyr
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sysbuild: true
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ram: 256
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flash: 480
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supported:
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- adc
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- can
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- counter
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- gpio
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- i2c
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- pwm
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- retained_mem
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- spi
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- watchdog
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- usbd

‎boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron_b0_mcuboot_defconfig‎

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# Copyright (c) 2025 Nordic Semiconductor
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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# Enable UART driver
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CONFIG_SERIAL=y
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# Enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# Enable MPU
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CONFIG_ARM_MPU=y
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# Enable hardware stack protection
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CONFIG_HW_STACK_PROTECTION=y
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# MPU-based null-pointer dereferencing detection cannot be applied
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# as the (0x0 - 0x400) region is unmapped for this target.
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CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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# Enable cache
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CONFIG_CACHE_MANAGEMENT=y
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CONFIG_EXTERNAL_CACHE=y
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# Enable GPIO
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CONFIG_GPIO=y
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# UICR generation is not supported, and when reintroduced will not use nrf-regtool.
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CONFIG_NRF_REGTOOL_GENERATE_UICR=n

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