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28 | 28 |
|
29 | 29 | #define MAX_SHIFT_COUNT 63 |
30 | 30 |
|
| 31 | +#define DUMMY_CYCLES_DATA 0x00000000 |
| 32 | + |
31 | 33 | #define CE_PIN_UNUSED UINT8_MAX |
32 | 34 |
|
33 | 35 | #define HRT_IRQ_PRIORITY 2 |
@@ -260,9 +262,15 @@ static void xfer_execute(nrfe_mspi_xfer_packet_msg_t *xfer_packet) |
260 | 262 |
|
261 | 263 | void prepare_and_read_data(nrfe_mspi_xfer_packet_msg_t *xfer_packet, volatile uint8_t *buffer) |
262 | 264 | { |
| 265 | + /* TODO: rx_dummy*bus_width must be divisible by 8, remove when SHIFTCNTB changing is done. |
| 266 | + */ |
| 267 | + NRFX_ASSERT((nrfe_mspi_xfer_config_ptr->rx_dummy * xfer_params.bus_widths.dummy_cycles % |
| 268 | + 8) == 0); |
| 269 | + |
263 | 270 | volatile nrfe_mspi_dev_config_t *device = |
264 | 271 | &nrfe_mspi_devices[nrfe_mspi_xfer_config_ptr->device_index]; |
265 | 272 | nrf_vpr_csr_vio_config_t config; |
| 273 | + uint32_t dummy_cycles_data = DUMMY_CYCLES_DATA; |
266 | 274 |
|
267 | 275 | xfer_params.counter_value = 4; |
268 | 276 | xfer_params.ce_vio = ce_vios[device->ce_index]; |
@@ -298,6 +306,13 @@ void prepare_and_read_data(nrfe_mspi_xfer_packet_msg_t *xfer_packet, volatile ui |
298 | 306 | xfer_params.xfer_data[HRT_FE_ADDRESS].word_count = |
299 | 307 | nrfe_mspi_xfer_config_ptr->address_length; |
300 | 308 |
|
| 309 | + /* Configure dummy_cycles phase. */ |
| 310 | + xfer_params.xfer_data[HRT_FE_DUMMY_CYCLES].fun_out = HRT_FUN_OUT_WORD; |
| 311 | + xfer_params.xfer_data[HRT_FE_DUMMY_CYCLES].data = (uint8_t *)&dummy_cycles_data; |
| 312 | + xfer_params.xfer_data[HRT_FE_DUMMY_CYCLES].word_count = |
| 313 | + nrfe_mspi_xfer_config_ptr->rx_dummy * xfer_params.bus_widths.dummy_cycles / |
| 314 | + BITS_IN_BYTE; |
| 315 | + |
301 | 316 | /* Configure data phase. */ |
302 | 317 | xfer_params.xfer_data[HRT_FE_DATA].word_count = xfer_packet->num_bytes; |
303 | 318 |
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