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Rallareioannisg
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spm: add NRF_DPPIC
Add the NRF_DPPIC peripheral to be configurable in non-secure, with a mask to configure each DPPI channel individually. Signed-off-by: Håkon Alseth <[email protected]>
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subsys/spm/Kconfig

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@@ -193,6 +193,20 @@ config SPM_NRF_WDT_NS
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default n
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endmenu
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config SPM_NRF_DPPIC_NS
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bool "DPPIC is Non-Secure"
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default y
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config SPM_NRF_DPPIC_PERM_MASK
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hex "Set DPPIC PERM mask for Non-secure"
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default 0x0000FFFF
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depends on SPM_NRF_DPPIC_NS
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help
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The input mask is a mirror of the permission bits set in
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register SPU.DPPI.PERM[] to allow non-secure application to
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control DPPIC per the given input mask.
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The default value is to allow all DPPI channels to non-secure region.
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endif # IS_SPM
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endmenu

subsys/spm/spm.c

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@@ -104,6 +104,13 @@ extern int irq_target_state_is_secure(unsigned int irq);
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}
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#endif
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/* Check if configuration exceeds the number of
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* DPPI Channels available on device.
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*/
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#if (CONFIG_SPM_NRF_DPPIC_PERM_MASK >= (1 << DPPI_CH_NUM))
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#error "SPM_NRF_DPPIC_PERM_MASK exceeds number of available DPPI channels"
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#endif
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#if defined(CONFIG_ARM_FIRMWARE_HAS_SECURE_ENTRY_FUNCS)
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static void spm_config_nsc_flash(void)
@@ -271,6 +278,11 @@ static int spm_config_peripheral(u8_t id, bool dma_present)
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return 0;
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}
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static void spm_dppi_configure(u32_t mask)
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{
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NRF_SPU->DPPI[0].PERM = mask;
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}
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static void spm_config_peripherals(void)
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{
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struct periph_cfg {
@@ -344,13 +356,18 @@ static void spm_config_peripherals(void)
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PERIPH("NRF_FPU", NRF_FPU_S, CONFIG_SPM_NRF_FPU_NS),
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PERIPH("NRF_EGU1", NRF_EGU1_S, CONFIG_SPM_NRF_EGU1_NS),
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PERIPH("NRF_EGU2", NRF_EGU2_S, CONFIG_SPM_NRF_EGU2_NS),
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PERIPH("NRF_DPPIC", NRF_DPPIC_S, CONFIG_SPM_NRF_DPPIC_NS),
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PERIPH("NRF_GPIOTE1", NRF_GPIOTE1_NS,
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CONFIG_SPM_NRF_GPIOTE1_NS),
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PERIPH("NRF_REGULATORS", NRF_REGULATORS_S,
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CONFIG_SPM_NRF_REGULATORS_NS),
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};
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if (IS_ENABLED(CONFIG_SPM_NRF_DPPIC_NS)) {
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spm_dppi_configure(CONFIG_SPM_NRF_DPPIC_PERM_MASK);
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}
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PRINT("Peripheral\t\tDomain\t\tStatus\n");
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if (IS_ENABLED(CONFIG_SPM_NRF_P0_NS)) {

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