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| 1 | +/* |
| 2 | + * Copyright (c) 2025 Nordic Semiconductor ASA |
| 3 | + * |
| 4 | + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause |
| 5 | + */ |
| 6 | + |
| 7 | +#ifndef __CPUCONF_H__ |
| 8 | +#define __CPUCONF_H__ |
| 9 | + |
| 10 | +#include <zephyr/drivers/firmware/nrf_ironside/call.h> |
| 11 | + |
| 12 | +#define IRONSIDE_SE_CPUCONF_SERVICE_WRONG_CPU 0x5eb2 |
| 13 | +#define IRONSIDE_SE_CPUCONF_SERVICE_STARTING_CPU_FAILED 0x5eb0 |
| 14 | +#define IRONSIDE_SE_CPUCONF_SERVICE_MEM_ACCESS_NOT_PERMITTED 0x5eb1 |
| 15 | + |
| 16 | +#define IRONSIDE_CALL_ID_CPUCONF_V0 2 |
| 17 | + |
| 18 | +enum { |
| 19 | + IRONSIDE_SE_CPUCONF_INDEX_CPU, |
| 20 | + IRONSIDE_SE_CPUCONF_INDEX_VECTOR_TABLE, |
| 21 | + IRONSIDE_SE_CPUCONF_INDEX_CPU_WAIT, |
| 22 | + IRONSIDE_SE_CPUCONF_INDEX_MSG, |
| 23 | + IRONSIDE_SE_CPUCONF_INDEX_MSG_SIZE, |
| 24 | + IRONSIDE_SE_CPUCONF_INDEX_ERR, |
| 25 | + /* The last enum value is reserved for the number of arguments */ |
| 26 | + IRONSIDE_SE_CPUCONF_NUM_ARGS |
| 27 | +}; |
| 28 | + |
| 29 | +BUILD_ASSERT(IRONSIDE_SE_CPUCONF_NUM_ARGS <= NRF_IRONSIDE_CALL_NUM_ARGS); |
| 30 | + |
| 31 | +/** |
| 32 | + * @brief Boot a local domain CPU |
| 33 | + * |
| 34 | + * @param cpu The CPU to be booted |
| 35 | + * @param vector_table Pointer to the vector table used to boot the CPU. |
| 36 | + * @param cpu_wait When this is true, the CPU will WAIT even if the CPU has clock. |
| 37 | + * @param msg A message that can be placed in radiocore's boot report. |
| 38 | + * @param msg_size Size of the message in bytes. |
| 39 | + * |
| 40 | + * @note cpu_wait is only intended to be enabled for debug purposes |
| 41 | + * and it is only supported that a debugger resumes the CPU. |
| 42 | + * |
| 43 | + * @retval 0 on success or if the CPU has already booted. |
| 44 | + * @retval -IRONSIDE_SE_CPUCONF_SERVICE_WRONG_CPU if cpu is unrecognized |
| 45 | + * @retval -IRONSIDE_SE_CPUCONF_SERVICE_STARTING_CPU_FAILED if starting the CPU failed |
| 46 | + * @retval -IRONSIDE_SE_CPUCONF_SERVICE_MEM_ACCESS_NOT_PERMITTED |
| 47 | + * if the CPU does not have read access configured for the vector_table address |
| 48 | + */ |
| 49 | +int ironside_se_cpuconf_boot_core(NRF_PROCESSORID_Type cpu, void *vector_table, bool cpu_wait, uint8_t *msg, size_t msg_size); |
| 50 | + |
| 51 | +#endif /* __CPUCONF_SERVICE_H__ */ |
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