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applications: sdp: mspi: Initial implementation
Added initial mspi implementation with hard real time task running on interrupts. Signed-off-by: Michal Frankiewicz <[email protected]> Signed-off-by: Magdalena Pastula <[email protected]>
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‎applications/sdp/mspi/CMakeLists.txt‎

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#
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# Copyright (c) 2024 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(sdp_mspi)
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sdp_assembly_generate("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
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sdp_assembly_check("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
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sdp_assembly_prepare_install("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
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target_sources(app PRIVATE src/main.c)
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target_sources(app PRIVATE src/hrt/hrt.s)
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add_dependencies(app asm_check)

‎applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf‎

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# Single-threaded
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CONFIG_MULTITHREADING=n
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CONFIG_KERNEL_MEM_POOL=n
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CONFIG_LOG=n
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# Drivers and peripherals
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CONFIG_I2C=n
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CONFIG_WATCHDOG=n
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CONFIG_GPIO=n
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CONFIG_PINCTRL=n
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CONFIG_SPI=n
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CONFIG_SERIAL=n
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CONFIG_FLASH=n
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# Power management
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CONFIG_PM=n
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# Interrupts
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CONFIG_DYNAMIC_INTERRUPTS=n
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CONFIG_IRQ_OFFLOAD=n
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CONFIG_GEN_SW_ISR_TABLE=n
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# Memory protection
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CONFIG_THREAD_STACK_INFO=n
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CONFIG_THREAD_CUSTOM_DATA=n
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CONFIG_FPU=n
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# Boot
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CONFIG_BOOT_BANNER=n
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CONFIG_NCS_BOOT_BANNER=n
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# Console
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CONFIG_CONSOLE=n
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CONFIG_UART_CONSOLE=n
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CONFIG_STDOUT_CONSOLE=n
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CONFIG_PRINTK=n
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CONFIG_EARLY_CONSOLE=n
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# Build
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CONFIG_SIZE_OPTIMIZATIONS=y
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# No timer support in the kernel
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CONFIG_SYS_CLOCK_EXISTS=n
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CONFIG_OUTPUT_DISASSEMBLY=y
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CONFIG_COMMON_LIBC_MALLOC=n

‎applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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&gpio0 {
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status = "disabled";
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};
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&gpio1 {
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status = "disabled";
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};
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&gpio2 {
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status = "disabled";
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};
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&gpiote20 {
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status = "disabled";
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};
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&gpiote30 {
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status = "disabled";
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};
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&grtc {
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status = "disabled";
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};
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&uart20 {
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status = "disabled";
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};
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&uart30 {
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status = "disabled";
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};
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&pwm20 {
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status = "disabled";
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};

‎applications/sdp/mspi/prj.conf‎

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CONFIG_MBOX=y

‎applications/sdp/mspi/sample.yaml‎

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sample:
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name: SDP mSPI application
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description: SDP mSPI application
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common:
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integration_platforms:
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- nrf54l15dk/nrf54l15/cpuflpr
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tests:
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applications.sdp.mspi.icmsg:
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build_only: true
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sysbuild: true
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platform_allow: nrf54l15dk/nrf54l15/cpuflpr
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tags: ci_build sysbuild mspi
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extra_configs:
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- CONFIG_IPC_SERVICE=y
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- CONFIG_IPC_SERVICE_BACKEND_ICMSG=y

‎applications/sdp/mspi/src/hrt/hrt.c‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#include "hrt.h"
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#include <hal/nrf_vpr_csr_vio.h>
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#include <hal/nrf_vpr_csr_vtim.h>
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#define TOP 4
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void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t counter_top,
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uint8_t word_size, bool ce_enable_state, bool hold_ce)
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{
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NRFX_ASSERT(word_size > MAX_WORD_SIZE);
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/* Configuration step */
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uint16_t dir = nrf_vpr_csr_vio_dir_get();
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nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(D0_PIN) | PIN_DIR_OUT_MASK(CS_PIN) |
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PIN_DIR_OUT_MASK(SCLK_PIN));
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uint16_t out = nrf_vpr_csr_vio_out_get();
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nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(D0_PIN) | PIN_OUT_HIGH_MASK(CS_PIN) |
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PIN_OUT_LOW_MASK(SCLK_PIN));
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nrf_vpr_csr_vio_mode_out_t out_mode = {
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.mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE,
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.frame_width = 1,
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};
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nrf_vpr_csr_vio_mode_out_set(&out_mode);
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nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
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nrf_vpr_csr_vio_config_t config;
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nrf_vpr_csr_vio_config_get(&config);
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config.input_sel = false;
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nrf_vpr_csr_vio_config_set(&config);
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/* Fix position of data if word size < MAX_WORD_SIZE,
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* so that leading zeros would not be printed instead of data bits.
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*/
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if (word_size < MAX_WORD_SIZE) {
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for (uint8_t i = 0; i < data_len; i++) {
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data[i] = data[i] << (MAX_WORD_SIZE - word_size);
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}
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}
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/* Counter settings */
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nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_RELOAD);
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nrf_vpr_csr_vtim_simple_counter_top_set(0, counter_top);
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/* Set number of shifts before OUTB needs to be updated.
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* First shift needs to be increased by 1.
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*/
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nrf_vpr_csr_vio_shift_cnt_out_set(word_size);
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nrf_vpr_csr_vio_shift_cnt_out_buffered_set(word_size - 1);
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/* Enable CS */
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out = nrf_vpr_csr_vio_out_get();
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out &= ~PIN_OUT_HIGH_MASK(CS_PIN);
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out |= ce_enable_state ? PIN_OUT_HIGH_MASK(CS_PIN) : PIN_OUT_LOW_MASK(CS_PIN);
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nrf_vpr_csr_vio_out_set(out);
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/* Start counter */
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nrf_vpr_csr_vtim_simple_counter_set(0, 3 * counter_top);
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/* Send data */
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for (uint8_t i = 0; i < data_len; i++) {
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nrf_vpr_csr_vio_out_buffered_reversed_byte_set(data[i]);
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}
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/* Clear all bits, wait until the last word is sent */
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nrf_vpr_csr_vio_out_buffered_set(0);
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/* Final configuration */
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out_mode.mode = NRF_VPR_CSR_VIO_SHIFT_NONE;
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nrf_vpr_csr_vio_mode_out_buffered_set(&out_mode);
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nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
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/* Deselect slave */
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if (!hold_ce) {
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out = nrf_vpr_csr_vio_out_get();
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out &= ~(PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_HIGH_MASK(SCLK_PIN));
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out |= ce_enable_state ? PIN_OUT_LOW_MASK(CS_PIN) : PIN_OUT_HIGH_MASK(CS_PIN);
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out |= PIN_OUT_LOW_MASK(SCLK_PIN);
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nrf_vpr_csr_vio_out_set(out);
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}
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/* Stop counter */
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nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP);
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}
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void write_quad_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t counter_top,
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uint8_t word_size, bool ce_enable_state, bool hold_ce)
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{
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NRFX_ASSERT(word_size > MAX_WORD_SIZE);
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NRFX_ASSERT(word_size % 4 == 0);
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/* Configuration step */
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uint16_t dir = nrf_vpr_csr_vio_dir_get();
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nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(D0_PIN) | PIN_DIR_OUT_MASK(D1_PIN) |
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PIN_DIR_OUT_MASK(D2_PIN) | PIN_DIR_OUT_MASK(D3_PIN) |
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PIN_DIR_OUT_MASK(CS_PIN) | PIN_DIR_OUT_MASK(SCLK_PIN));
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uint16_t out = nrf_vpr_csr_vio_out_get();
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nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(D0_PIN) | PIN_OUT_LOW_MASK(D1_PIN) |
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PIN_OUT_LOW_MASK(D2_PIN) | PIN_OUT_LOW_MASK(D3_PIN) |
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PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_LOW_MASK(SCLK_PIN));
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nrf_vpr_csr_vio_mode_out_t out_mode = {
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.mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE,
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.frame_width = 4,
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};
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nrf_vpr_csr_vio_mode_out_set(&out_mode);
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nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
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nrf_vpr_csr_vio_config_t config;
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nrf_vpr_csr_vio_config_get(&config);
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config.input_sel = false;
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nrf_vpr_csr_vio_config_set(&config);
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/* Fix position of data if word size < MAX_WORD_SIZE,
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* so that leading zeros would not be printed instead of data.
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*/
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if (word_size < MAX_WORD_SIZE) {
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for (uint8_t i = 0; i < data_len; i++) {
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data[i] = data[i] << (MAX_WORD_SIZE - word_size);
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}
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}
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/* Counter settings */
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nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_RELOAD);
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nrf_vpr_csr_vtim_simple_counter_top_set(0, counter_top);
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/* Set number of shifts before OUTB needs to be updated.
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* First shift needs to be increased by 1.
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*/
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nrf_vpr_csr_vio_shift_cnt_out_set(word_size / 4);
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nrf_vpr_csr_vio_shift_cnt_out_buffered_set(word_size / 4 - 1);
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/* Enable CS */
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out = nrf_vpr_csr_vio_out_get();
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out &= ~PIN_OUT_HIGH_MASK(CS_PIN);
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out |= ce_enable_state ? PIN_OUT_HIGH_MASK(CS_PIN) : PIN_OUT_LOW_MASK(CS_PIN);
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nrf_vpr_csr_vio_out_set(out);
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/* Start counter */
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nrf_vpr_csr_vtim_simple_counter_set(0, 3 * counter_top);
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/* Send data */
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for (uint8_t i = 0; i < data_len; i++) {
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nrf_vpr_csr_vio_out_buffered_reversed_byte_set(data[i]);
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}
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/* Clear all bits, wait until the last word is sent */
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nrf_vpr_csr_vio_out_buffered_set(0);
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/* Final configuration */
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out_mode.mode = NRF_VPR_CSR_VIO_SHIFT_NONE;
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nrf_vpr_csr_vio_mode_out_buffered_set(&out_mode);
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nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
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/* Deselect slave */
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if (!hold_ce) {
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out = nrf_vpr_csr_vio_out_get();
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out &= ~(PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_HIGH_MASK(SCLK_PIN));
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out |= ce_enable_state ? PIN_OUT_LOW_MASK(CS_PIN) : PIN_OUT_HIGH_MASK(CS_PIN);
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out |= PIN_OUT_LOW_MASK(SCLK_PIN);
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nrf_vpr_csr_vio_out_set(out);
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}
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/* Stop counter */
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nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP);
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}

‎applications/sdp/mspi/src/hrt/hrt.h‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#ifndef _HRT_H__
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#define _HRT_H__
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#include <stdint.h>
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#include <stdbool.h>
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#define SCLK_PIN 0
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#define D0_PIN 1
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#define D1_PIN 2
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#define D2_PIN 3
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#define D3_PIN 4
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#define CS_PIN 5
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/* Max word size. */
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#define MAX_WORD_SIZE NRF_VPR_CSR_VIO_SHIFT_CNT_OUT_BUFFERED_MAX
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/* Macro for getting direction mask for specified pin and direction. */
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#define PIN_DIR_MASK(PIN_NUM, DIR) \
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(VPRCSR_NORDIC_DIR_PIN##PIN_NUM##_##DIR << VPRCSR_NORDIC_DIR_PIN##PIN_NUM##_Pos)
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/* Macro for getting output mask for specified pin. */
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#define PIN_DIR_OUT_MASK(PIN_NUM) PIN_DIR_MASK(PIN_NUM, OUTPUT)
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/* Macro for getting input mask for specified pin. */
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#define PIN_DIR_IN_MASK(PIN_NUM) PIN_DIR_MASK(PIN_NUM, INPUT)
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/* Macro for getting state mask for specified pin and state. */
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#define PIN_OUT_MASK(PIN_NUM, STATE) \
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(VPRCSR_NORDIC_OUT_PIN##PIN_NUM##_##STATE << VPRCSR_NORDIC_OUT_PIN##PIN_NUM##_Pos)
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/* Macro for getting high state mask for specified pin. */
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#define PIN_OUT_HIGH_MASK(PIN_NUM) PIN_OUT_MASK(PIN_NUM, HIGH)
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/* Macro for getting low state mask for specified pin. */
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#define PIN_OUT_LOW_MASK(PIN_NUM) PIN_OUT_MASK(PIN_NUM, LOW)
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/** @brief Write on single line.
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*
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* Function to be used to write data on single data line (SPI).
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*
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* @param[in] data Data to be sent.
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* @param[in] data_len Length of data in words.
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* @param[in] counter_top Top value of VTIM. This will determine clock frequency
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* (SPI_CLOCK ~= CPU_CLOCK / (2 * TOP)).
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* @param[in] word_size Size of a word in bits.
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* @param[in] ce_enable_state Chip enable pin polarity in enabled state
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* @param[in] hold_ce If true CE pin will be left enabled after transfer
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*/
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void write_single_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t counter_top,
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uint8_t word_size, bool ce_enable_state, bool hold_ce);
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/** @brief Write on four lines.
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*
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* Function to be used to write data on quad data line (SPI).
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*
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* @param[in] data Data to be sent.
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* @param[in] data_len Length of data in words.
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* @param[in] counter_top Top value of VTIM. This will determine clock frequency
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* (SPI_CLOCK ~= CPU_CLOCK / (2 * TOP)).
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* @param[in] word_size Size of a word in bits.
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* @param[in] ce_enable_state Chip enable pin polarity in enabled state
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* @param[in] hold_ce If true CE pin will be left enabled after transfer
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*/
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void write_quad_by_word(volatile uint32_t *data, uint8_t data_len, uint32_t counter_top,
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uint8_t word_size, bool ce_enable_state, bool hold_ce);
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#endif /* _HRT_H__ */

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