applications: sdp: mspi: add SPI RX path

Add path for receiving data on SPI.

Signed-off-by: Magdalena Pastula <[email protected]>

Author: magp-nordic

applications/sdp/mspi/CMakeLists.txt

@@ -14,6 +14,6 @@ sdp_assembly_check("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
 sdp_assembly_prepare_install("${CMAKE_SOURCE_DIR}/src/hrt/hrt.c")
 
 target_sources(app PRIVATE src/main.c)
-target_sources(app PRIVATE src/hrt/hrt.s)
+target_sources(app PRIVATE src/hrt/hrt.c)
 
 add_dependencies(app asm_check)

applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.conf

@@ -7,9 +7,9 @@ CONFIG_LOG=n
 CONFIG_I2C=n
 CONFIG_WATCHDOG=n
 CONFIG_GPIO=n
-CONFIG_PINCTRL=n
+CONFIG_PINCTRL=y
 CONFIG_SPI=n
-CONFIG_SERIAL=n
+CONFIG_SERIAL=y
 CONFIG_FLASH=n
 
 # Power management
@@ -18,23 +18,23 @@ CONFIG_PM=n
 # Interrupts
 CONFIG_DYNAMIC_INTERRUPTS=n
 CONFIG_IRQ_OFFLOAD=n
-CONFIG_GEN_SW_ISR_TABLE=n
+CONFIG_GEN_SW_ISR_TABLE=y
 
 # Memory protection
 CONFIG_THREAD_STACK_INFO=n
 CONFIG_THREAD_CUSTOM_DATA=n
 CONFIG_FPU=n
 
 # Boot
-CONFIG_BOOT_BANNER=n
+CONFIG_BOOT_BANNER=y
 CONFIG_NCS_BOOT_BANNER=n
 
 # Console
-CONFIG_CONSOLE=n
-CONFIG_UART_CONSOLE=n
-CONFIG_STDOUT_CONSOLE=n
-CONFIG_PRINTK=n
-CONFIG_EARLY_CONSOLE=n
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+CONFIG_STDOUT_CONSOLE=y
+CONFIG_PRINTK=y
+CONFIG_EARLY_CONSOLE=y
 
 # Build
 CONFIG_SIZE_OPTIMIZATIONS=y

applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay

@@ -10,12 +10,12 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			sram_tx: memory@2003c000 {
-				reg = <0x2003c000 0x0800>;
+			sram_tx: memory@2003a000 {
+				reg = <0x2003a000 0x0800>;
 			};
 
-			sram_rx: memory@2003c800 {
-				reg = <0x2003c800 0x0800>;
+			sram_rx: memory@2003a800 {
+				reg = <0x2003a800 0x0800>;
 			};
 		};
 	};
@@ -33,16 +33,16 @@
 };
 
 &cpuflpr_rram {
-	reg = <0x17a000 DT_SIZE_K(12)>;
+	reg = <0x178000 DT_SIZE_K(20)>;
 };
 
 &cpuflpr_code_partition {
-	reg = <0x0 DT_SIZE_K(12)>;
+	reg = <0x0 DT_SIZE_K(20)>;
 };
 
 &cpuflpr_sram {
-	reg = <0x2003d000 DT_SIZE_K(12)>;
-	ranges = <0x0 0x2003d000 0x3000>;
+	reg = <0x2003b000 DT_SIZE_K(20)>;
+	ranges = <0x0 0x2003b000 0x5000>;
 };
 
 &cpuflpr_vevif_rx {
@@ -85,7 +85,7 @@
 };
 
 &uart30 {
-	status = "disabled";
+	status = "okay";
 };
 
 &pwm20 {

applications/sdp/mspi/src/hrt/hrt.c

@@ -10,6 +10,13 @@
 /* Hardware requirement, to get n shifts SHIFTCNTB register has to be set to n-1*/
 #define SHIFTCNTB_VALUE(shift_count) (shift_count - 1)
 
+#define SPI_INPUT_PIN_NUM	2
+#define CNT1_INIT_VALUE		1
+
+#define INPUT_SHIFT_COUNT	(BITS_IN_WORD - BITS_IN_BYTE)
+
+#define CNT1_TOP_CALCULATE(cnt0_top) (2 * ((cnt0_top) + 1) - 1)
+
 /** @brief Shift control configuration. */
 typedef struct {
 	uint8_t shift_count;
@@ -189,3 +196,121 @@ void hrt_write(hrt_xfer_t *hrt_xfer_params)
 		}
 	}
 }
+
+static void hrt_tx_rx(volatile hrt_xfer_data_t *xfer_data, uint8_t frame_width, uint16_t cnt0_val, uint16_t cnt1_val, bool *counter_running)
+{
+	if(xfer_data->word_count == 0)
+	{
+		return;
+	}
+
+	nrf_vpr_csr_vio_shift_ctrl_t shift_ctrl = {
+		.shift_count = BITS_IN_BYTE - 1,
+		.out_mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE,
+		.frame_width = frame_width,
+		.in_mode = NRF_VPR_CSR_VIO_MODE_IN_SHIFT,
+	};
+
+	for (uint32_t i = 0; i < xfer_data->word_count; i++) {
+
+		switch (xfer_data->word_count - i) {
+			case 1: /* Last transfer */
+				shift_ctrl.shift_count = xfer_data->last_word_clocks - 1;
+				nrf_vpr_csr_vio_shift_ctrl_buffered_set(&shift_ctrl);
+
+				xfer_data->vio_out_set(xfer_data->last_word);
+				break;
+			case 2: /* Last but one transfer.*/
+				shift_ctrl.shift_count =
+					xfer_data->penultimate_word_clocks - 1;
+				nrf_vpr_csr_vio_shift_ctrl_buffered_set(&shift_ctrl);
+				xfer_data->vio_out_set(((uint32_t *)xfer_data->data)[i]);
+				break;
+			default:
+				nrf_vpr_csr_vio_shift_ctrl_buffered_set(&shift_ctrl);
+				xfer_data->vio_out_set(((uint32_t *)xfer_data->data)[i]);
+		}
+
+		if ((i == 0) && (!*counter_running)) {
+			/* Start both counters */
+			nrf_vpr_csr_vtim_combined_counter_set(
+				(cnt0_val << VPRCSR_NORDIC_CNT_CNT0_Pos) +
+				(cnt1_val << VPRCSR_NORDIC_CNT_CNT1_Pos));
+			*counter_running = true;
+		}
+	}
+}
+
+void hrt_read(volatile hrt_xfer_t *hrt_xfer_params)
+{
+	uint16_t out;
+	bool counter_running = false;
+	nrf_vpr_csr_vio_shift_ctrl_t shift_ctrl = {
+		.out_mode = NRF_VPR_CSR_VIO_SHIFT_NONE,
+		.in_mode = NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS,
+	};
+	nrf_vpr_csr_vio_mode_out_t out_mode = {
+		.mode = NRF_VPR_CSR_VIO_SHIFT_OUTB_TOGGLE,
+		.frame_width = 1,
+	};
+
+	/* Enable CS */
+	out = nrf_vpr_csr_vio_out_get();
+	if (hrt_xfer_params->ce_polarity == MSPI_CE_ACTIVE_LOW) {
+		WRITE_BIT(out, hrt_xfer_params->ce_vio, VPRCSR_NORDIC_OUT_LOW);
+	} else {
+		WRITE_BIT(out, hrt_xfer_params->ce_vio, VPRCSR_NORDIC_OUT_HIGH);
+	}
+	nrf_vpr_csr_vio_out_set(out);
+
+	/* Configure clock and pins */
+	/* Set DQ1 as input */
+	WRITE_BIT(hrt_xfer_params->tx_direction_mask, SPI_INPUT_PIN_NUM, VPRCSR_NORDIC_DIR_INPUT);
+	nrf_vpr_csr_vio_dir_set(hrt_xfer_params->tx_direction_mask);
+
+	/* Initial configuration */
+	nrf_vpr_csr_vio_mode_in_set(NRF_VPR_CSR_VIO_MODE_IN_SHIFT);
+	nrf_vpr_csr_vio_mode_out_set(&out_mode);
+	nrf_vpr_csr_vio_shift_cnt_out_set(hrt_xfer_params->xfer_data[HRT_FE_COMMAND].word_count * BITS_IN_BYTE);
+
+	/* Counter settings */
+	nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_RELOAD);
+	nrf_vpr_csr_vtim_count_mode_set(1, NRF_VPR_CSR_VTIM_COUNT_RELOAD);
+
+	/* Set top counters value. Trigger data capture every two clock cycles */
+	nrf_vpr_csr_vtim_simple_counter_top_set(0, hrt_xfer_params->counter_value);
+	nrf_vpr_csr_vtim_simple_counter_top_set(1, CNT1_TOP_CALCULATE(hrt_xfer_params->counter_value));
+
+	/* Transfer command */
+	hrt_tx_rx(&hrt_xfer_params->xfer_data[HRT_FE_COMMAND], hrt_xfer_params->bus_widths.command, hrt_xfer_params->counter_value,
+			CNT1_INIT_VALUE, &counter_running);
+
+	for (uint8_t i = 0; i < hrt_xfer_params->xfer_data[HRT_FE_DATA].word_count; i++)
+	{
+		hrt_xfer_params->xfer_data[HRT_FE_DATA].rx_data[i] = hrt_xfer_params->xfer_data[HRT_FE_DATA].vio_inb_get() >> INPUT_SHIFT_COUNT;
+	}
+
+	/* Final configuration */
+	nrf_vpr_csr_vio_shift_ctrl_buffered_set(&shift_ctrl);
+	nrf_vpr_csr_vio_out_buffered_reversed_word_set(0);
+
+	/* Stop counters */
+	nrf_vpr_csr_vtim_count_mode_set(0, NRF_VPR_CSR_VTIM_COUNT_STOP);
+	nrf_vpr_csr_vtim_count_mode_set(1, NRF_VPR_CSR_VTIM_COUNT_STOP);
+
+	/* Disable CS */
+	if (!hrt_xfer_params->ce_hold) {
+		out = nrf_vpr_csr_vio_out_get();
+
+		if (hrt_xfer_params->ce_polarity == MSPI_CE_ACTIVE_LOW) {
+			WRITE_BIT(out, hrt_xfer_params->ce_vio, VPRCSR_NORDIC_OUT_HIGH);
+		} else {
+			WRITE_BIT(out, hrt_xfer_params->ce_vio, VPRCSR_NORDIC_OUT_LOW);
+		}
+		nrf_vpr_csr_vio_out_set(out);
+	}
+
+	/* Set DQ1 back as output. */
+	WRITE_BIT(hrt_xfer_params->tx_direction_mask, SPI_INPUT_PIN_NUM, VPRCSR_NORDIC_DIR_OUTPUT);
+	nrf_vpr_csr_vio_dir_set(hrt_xfer_params->tx_direction_mask);
+}

applications/sdp/mspi/src/hrt/hrt.h

@@ -37,7 +37,8 @@ typedef struct {
 
 typedef struct {
 	/** @brief Buffer for RX/TX data */
-	volatile uint8_t *data;
+	uint8_t *data;
+	uint8_t *rx_data;
 
 	/** @brief Data length in 4 byte words,
 	 *         calculated as CEIL(buffer_length_bits/32).
@@ -70,6 +71,10 @@ typedef struct {
 
 	/** @brief Function for writing to buffered out register. */
 	void (*vio_out_set)(uint32_t value);
+
+	/** @brief Function for reading from buffered in register. */
+	uint32_t (*vio_inb_get)(void);
+
 } hrt_xfer_data_t;
 
 /** @brief Hrt transfer parameters. */
@@ -115,4 +120,12 @@ typedef struct {
  */
 void hrt_write(hrt_xfer_t *hrt_xfer_params);
 
+/** @brief Read.
+ *
+ *  Function to be used to read data from MSPI.
+ *
+ *  @param[in] hrt_xfer_params Hrt transfer parameters.
+ */
+void hrt_read(volatile hrt_xfer_t *hrt_xfer_params);
+
 #endif /* _HRT_H__ */