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6 | 6 |
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7 | 7 | #include <mpsl_fem_twi_drv.h> |
8 | 8 | #include <zephyr/drivers/i2c.h> |
| 9 | +#include <zephyr/drivers/i2c/i2c_nrfx_twim.h> |
| 10 | +#include <../drivers/i2c/i2c_nrfx_twim_common.h> |
9 | 11 |
|
| 12 | +static int32_t mpsl_fem_twi_drv_impl_xfer_read(void *p_instance, uint8_t slave_address, |
| 13 | + uint8_t internal_address, uint8_t *p_data, |
| 14 | + uint8_t data_length) |
| 15 | +{ |
| 16 | + mpsl_fem_twi_drv_t *drv = (mpsl_fem_twi_drv_t *)p_instance; |
| 17 | + |
| 18 | + return i2c_burst_read(drv->dev, slave_address, internal_address, p_data, data_length); |
| 19 | +} |
| 20 | + |
| 21 | +static int32_t mpsl_fem_twi_drv_impl_xfer_write(void *p_instance, uint8_t slave_address, |
| 22 | + uint8_t internal_address, const uint8_t *p_data, |
| 23 | + uint8_t data_length) |
| 24 | +{ |
| 25 | + mpsl_fem_twi_drv_t *drv = (mpsl_fem_twi_drv_t *)p_instance; |
| 26 | + |
| 27 | + return i2c_burst_write(drv->dev, slave_address, internal_address, p_data, data_length); |
| 28 | +} |
| 29 | + |
| 30 | +static inline void mpsl_fem_twi_drv_nrfx_twim_callback_replace(mpsl_fem_twi_drv_t *drv, |
| 31 | + nrfx_twim_evt_handler_t callback) |
| 32 | +{ |
| 33 | + const struct i2c_nrfx_twim_common_config *config = drv->dev->config; |
| 34 | + nrfx_err_t err; |
| 35 | + |
| 36 | + nrfx_twim_callback_get(&config->twim, &drv->nrfx_twim_callback_saved, |
| 37 | + &drv->nrfx_twim_callback_ctx_saved); |
| 38 | + |
| 39 | + err = nrfx_twim_callback_set(&config->twim, callback, drv); |
| 40 | + |
| 41 | + __ASSERT_NO_MSG(err == NRFX_SUCCESS); |
| 42 | + (void)err; |
| 43 | +} |
| 44 | + |
| 45 | +static inline void mpsl_fem_twi_drv_nrfx_twim_callback_restore(mpsl_fem_twi_drv_t *drv) |
| 46 | +{ |
| 47 | + const struct i2c_nrfx_twim_common_config *config = drv->dev->config; |
| 48 | + nrfx_err_t err; |
| 49 | + |
| 50 | + err = nrfx_twim_callback_set(&config->twim, drv->nrfx_twim_callback_saved, |
| 51 | + drv->nrfx_twim_callback_ctx_saved); |
| 52 | + |
| 53 | + __ASSERT_NO_MSG(err == NRFX_SUCCESS); |
| 54 | + (void)err; |
| 55 | +} |
| 56 | + |
| 57 | +static void mpsl_fem_twi_drv_nrfx_twim_evt_handler(nrfx_twim_evt_t const *p_event, void *p_context) |
| 58 | +{ |
| 59 | + mpsl_fem_twi_drv_t *drv = (mpsl_fem_twi_drv_t *)p_context; |
| 60 | + int32_t res = 0; |
| 61 | + |
| 62 | + mpsl_fem_twi_drv_nrfx_twim_callback_restore(drv); |
10 | 63 |
|
11 | | -int32_t mpsl_fem_twi_drv_impl_xfer_read(void *p_instance, uint8_t slave_address, |
12 | | - uint8_t internal_address, uint8_t *p_data, uint8_t data_length) |
| 64 | + if (p_event->type != NRFX_TWIM_EVT_DONE) { |
| 65 | + res = -EIO; |
| 66 | + } |
| 67 | + |
| 68 | + /* Call the callback which was passed to the mpsl_fem_twi_drv_impl_xfer_write_async call, |
| 69 | + * that started the transfer. |
| 70 | + */ |
| 71 | + drv->fem_twi_async_xfwr_write_cb(drv, res, drv->fem_twi_async_xfwr_write_cb_ctx); |
| 72 | +} |
| 73 | + |
| 74 | +static int32_t mpsl_fem_twi_drv_impl_xfer_write_async(void *p_instance, uint8_t slave_address, |
| 75 | + const uint8_t *p_data, uint8_t data_length, |
| 76 | + mpsl_fem_twi_async_xfer_write_cb_t p_callback, |
| 77 | + void *p_context) |
13 | 78 | { |
14 | | - const struct device *dev = (const struct device *)p_instance; |
| 79 | + mpsl_fem_twi_drv_t *drv = (mpsl_fem_twi_drv_t *)p_instance; |
| 80 | + const struct i2c_nrfx_twim_common_config *config = drv->dev->config; |
| 81 | + |
| 82 | + /* At this moment the exclusive access to the drv->dev should have been already acquired. |
| 83 | + * No ongoing twi transfers are expected. Because of that it is safe to replace |
| 84 | + * original event handler of the TWIM with custom one, perform twim transfer and then |
| 85 | + * restore the original event handler. |
| 86 | + */ |
| 87 | + |
| 88 | + nrfx_twim_xfer_desc_t cur_xfer = { |
| 89 | + .address = slave_address, |
| 90 | + .type = NRFX_TWIM_XFER_TX, |
| 91 | + .p_primary_buf = (uint8_t *)p_data, |
| 92 | + .primary_length = data_length, |
| 93 | + }; |
| 94 | + nrfx_err_t err; |
| 95 | + int32_t ret = 0; |
| 96 | + |
| 97 | + drv->fem_twi_async_xfwr_write_cb = p_callback; |
| 98 | + drv->fem_twi_async_xfwr_write_cb_ctx = p_context; |
15 | 99 |
|
16 | | - return i2c_burst_read(dev, slave_address, internal_address, p_data, data_length); |
| 100 | + mpsl_fem_twi_drv_nrfx_twim_callback_replace(drv, mpsl_fem_twi_drv_nrfx_twim_evt_handler); |
| 101 | + |
| 102 | + err = nrfx_twim_xfer(&config->twim, &cur_xfer, 0); |
| 103 | + |
| 104 | + if (err != NRFX_SUCCESS) { |
| 105 | + mpsl_fem_twi_drv_nrfx_twim_callback_restore(drv); |
| 106 | + if (err == NRFX_ERROR_BUSY) { |
| 107 | + ret = -EBUSY; |
| 108 | + } else { |
| 109 | + ret = -EIO; |
| 110 | + } |
| 111 | + } |
| 112 | + |
| 113 | + return ret; |
17 | 114 | } |
18 | 115 |
|
19 | | -int32_t mpsl_fem_twi_drv_impl_xfer_write(void *p_instance, uint8_t slave_address, |
20 | | - uint8_t internal_address, const uint8_t *p_data, uint8_t data_length) |
| 116 | +static uint32_t mpsl_fem_twi_drv_frequency_hz_get(mpsl_fem_twi_drv_t *drv) |
21 | 117 | { |
22 | | - const struct device *dev = (const struct device *)p_instance; |
| 118 | + const struct i2c_nrfx_twim_common_config *config = drv->dev->config; |
| 119 | + |
| 120 | + switch (config->twim_config.frequency) { |
| 121 | + case NRF_TWIM_FREQ_100K: |
| 122 | + return 100000; |
| 123 | + case NRF_TWIM_FREQ_250K: |
| 124 | + return 250000; |
| 125 | + case NRF_TWIM_FREQ_400K: |
| 126 | + return 400000; |
| 127 | +#if NRF_TWIM_HAS_1000_KHZ_FREQ |
| 128 | + case NRF_TWIM_FREQ_1000K: |
| 129 | + return 1000000; |
| 130 | +#endif |
| 131 | + default: |
| 132 | + __ASSERT_NO_MSG(false); |
| 133 | + return 100000; |
| 134 | + } |
| 135 | +} |
23 | 136 |
|
24 | | - return i2c_burst_write(dev, slave_address, internal_address, p_data, data_length); |
| 137 | +static uint32_t mpsl_fem_twi_drv_impl_xfer_write_async_time_get(void *p_instance, |
| 138 | + uint8_t data_length) |
| 139 | +{ |
| 140 | + mpsl_fem_twi_drv_t *drv = (mpsl_fem_twi_drv_t *)p_instance; |
| 141 | + |
| 142 | + static const uint32_t sw_overhead_safety_margin_time_us = 10U; |
| 143 | + /* Note: on nRF5 devices the first bit of each data octet is delayed by one period, |
| 144 | + * thus +1 below. |
| 145 | + */ |
| 146 | + static const uint32_t i2c_data_byte_sck_periods_with_ack = 1U + 8U + 1U; |
| 147 | + static const uint32_t i2c_start_bit_sck_periods = 2U; |
| 148 | + static const uint32_t i2c_stop_bit_sck_periods = 2U; |
| 149 | + uint32_t i2c_sck_frequency_hz = mpsl_fem_twi_drv_frequency_hz_get(drv); |
| 150 | + |
| 151 | + /* Total number of sck periods needed to perform a write transfer. */ |
| 152 | + uint32_t total_periods = i2c_start_bit_sck_periods |
| 153 | + + (data_length + 1U) * i2c_data_byte_sck_periods_with_ack |
| 154 | + + i2c_stop_bit_sck_periods; |
| 155 | + |
| 156 | + return (total_periods * 1000000 / i2c_sck_frequency_hz) + sw_overhead_safety_margin_time_us; |
| 157 | +} |
| 158 | + |
| 159 | +void mpsl_fem_twi_drv_fem_twi_if_prepare(mpsl_fem_twi_drv_t *drv, mpsl_fem_twi_if_t *twi_if, |
| 160 | + uint8_t address) |
| 161 | +{ |
| 162 | + twi_if->enabled = true; |
| 163 | + twi_if->slave_address = address; |
| 164 | + twi_if->p_instance = (void *)drv; |
| 165 | + twi_if->p_xfer_read = mpsl_fem_twi_drv_impl_xfer_read; |
| 166 | + twi_if->p_xfer_write = mpsl_fem_twi_drv_impl_xfer_write; |
| 167 | +} |
| 168 | + |
| 169 | +void mpsl_fem_twi_drv_fem_twi_if_prepare_add_async(mpsl_fem_twi_if_t *twi_if) |
| 170 | +{ |
| 171 | + twi_if->p_xfer_write_async = mpsl_fem_twi_drv_impl_xfer_write_async; |
| 172 | + twi_if->p_xfer_write_async_time_get = mpsl_fem_twi_drv_impl_xfer_write_async_time_get; |
25 | 173 | } |
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