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tests: benchmarks: multicore: add idle_clock_control
Checking s2ram while changing clocks. Signed-off-by: Piotr Kosycarz <[email protected]>
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‎tests/benchmarks/multicore/idle_clock_control/CMakeLists.txt‎

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#
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# Copyright (c) 2024 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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if(NOT SYSBUILD)
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message(FATAL_ERROR
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" This is a multi-image application that should be built using sysbuild.\n"
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" Add --sysbuild argument to west build command to prepare all the images.")
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endif()
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project(idle_clock_control)
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target_sources(app PRIVATE src/main.c)

‎tests/benchmarks/multicore/idle_clock_control/Kconfig.sysbuild‎

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#
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# Copyright (c) 2024 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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source "${ZEPHYR_BASE}/share/sysbuild/Kconfig"
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config REMOTE_BOARD
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string "The board used for remote target"

‎tests/benchmarks/multicore/idle_clock_control/prj.conf‎

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CONFIG_PM=y
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CONFIG_PM_S2RAM=y
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CONFIG_PM_S2RAM_CUSTOM_MARKING=y
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CONFIG_PM_DEVICE=y
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CONFIG_PM_DEVICE_RUNTIME=y
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CONFIG_POWEROFF=y
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CONFIG_GPIO=n
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CONFIG_BOOT_BANNER=n
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CONFIG_SOC_NRF54H20_NO_MRAM_LATENCY=n
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CONFIG_NRFS=y
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CONFIG_CLOCK_CONTROL=y
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CONFIG_ASSERT=y
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# Enable for debugging purposes only
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CONFIG_PRINTK=n
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CONFIG_LOG=n
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CONFIG_CONSOLE=n
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CONFIG_UART_CONSOLE=n
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CONFIG_SERIAL=n

‎tests/benchmarks/multicore/idle_clock_control/remote/CMakeLists.txt‎

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#
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# Copyright (c) 2024 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(remote)
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target_sources(app PRIVATE src/main.c)

‎tests/benchmarks/multicore/idle_clock_control/remote/prj.conf‎

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CONFIG_PM=y
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CONFIG_POWEROFF=y
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CONFIG_CONSOLE=n
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CONFIG_UART_CONSOLE=n
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CONFIG_SERIAL=n
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CONFIG_GPIO=n
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CONFIG_BOOT_BANNER=n
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CONFIG_SOC_NRF54H20_NO_MRAM_LATENCY=n

‎tests/benchmarks/multicore/idle_clock_control/remote/src/main.c‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#include <zephyr/kernel.h>
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int main(void)
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{
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k_sleep(K_FOREVER);
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return 0;
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}

‎tests/benchmarks/multicore/idle_clock_control/src/main.c‎

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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/sys/printk.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/devicetree/clocks.h>
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#include <zephyr/drivers/clock_control/nrf_clock_control.h>
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LOG_MODULE_REGISTER(idle_clock_control);
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struct test_clk_ctx {
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const struct device *clk_dev;
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const struct nrf_clock_spec *clk_specs;
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size_t clk_specs_size;
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};
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const struct nrf_clock_spec test_clk_specs_hsfll[] = {
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{
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.frequency = MHZ(128),
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.accuracy = 0,
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.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
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},
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{
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.frequency = MHZ(320),
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.accuracy = 0,
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.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
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},
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{
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.frequency = MHZ(64),
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.accuracy = 0,
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.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
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},
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};
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const struct nrf_clock_spec test_clk_specs_fll16m[] = {
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{
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.frequency = MHZ(16),
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.accuracy = 20000,
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.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
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},
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{
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.frequency = MHZ(16),
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.accuracy = 5020,
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.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
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},
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{
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.frequency = MHZ(16),
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.accuracy = 30,
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.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
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},
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};
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static const struct test_clk_ctx fll16m_test_clk_ctx[] = {
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{
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.clk_dev = DEVICE_DT_GET(DT_NODELABEL(fll16m)),
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.clk_specs = test_clk_specs_fll16m,
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.clk_specs_size = ARRAY_SIZE(test_clk_specs_fll16m),
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},
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};
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static const struct test_clk_ctx hsfll_test_clk_ctx[] = {
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{
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.clk_dev = DEVICE_DT_GET(DT_NODELABEL(cpuapp_hsfll)),
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.clk_specs = test_clk_specs_hsfll,
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.clk_specs_size = ARRAY_SIZE(test_clk_specs_hsfll),
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},
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};
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const struct nrf_clock_spec test_clk_specs_lfclk[] = {
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{
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.frequency = 32768,
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.accuracy = 0,
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.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
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},
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{
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.frequency = 32768,
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.accuracy = 20,
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.precision = NRF_CLOCK_CONTROL_PRECISION_DEFAULT,
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},
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{
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.frequency = 32768,
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.accuracy = 20,
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.precision = NRF_CLOCK_CONTROL_PRECISION_HIGH,
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},
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};
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static const struct test_clk_ctx lfclk_test_clk_ctx[] = {
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{
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.clk_dev = DEVICE_DT_GET(DT_NODELABEL(lfclk)),
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.clk_specs = test_clk_specs_lfclk,
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.clk_specs_size = ARRAY_SIZE(test_clk_specs_lfclk),
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},
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};
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static void test_request_release_clock_spec(const struct device *clk_dev,
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const struct nrf_clock_spec *clk_spec)
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{
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int ret = 0;
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int res = 0;
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struct onoff_client cli;
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uint32_t rate;
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LOG_INF("Clock under test: %s", clk_dev->name);
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sys_notify_init_spinwait(&cli.notify);
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ret = nrf_clock_control_request(clk_dev, clk_spec, &cli);
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__ASSERT_NO_MSG(ret == 0);
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do {
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ret = sys_notify_fetch_result(&cli.notify, &res);
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k_yield();
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} while (ret == -EAGAIN);
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__ASSERT_NO_MSG(ret == 0);
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__ASSERT_NO_MSG(res == 0);
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ret = clock_control_get_rate(clk_dev, NULL, &rate);
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__ASSERT_NO_MSG(ret == 0);
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__ASSERT_NO_MSG(rate == clk_spec->frequency);
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k_busy_wait(10000);
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ret = nrf_clock_control_release(clk_dev, clk_spec);
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__ASSERT_NO_MSG(ret == ONOFF_STATE_ON);
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}
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static void test_clock_control_request(const struct test_clk_ctx *clk_contexts,
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size_t contexts_size)
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{
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const struct test_clk_ctx *clk_context;
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size_t clk_specs_size;
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const struct device *clk_dev;
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const struct nrf_clock_spec *clk_spec;
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for (size_t i = 0; i < contexts_size; i++) {
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clk_context = &clk_contexts[i];
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clk_specs_size = clk_context->clk_specs_size;
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for (size_t u = 0; u < clk_specs_size; u++) {
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clk_dev = clk_context->clk_dev;
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clk_spec = &clk_context->clk_specs[u];
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LOG_INF("Applying clock (%s) spec: frequency %d, accuracy %d, precision "
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"%d",
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clk_dev->name, clk_spec->frequency, clk_spec->accuracy,
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clk_spec->precision);
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test_request_release_clock_spec(clk_dev, clk_spec);
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k_msleep(1000);
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}
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}
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}
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int main(void)
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{
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LOG_INF("Idle clock_control, %s", CONFIG_BOARD_TARGET);
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k_msleep(100);
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while (1) {
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test_clock_control_request(hsfll_test_clk_ctx, ARRAY_SIZE(hsfll_test_clk_ctx));
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test_clock_control_request(fll16m_test_clk_ctx, ARRAY_SIZE(fll16m_test_clk_ctx));
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test_clock_control_request(lfclk_test_clk_ctx, ARRAY_SIZE(lfclk_test_clk_ctx));
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}
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return 0;
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}

‎tests/benchmarks/multicore/idle_clock_control/sysbuild.cmake‎

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#
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# Copyright (c) 2024 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
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#
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if("${SB_CONFIG_REMOTE_BOARD}" STREQUAL "")
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message(FATAL_ERROR "REMOTE_BOARD must be set to a valid board name")
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endif()
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# Add remote project
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ExternalZephyrProject_Add(
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APPLICATION remote
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SOURCE_DIR ${APP_DIR}/remote
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BOARD ${SB_CONFIG_REMOTE_BOARD}
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BOARD_REVISION ${BOARD_REVISION}
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)
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# Add a dependency so that the remote image will be built and flashed first
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add_dependencies(idle_clock_control remote)
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# Add dependency so that the remote image is flashed first.
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sysbuild_add_dependencies(FLASH idle_clock_control remote)

‎tests/benchmarks/multicore/idle_clock_control/sysbuild/nrf54h20dk_nrf54h20_cpurad.conf‎

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SB_CONFIG_REMOTE_BOARD="nrf54h20dk/nrf54h20/cpurad"

‎tests/benchmarks/multicore/idle_clock_control/testcase.yaml‎

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common:
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sysbuild: true
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tags: ci_build ci_tests_benchmarks_multicore ppk_power_measure
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tests:
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benchmarks.multicore.idle_clock_control:
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harness: pytest
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platform_allow:
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- nrf54h20dk/nrf54h20/cpuapp
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integration_platforms:
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- nrf54h20dk/nrf54h20/cpuapp
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extra_args:
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- SB_CONF_FILE=sysbuild/nrf54h20dk_nrf54h20_cpurad.conf
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harness_config:
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fixture: ppk_power_measure
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pytest_root:
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- "${CUSTOM_ROOT_TEST_DIR}/test_measure_power_consumption.py::test_measure_and_data_dump_power_consumption_clock_control"
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timeout: 90

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