debug: cpu_load: Align to the new GPPI API

Additionally, removed support for PPI resources cleanup in case
of failed allocation. cpu_load is a debug feature and if allocation
fails then there is something wrong with the configuration and
configuration shall be fixed or cpu_load disabled.

Signed-off-by: Krzysztof Chruściński <[email protected]>

Author: nordic-krch

subsys/debug/cpu_load/cpu_load.c

@@ -34,64 +34,6 @@ static nrfx_timer_t timer =
 static bool ready;
 static struct k_work_delayable cpu_load_log;
 static uint32_t cycle_ref;
-static uint32_t shared_ch_mask;
-
-#define IS_CH_SHARED(ch) \
-	(IS_ENABLED(CONFIG_NRF_CPU_LOAD_USE_SHARED_DPPI_CHANNELS) && \
-	(BIT(ch) & shared_ch_mask))
-
-
-/** @brief Allocate (D)PPI channel. */
-static nrfx_err_t ppi_alloc(uint8_t *ch, uint32_t evt)
-{
-#ifdef DPPI_PRESENT
-	if (*PUBLISH_ADDR(evt) != 0) {
-		if (!IS_ENABLED(CONFIG_NRF_CPU_LOAD_USE_SHARED_DPPI_CHANNELS)) {
-			return NRFX_ERROR_BUSY;
-		}
-		/* Use mask of one of subscribe registers in the system,
-		 * assuming that all subscribe registers has the same mask for
-		 * channel id.
-		 */
-		*ch = *PUBLISH_ADDR(evt) & DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk;
-		shared_ch_mask |= BIT(*ch);
-		return NRFX_SUCCESS;
-	}
-#endif
-	return nrfx_gppi_channel_alloc(ch);
-}
-
-static nrfx_err_t ppi_free(uint8_t ch)
-{
-#ifdef DPPI_PRESENT
-	if (IS_CH_SHARED(ch)) {
-		shared_ch_mask &= ~BIT(ch);
-		return NRFX_SUCCESS;
-	}
-#endif
-	return nrfx_gppi_channel_free(ch);
-}
-
-static void ppi_cleanup(uint8_t ch_tick, uint8_t ch_sleep, uint8_t ch_wakeup)
-{
-	nrfx_err_t err = NRFX_SUCCESS;
-
-	if (IS_ENABLED(CONFIG_NRF_CPU_LOAD_ALIGNED_CLOCKS)) {
-		err = ppi_free(ch_tick);
-	}
-
-	if ((err == NRFX_SUCCESS) && (ch_sleep != CH_INVALID)) {
-		err = ppi_free(ch_sleep);
-	}
-
-	if ((err == NRFX_SUCCESS) && (ch_wakeup != CH_INVALID)) {
-		err = ppi_free(ch_wakeup);
-	}
-
-	if (err != NRFX_SUCCESS) {
-		LOG_ERR("PPI channel freeing failed (err:%d)", err);
-	}
-}
 
 static void cpu_load_log_fn(struct k_work *item)
 {
@@ -120,12 +62,43 @@ static void timer_handler(nrf_timer_event_t event_type, void *context)
 	/*empty*/
 }
 
+static int ppi_handle_get(uint32_t evt)
+{
+#ifdef DPPI_PRESENT
+	if (*PUBLISH_ADDR(evt) != 0) {
+		if (!IS_ENABLED(CONFIG_NRF_CPU_LOAD_USE_SHARED_DPPI_CHANNELS)) {
+			return -ENOTSUP;
+		}
+		return *PUBLISH_ADDR(evt) & DPPIC_SUBSCRIBE_CHG_EN_CHIDX_Msk;
+	}
+#endif
+	return -ENOTSUP;
+}
+static int ppi_setup(uint32_t eep, uint32_t tep)
+{
+	nrfx_gppi_handle_t handle;
+	int err;
+
+	err = ppi_handle_get(eep);
+	if (err >= 0) {
+		/* It works only on single domain DPPI. */
+		handle = (nrfx_gppi_handle_t)err;
+		nrfx_gppi_ep_attach(handle, tep);
+		return 0;
+	}
+
+	err = nrfx_gppi_conn_alloc(eep, tep, &handle);
+	if (err < 0) {
+		LOG_ERR("Failed to allocate PPI resources");
+		return err;
+	}
+
+	nrfx_gppi_conn_enable(handle);
+	return 0;
+}
 
 int cpu_load_init_internal(void)
 {
-	uint8_t ch_sleep;
-	uint8_t ch_wakeup;
-	uint8_t ch_tick = 0;
 	nrfx_err_t err;
 	uint32_t base_frequency = NRF_TIMER_BASE_FREQUENCY_GET(timer.p_reg);
 	nrfx_timer_config_t config = NRFX_TIMER_DEFAULT_CONFIG(base_frequency);
@@ -141,57 +114,31 @@ int cpu_load_init_internal(void)
 #ifdef CONFIG_NRF_CPU_LOAD_ALIGNED_CLOCKS
 	/* It's assumed that RTC1 is driving system clock. */
 	config.mode = NRF_TIMER_MODE_COUNTER;
-	err = ppi_alloc(&ch_tick,
-	       nrf_rtc_event_address_get(NRF_RTC1, NRF_RTC_EVENT_TICK));
-	if (err != NRFX_SUCCESS) {
-		return -ENODEV;
+	ret = ppi_setup(nrf_rtc_event_address_get(NRF_RTC1, NRF_RTC_EVENT_TICK),
+			nrfx_timer_task_address_get(&timer, NRF_TIMER_TASK_COUNT));
+	if (ret < 0) {
+		return ret;
 	}
-	nrfx_gppi_channel_endpoints_setup(ch_tick,
-	     nrf_rtc_event_address_get(NRF_RTC1, NRF_RTC_EVENT_TICK),
-	     nrfx_timer_task_address_get(&timer, NRF_TIMER_TASK_COUNT));
 	nrf_rtc_event_enable(NRF_RTC1, NRF_RTC_INT_TICK_MASK);
 #endif
 
-	err = ppi_alloc(&ch_sleep,
-		       nrf_power_event_address_get(NRF_POWER,
-						   NRF_POWER_EVENT_SLEEPENTER));
-	if (err != NRFX_SUCCESS) {
-		ppi_cleanup(ch_tick, CH_INVALID, CH_INVALID);
-		return -ENODEV;
+	ret = ppi_setup(nrf_power_event_address_get(NRF_POWER, NRF_POWER_EVENT_SLEEPENTER),
+			nrfx_timer_task_address_get(&timer, NRF_TIMER_TASK_START));
+	if (ret < 0) {
+		return ret;
 	}
 
-	err = ppi_alloc(&ch_wakeup,
-		       nrf_power_event_address_get(NRF_POWER,
-						   NRF_POWER_EVENT_SLEEPEXIT));
-	if (err != NRFX_SUCCESS) {
-		ppi_cleanup(ch_tick, ch_sleep, CH_INVALID);
-		return -ENODEV;
+	ret = ppi_setup(nrf_power_event_address_get(NRF_POWER, NRF_POWER_EVENT_SLEEPEXIT),
+			nrfx_timer_task_address_get(&timer, NRF_TIMER_TASK_STOP));
+	if (ret < 0) {
+		return ret;
 	}
 
 	err = nrfx_timer_init(&timer, &config, timer_handler);
 	if (err != NRFX_SUCCESS) {
-		ppi_cleanup(ch_tick, ch_sleep, ch_wakeup);
 		return -EBUSY;
 	}
 
-	nrfx_gppi_channel_endpoints_setup(ch_sleep,
-		  nrf_power_event_address_get(NRF_POWER,
-					      NRF_POWER_EVENT_SLEEPENTER),
-		  nrfx_timer_task_address_get(&timer, NRF_TIMER_TASK_START));
-	nrfx_gppi_channel_endpoints_setup(ch_wakeup,
-		  nrf_power_event_address_get(NRF_POWER,
-					      NRF_POWER_EVENT_SLEEPEXIT),
-		  nrfx_timer_task_address_get(&timer, NRF_TIMER_TASK_STOP));
-
-	/* In case of DPPI event can only be assigned to a single channel. In
-	 * that case, cpu load can still subscribe to the channel but should
-	 * not control it. It may result in cpu load not working. User must
-	 * take care of that.
-	 */
-	nrfx_gppi_channels_enable((IS_CH_SHARED(ch_sleep) ? 0 : BIT(ch_sleep)) |
-				(IS_CH_SHARED(ch_wakeup) ? 0 : BIT(ch_wakeup)) |
-				(IS_CH_SHARED(ch_tick) ? 0 : BIT(ch_tick)));
-
 	cpu_load_reset();
 
 	if (IS_ENABLED(CONFIG_NRF_CPU_LOAD_LOG_PERIODIC)) {

tests/subsys/debug/cpu_load/src/test_cpu_load.c

@@ -13,7 +13,6 @@
 #include <hal/nrf_power.h>
 
 #ifdef CONFIG_NRF_CPU_LOAD_USE_SHARED_DPPI_CHANNELS
-#include <nrfx_dppi.h>
 
 static void timer_handler(nrf_timer_event_t event_type, void *context)
 {
@@ -26,22 +25,22 @@ static int dppi_shared_resources_init(void)
 	static nrfx_timer_t timer = NRFX_TIMER_INSTANCE(NRF_TIMER1);
 	uint32_t base_frequency = NRF_TIMER_BASE_FREQUENCY_GET(timer.p_reg);
 	nrfx_timer_config_t config = NRFX_TIMER_DEFAULT_CONFIG(base_frequency);
-	uint8_t ch;
+	nrfx_gppi_handle_t handle;
 	uint32_t evt = nrf_power_event_address_get(NRF_POWER,
 						NRF_POWER_EVENT_SLEEPENTER);
 	uint32_t tsk = nrfx_timer_task_address_get(&timer, NRF_TIMER_TASK_COUNT);
+	int rv;
 
 	config.frequency = NRFX_MHZ_TO_HZ(1);
 	config.bit_width = NRF_TIMER_BIT_WIDTH_32;
 
 	err = nrfx_timer_init(&timer, &config, timer_handler);
 	zassert_equal(err, NRFX_SUCCESS, "Unexpected error:%d", err);
 
-	err = nrfx_gppi_channel_alloc(&ch);
-	zassert_equal(err, NRFX_SUCCESS, "Unexpected error:%d", err);
+	rv = nrfx_gppi_conn_alloc(evt, tsk, &handle);
+	zassert_equal(rv, 0);
 
-	nrfx_gppi_channel_endpoints_setup(ch, evt, tsk);
-	nrfx_gppi_channels_enable(BIT(ch));
+	nrfx_gppi_conn_enable(handle);
 
 	return 0;
 }