@@ -21,12 +21,13 @@ LOG_MODULE_REGISTER(mspi_nrfe, CONFIG_MSPI_LOG_LEVEL);
2121#include <hal/nrf_gpio.h>
2222#include <drivers/mspi/nrfe_mspi.h>
2323
24- #define MSPI_NRFE_NODE DT_DRV_INST(0)
25- #define MAX_TX_MSG_SIZE (DT_REG_SIZE(DT_NODELABEL(sram_tx)))
26- #define MAX_RX_MSG_SIZE (DT_REG_SIZE(DT_NODELABEL(sram_rx)))
27- #define IPC_TIMEOUT_MS 100
28- #define EP_SEND_TIMEOUT_MS 10
29- #define CNT0_TOP_CALCULATE (freq ) (NRFX_CEIL_DIV(SystemCoreClock, freq * 2) - 1)
24+ #define MSPI_NRFE_NODE DT_DRV_INST(0)
25+ #define MAX_TX_MSG_SIZE (DT_REG_SIZE(DT_NODELABEL(sram_tx)))
26+ #define MAX_RX_MSG_SIZE (DT_REG_SIZE(DT_NODELABEL(sram_rx)))
27+ #define IPC_TIMEOUT_MS 100
28+ #define EP_SEND_TIMEOUT_MS 10
29+ #define EXTREME_DRIVE_FREQ_THRESHOLD 32000000
30+ #define CNT0_TOP_CALCULATE (freq ) (NRFX_CEIL_DIV(SystemCoreClock, freq * 2) - 1)
3031
3132#define SDP_MPSI_PINCTRL_DEV_CONFIG_INIT (node_id ) \
3233 { \
@@ -439,6 +440,23 @@ static int api_dev_config(const struct device *dev, const struct mspi_dev_id *de
439440 }
440441
441442 if (param_mask & MSPI_DEVICE_CONFIG_FREQUENCY ) {
443+
444+ uint8_t state_id ;
445+
446+ for (state_id = 0 ; state_id < drv_cfg -> pcfg -> state_cnt ; state_id ++ ) {
447+ if (drv_cfg -> pcfg -> states [state_id ].id == PINCTRL_STATE_DEFAULT ) {
448+ break ;
449+ }
450+ }
451+
452+ if ((cfg -> freq >= EXTREME_DRIVE_FREQ_THRESHOLD ) &&
453+ (NRF_GET_DRIVE (drv_cfg -> pcfg -> states [state_id ].pins [0 ]) != NRF_DRIVE_E0E1 )) {
454+ LOG_ERR ("Invalid pin drive for this frequency: %u, expected: %u" ,
455+ NRF_GET_DRIVE (drv_cfg -> pcfg -> states [state_id ].pins [0 ]),
456+ NRF_DRIVE_E0E1 );
457+ return - EINVAL ;
458+ }
459+
442460 if (cfg -> freq > drv_cfg -> mspicfg .max_freq ) {
443461 LOG_ERR ("Invalid frequency: %u, MAX: %u" , cfg -> freq ,
444462 drv_cfg -> mspicfg .max_freq );
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