snippets: nordic: Add FLPR core support for nRF54LV10A

FLPR core support for nRF54LV10A devices.

Signed-off-by: Adam Kondraciuk <[email protected]>

Author: adamkondraciuk

snippets/nordic-flpr/snippet.yml

@@ -6,3 +6,6 @@ boards:
   /.*/nrf54lm20a/cpuapp/:
     append:
       EXTRA_DTC_OVERLAY_FILE: soc/nrf54lm20a_cpuapp.overlay
+  /.*/nrf54lv10a/cpuapp/:
+    append:
+      EXTRA_DTC_OVERLAY_FILE: soc/nrf54lv10a_cpuapp.overlay

snippets/nordic-flpr/soc/nrf54lv10a_cpuapp.overlay

@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/ {
+	soc {
+		reserved-memory {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			cpuflpr_code_partition: image@ed000 {
+				/* FLPR core code partition */
+				reg = <0xed000 DT_SIZE_K(64)>;
+			};
+		};
+
+		cpuflpr_sram_code_data: memory@2001fc00 {
+			compatible = "mmio-sram";
+			reg = <0x2001fc00 DT_SIZE_K(64)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0x2001fc00 DT_SIZE_K(64)>;
+		};
+	};
+};
+
+&cpuapp_sram {
+	reg = <0x20000000 DT_SIZE_K(127)>;
+	ranges = <0x0 0x20000000 DT_SIZE_K(127)>;
+};
+
+&uart30 {
+	status = "reserved";
+};
+
+&cpuflpr_vpr {
+	execution-memory = <&cpuflpr_sram_code_data>;
+	source-memory = <&cpuflpr_code_partition>;
+};
+
+&cpuapp_vevif_tx {
+	status = "okay";
+};