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jaz1-nordicmasz-nordic
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applications: sdp: mspi: Add IPC solution to SDP MSPI application
Add IPC solution based on icmsg to application for FLPR core to communicate with SDP MSPI driver. Signed-off-by: Jakub Zymelka <[email protected]>
1 parent 39f3adf commit ee0ab07

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6 files changed

+236
-78
lines changed

6 files changed

+236
-78
lines changed

‎applications/sdp/mspi/boards/nrf54l15dk_nrf54l15_cpuflpr.overlay‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,58 @@
44
* SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
55
*/
66

7+
/ {
8+
soc {
9+
reserved-memory {
10+
#address-cells = <1>;
11+
#size-cells = <1>;
12+
13+
sram_tx: memory@2003c000 {
14+
reg = <0x2003c000 0x0800>;
15+
};
16+
17+
sram_rx: memory@2003c800 {
18+
reg = <0x2003c800 0x0800>;
19+
};
20+
};
21+
};
22+
23+
ipc {
24+
ipc0: ipc0 {
25+
compatible = "zephyr,ipc-icmsg";
26+
tx-region = <&sram_tx>;
27+
rx-region = <&sram_rx>;
28+
mboxes = <&cpuflpr_vevif_rx 16>, <&cpuflpr_vevif_tx 20>;
29+
mbox-names = "rx", "tx";
30+
status = "okay";
31+
};
32+
};
33+
};
34+
35+
&cpuflpr_rram {
36+
reg = <0x17a000 DT_SIZE_K(12)>;
37+
};
38+
39+
&cpuflpr_code_partition {
40+
reg = <0x0 DT_SIZE_K(12)>;
41+
};
42+
43+
&cpuflpr_sram {
44+
reg = <0x2003d000 DT_SIZE_K(12)>;
45+
ranges = <0x0 0x2003d000 0x3000>;
46+
};
47+
48+
&cpuflpr_vevif_rx {
49+
status = "okay";
50+
interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>;
51+
nordic,tasks = <1>;
52+
nordic,tasks-mask = <0x00010000>;
53+
};
54+
55+
&cpuflpr_vevif_tx {
56+
status = "okay";
57+
};
58+
759
&gpio0 {
860
status = "disabled";
961
};

‎applications/sdp/mspi/prj.conf‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
1-
CONFIG_MBOX=n
2-
CONFIG_IPC_SERVICE=n
3-
CONFIG_IPC_SERVICE_BACKEND_ICMSG=n
1+
CONFIG_MBOX=y
2+
CONFIG_IPC_SERVICE=y
3+
CONFIG_IPC_SERVICE_BACKEND_ICMSG=y

‎applications/sdp/mspi/sample.yaml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ common:
55
integration_platforms:
66
- nrf54l15dk/nrf54l15/cpuflpr
77
tests:
8-
applications.sdp.mspi.icmsg:
8+
applications.sdp.mspi:
99
build_only: true
1010
sysbuild: true
1111
platform_allow: nrf54l15dk/nrf54l15/cpuflpr

‎applications/sdp/mspi/src/hrt/hrt.c‎

Lines changed: 26 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -22,12 +22,10 @@ void write_single_by_word(volatile struct hrt_ll_xfer xfer_ll_params)
2222
NRFX_ASSERT(xfer_ll_params.word_size <= MAX_WORD_SIZE);
2323
/* Configuration step */
2424
dir = nrf_vpr_csr_vio_dir_get();
25-
26-
nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(D0_PIN));
25+
nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)));
2726

2827
out = nrf_vpr_csr_vio_out_get();
29-
30-
nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(D0_PIN));
28+
nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)));
3129

3230
nrf_vpr_csr_vio_mode_out_set(&out_mode);
3331
nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
@@ -59,9 +57,9 @@ void write_single_by_word(volatile struct hrt_ll_xfer xfer_ll_params)
5957

6058
/* Enable CS */
6159
out = nrf_vpr_csr_vio_out_get();
62-
out &= ~PIN_OUT_HIGH_MASK(CS_PIN);
63-
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_HIGH_MASK(CS_PIN)
64-
: PIN_OUT_LOW_MASK(CS_PIN);
60+
out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
61+
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
62+
: PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
6563
nrf_vpr_csr_vio_out_set(out);
6664

6765
/* Start counter */
@@ -84,9 +82,11 @@ void write_single_by_word(volatile struct hrt_ll_xfer xfer_ll_params)
8482
/* Disable CS */
8583
if (!xfer_ll_params.ce_hold) {
8684
out = nrf_vpr_csr_vio_out_get();
87-
out &= ~(PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_HIGH_MASK(SCLK_PIN));
88-
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_LOW_MASK(CS_PIN)
89-
: PIN_OUT_HIGH_MASK(CS_PIN);
85+
out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
86+
PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
87+
out |= xfer_ll_params.ce_enable_state
88+
? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
89+
: PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
9090
nrf_vpr_csr_vio_out_set(out);
9191
}
9292

@@ -109,13 +109,17 @@ void write_quad_by_word(volatile struct hrt_ll_xfer xfer_ll_params)
109109
/* Configuration step */
110110
dir = nrf_vpr_csr_vio_dir_get();
111111

112-
nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(D0_PIN) | PIN_DIR_OUT_MASK(D1_PIN) |
113-
PIN_DIR_OUT_MASK(D2_PIN) | PIN_DIR_OUT_MASK(D3_PIN));
112+
nrf_vpr_csr_vio_dir_set(dir | PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
113+
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) |
114+
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) |
115+
PIN_DIR_OUT_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER)));
114116

115117
out = nrf_vpr_csr_vio_out_get();
116118

117-
nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(D0_PIN) | PIN_OUT_LOW_MASK(D1_PIN) |
118-
PIN_OUT_LOW_MASK(D2_PIN) | PIN_OUT_LOW_MASK(D3_PIN));
119+
nrf_vpr_csr_vio_out_set(out | PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ0_PIN_NUMBER)) |
120+
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ1_PIN_NUMBER)) |
121+
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ2_PIN_NUMBER)) |
122+
PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_DQ3_PIN_NUMBER)));
119123

120124
nrf_vpr_csr_vio_mode_out_set(&out_mode);
121125
nrf_vpr_csr_vio_mode_in_buffered_set(NRF_VPR_CSR_VIO_MODE_IN_CONTINUOUS);
@@ -147,9 +151,9 @@ void write_quad_by_word(volatile struct hrt_ll_xfer xfer_ll_params)
147151

148152
/* Enable CS */
149153
out = nrf_vpr_csr_vio_out_get();
150-
out &= ~PIN_OUT_HIGH_MASK(CS_PIN);
151-
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_HIGH_MASK(CS_PIN)
152-
: PIN_OUT_LOW_MASK(CS_PIN);
154+
out &= ~PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
155+
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
156+
: PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
153157
nrf_vpr_csr_vio_out_set(out);
154158

155159
/* Start counter */
@@ -171,9 +175,11 @@ void write_quad_by_word(volatile struct hrt_ll_xfer xfer_ll_params)
171175
/* Disable CS */
172176
if (!xfer_ll_params.ce_hold) {
173177
out = nrf_vpr_csr_vio_out_get();
174-
out &= ~(PIN_OUT_HIGH_MASK(CS_PIN) | PIN_OUT_HIGH_MASK(SCLK_PIN));
175-
out |= xfer_ll_params.ce_enable_state ? PIN_OUT_LOW_MASK(CS_PIN)
176-
: PIN_OUT_HIGH_MASK(CS_PIN);
178+
out &= ~(PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER)) |
179+
PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_SCK_PIN_NUMBER)));
180+
out |= xfer_ll_params.ce_enable_state
181+
? PIN_OUT_LOW_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER))
182+
: PIN_OUT_HIGH_MASK(VIO(NRFE_MSPI_CS0_PIN_NUMBER));
177183
nrf_vpr_csr_vio_out_set(out);
178184
}
179185

‎applications/sdp/mspi/src/hrt/hrt.h‎

Lines changed: 1 addition & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -9,13 +9,7 @@
99

1010
#include <stdint.h>
1111
#include <stdbool.h>
12-
13-
#define SCLK_PIN 0
14-
#define D0_PIN 1
15-
#define D1_PIN 2
16-
#define D2_PIN 3
17-
#define D3_PIN 4
18-
#define CS_PIN 5
12+
#include <drivers/mspi/nrfe_mspi.h>
1913

2014
/* Max word size. */
2115
#define MAX_WORD_SIZE NRF_VPR_CSR_VIO_SHIFT_CNT_OUT_BUFFERED_MAX

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