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doc: nrf: drivers: Add documentation for sQSPI MSPI shim driver
Add a few words about the purpose of the driver and how to configure it, along with examples of dts overlays for supported SoCs. Signed-off-by: Andrzej Głąbek <[email protected]>
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‎CODEOWNERS‎

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/doc/nrf/drivers/suit_flash_ipuc.rst @nrfconnect/ncs-charon-doc
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/doc/nrf/drivers/images/flash_ipuc/* @nrfconnect/ncs-charon-doc
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/doc/nrf/drivers/hw_cc3xx.rst @nrfconnect/ncs-aegir-doc
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/doc/nrf/drivers/mspi_sqspi.rst @annwoj
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/doc/nrf/drivers/paw3212.rst @nrfconnect/ncs-si-bluebagel-doc
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/doc/nrf/drivers/pmw3360.rst @nrfconnect/ncs-si-bluebagel-doc
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/doc/nrf/drivers/sensor_sim.rst @nrfconnect/ncs-cia-doc

‎doc/nrf/drivers/mspi_sqspi.rst‎

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.. _mspi_sqspi:
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sQSPI MSPI shim driver
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######################
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.. contents::
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:local:
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:depth: 2
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This driver integrates the :ref:`sQSPI` soft peripheral with the Zephyr MSPI API, enabling control over the peripheral.
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This allows for communication with devices that use MSPI bus-based Zephyr drivers, such as flash chips or displays.
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Configuration
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*************
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To configure the sQSPI MSPI shim driver with the devicetree, complete the following steps:
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1. Specify the base address of the sQSPI registers in RAM by creating the :dtcompatible:`nordic,nrf-sqspi` node within the RAM region reserved for the soft peripheral.
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#. Specify an interrupt for communication between the application and FLPR cores, and determine the pins for sQSPI operation.
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Provide this information in the properties of the node labeled as ``cpuflpr_vpr``.
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#. If the ``execution-memory`` property exists in the ``cpuflpr_vpr`` node, delete it to ensure the FLPR core does not use the Nordic VPR coprocessor launcher (see the :kconfig:option:`CONFIG_NORDIC_VPR_LAUNCHER` Kconfig option).
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For RAM configuration details on supported SoCs, refer to the following guides:
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* :ref:`nRF54L15 RAM configuration <nrf54L15_porting_guide_ram_configuration>`
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* :ref:`nRF54H20 RAM configuration <nrf54H20_porting_guide_ram_configuration>` - On the nRF54H20 SoC, ensure the RAM region reserved for the sQSPI is labeled ``softperiph_ram`` to set it as non-cacheable in the MPU configuration.
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See the following configuration example for the nRF54L15 SoC:
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.. code-block:: devicetree
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&pinctrl {
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sqspi_default: sqspi_default {
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group1 {
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psels = <NRF_PSEL(SDP_MSPI_SCK, 2, 1)>,
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<NRF_PSEL(SDP_MSPI_CS0, 2, 5)>,
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<NRF_PSEL(SDP_MSPI_DQ0, 2, 2)>;
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nordic,drive-mode = <NRF_DRIVE_E0E1>;
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};
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group2 {
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psels = <NRF_PSEL(SDP_MSPI_DQ1, 2, 4)>,
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<NRF_PSEL(SDP_MSPI_DQ2, 2, 3)>,
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<NRF_PSEL(SDP_MSPI_DQ3, 2, 0)>;
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nordic,drive-mode = <NRF_DRIVE_E0E1>;
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bias-pull-up;
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};
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};
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sqspi_sleep: sqspi_sleep {
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group1 {
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low-power-enable;
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psels = <NRF_PSEL(SDP_MSPI_SCK, 2, 1)>,
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<NRF_PSEL(SDP_MSPI_CS0, 2, 5)>,
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<NRF_PSEL(SDP_MSPI_DQ0, 2, 2)>,
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<NRF_PSEL(SDP_MSPI_DQ1, 2, 4)>,
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<NRF_PSEL(SDP_MSPI_DQ2, 2, 3)>,
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<NRF_PSEL(SDP_MSPI_DQ3, 2, 0)>;
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};
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};
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};
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&cpuflpr_vpr {
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pinctrl-0 = <&sqspi_default>;
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pinctrl-1 = <&sqspi_sleep>;
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pinctrl-names = "default", "sleep";
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interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>;
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status = "okay";
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};
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/ {
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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softperiph_ram: memory@2003c000 {
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reg = <0x2003c000 0x4000>;
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ranges = <0 0x2003c000 0x4000>;
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#address-cells = <1>;
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#size-cells = <1>;
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sqspi: sqspi@3c00 {
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compatible = "nordic,nrf-sqspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3c00 0x200>;
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status = "okay";
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zephyr,pm-device-runtime-auto;
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};
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};
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};
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};
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For the nRF54H20 SoC, you must also reserve a RAM region for data buffers used in sQSPI transfers, accessible by the FLPR core.
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Indicate this region to the shim driver using the ``memory-regions`` property in the sQSPI node.
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If you initiate an MSPI transfer with a buffer outside this region, the shim driver will temporarily allocate a buffer within the region and correctly transfer data between the two buffers - before transmitting (TX) or after receiving (RX).
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To avoid overhead from automatic allocation and copying, allocate buffers statically using :c:macro:`DMM_MEMORY_SECTION`.
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The shim driver will then directly pass these buffers to the sQSPI.
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The following example configuration for the nRF54H20 SoC sets up the necessary parameters:
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.. code-block:: devicetree
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&pinctrl {
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sqspi_default: sqspi_default {
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group1 {
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psels = <NRF_PSEL(SDP_MSPI_SCK, 7, 0)>,
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<NRF_PSEL(SDP_MSPI_CS0, 7, 5)>,
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<NRF_PSEL(SDP_MSPI_DQ0, 7, 1)>;
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nordic,drive-mode = <NRF_DRIVE_E0E1>;
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};
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group2 {
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psels = <NRF_PSEL(SDP_MSPI_DQ1, 7, 2)>,
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<NRF_PSEL(SDP_MSPI_DQ2, 7, 3)>,
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<NRF_PSEL(SDP_MSPI_DQ3, 7, 4)>;
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nordic,drive-mode = <NRF_DRIVE_E0E1>;
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bias-pull-up;
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};
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};
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sqspi_sleep: sqspi_sleep {
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group1 {
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low-power-enable;
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psels = <NRF_PSEL(SDP_MSPI_SCK, 7, 0)>,
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<NRF_PSEL(SDP_MSPI_CS0, 7, 5)>,
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<NRF_PSEL(SDP_MSPI_DQ0, 7, 1)>,
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<NRF_PSEL(SDP_MSPI_DQ1, 7, 2)>,
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<NRF_PSEL(SDP_MSPI_DQ2, 7, 3)>,
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<NRF_PSEL(SDP_MSPI_DQ3, 7, 4)>;
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};
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};
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};
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&cpuflpr_vpr {
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pinctrl-0 = <&sqspi_default>;
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pinctrl-1 = <&sqspi_sleep>;
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pinctrl-names = "default", "sleep";
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interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>;
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status = "okay";
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/delete-property/ execution-memory;
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};
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/delete-node/ &cpuflpr_code_data;
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/delete-node/ &cpuapp_cpuflpr_ipc_shm;
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/delete-node/ &cpuflpr_cpuapp_ipc_shm;
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/delete-node/ &cpuapp_cpuflpr_ipc;
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&ram21_region {
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status = "okay";
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softperiph_ram: memory@0 {
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reg = <0 0x4000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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sqspi: sqspi@3e00 {
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compatible = "nordic,nrf-sqspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x3e00 0x200>;
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zephyr,pm-device-runtime-auto;
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memory-regions = <&sqspi_buffers>;
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};
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};
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sqspi_buffers: memory@4000 {
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compatible = "zephyr,memory-region";
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reg = <0x4000 0x4000>;
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#memory-region-cells = <0>;
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zephyr,memory-region = "SQSPI_BUFFERS";
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zephyr,memory-attr = <DT_MEM_CACHEABLE>;
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};
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};
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API documentation
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*****************
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| Header file: :file:`include/zephyr/drivers/mspi.h`
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| Source file: :file:`drivers/mspi/mspi_sqspi.c`
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.. doxygengroup:: mspi_interface

‎doc/nrf/releases_and_maturity/releases/release-notes-changelog.rst‎

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This section provides detailed lists of changes by :ref:`driver <drivers>`.
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|no_changes_yet_note|
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* Added the :ref:`mspi_sqspi` that allows for communication with devices that use MSPI bus-based Zephyr drivers.
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Wi-Fi drivers
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-------------

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