diff --git a/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay b/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay
index 3b45642d36cb..8621993af6ee 100644
--- a/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay
+++ b/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_icbmsg.overlay
@@ -34,6 +34,14 @@
 	};
 };
 
+&cpuflpr_rram {
+	reg = <0x179800 DT_SIZE_K(14)>;
+};
+
+&cpuflpr_code_partition {
+	reg = <0x0 DT_SIZE_K(14)>;
+};
+
 &cpuflpr_sram {
 	reg = <0x2003c800 DT_SIZE_K(14)>;
 	ranges = <0x0 0x2003c800 0x3800>;
diff --git a/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_icmsg.overlay b/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_icmsg.overlay
index 4df6ef5eb5aa..9c10b2fb3aa9 100644
--- a/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_icmsg.overlay
+++ b/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_icmsg.overlay
@@ -32,6 +32,14 @@
 	};
 };
 
+&cpuflpr_rram {
+	reg = <0x17a000 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_code_partition {
+	reg = <0x0 DT_SIZE_K(12)>;
+};
+
 &cpuflpr_sram {
 	reg = <0x2003d000 DT_SIZE_K(12)>;
 	ranges = <0x0 0x2003d000 0x3000>;
diff --git a/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_mbox.overlay b/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_mbox.overlay
index 2192394fc45c..2eb0cf2b8282 100644
--- a/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_mbox.overlay
+++ b/applications/sdp/gpio/boards/nrf54l15dk_nrf54l15_cpuflpr_mbox.overlay
@@ -27,6 +27,14 @@
 	};
 };
 
+&cpuflpr_rram {
+	reg = <0x17a000 DT_SIZE_K(12)>;
+};
+
+&cpuflpr_code_partition {
+	reg = <0x0 DT_SIZE_K(12)>;
+};
+
 &cpuflpr_sram {
 	reg = <0x2003d000 DT_SIZE_K(12)>;
 	ranges = <0x0 0x2003d000 0x3000>;
diff --git a/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
index 09b3822f85ef..1f6b2cb26a56 100644
--- a/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
+++ b/snippets/emulated-gpio/icbmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -10,9 +10,8 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			cpuflpr_code_partition: image@165000 {
-				/* FLPR core code partition */
-				reg = <0x165000 DT_SIZE_K(96)>;
+			cpuflpr_code_partition: image@179800 {
+				reg = <0x179800 DT_SIZE_K(14)>;
 			};
 
 			sram_rx: memory@2003b800 {
@@ -48,6 +47,10 @@
 	};
 };
 
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(1510)>;
+};
+
 &cpuapp_sram {
 	reg = <0x20000000 DT_SIZE_K(242)>;
 	ranges = <0x0 0x20000000 0x3d000>;
diff --git a/snippets/emulated-gpio/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/snippets/emulated-gpio/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
index 9fb9821dc1d7..388251c8ca91 100644
--- a/snippets/emulated-gpio/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
+++ b/snippets/emulated-gpio/icmsg/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -10,9 +10,8 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			cpuflpr_code_partition: image@165000 {
-				/* FLPR core code partition */
-				reg = <0x165000 DT_SIZE_K(96)>;
+			cpuflpr_code_partition: image@17a000 {
+				reg = <0x17a000 DT_SIZE_K(12)>;
 			};
 
 			sram_rx: memory@2003c000 {
@@ -46,6 +45,10 @@
 	};
 };
 
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(1512)>;
+};
+
 &cpuapp_sram {
 	reg = <0x20000000 DT_SIZE_K(244)>;
 	ranges = <0x0 0x20000000 0x3d000>;
diff --git a/snippets/emulated-gpio/mbox/boards/nrf54l15dk_nrf54l15_cpuapp.overlay b/snippets/emulated-gpio/mbox/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
index 66506cae1187..904e3b116fa5 100644
--- a/snippets/emulated-gpio/mbox/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
+++ b/snippets/emulated-gpio/mbox/boards/nrf54l15dk_nrf54l15_cpuapp.overlay
@@ -10,9 +10,8 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-			cpuflpr_code_partition: image@165000 {
-				/* FLPR core code partition */
-				reg = <0x165000 DT_SIZE_K(96)>;
+			cpuflpr_code_partition: image@17a000 {
+				reg = <0x17a000 DT_SIZE_K(12)>;
 			};
 
 			sram_rx: memory@2003c000 {
@@ -41,6 +40,10 @@
 	};
 };
 
+&cpuapp_rram {
+	reg = <0x0 DT_SIZE_K(1512)>;
+};
+
 &cpuapp_sram {
 	reg = <0x20000000 DT_SIZE_K(244)>;
 	ranges = <0x0 0x20000000 0x3d000>;