diff --git a/CODEOWNERS b/CODEOWNERS index 41949f018bcf..6b082d23ec46 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -656,7 +656,10 @@ /scripts/ncs-toolchain-version-minimum.txt @nrfconnect/ncs-co-build-system @nrfconnect/ncs-ci /scripts/tools-versions-*.txt @nrfconnect/ncs-co-build-system @nrfconnect/ncs-ci /scripts/requirements-*.txt @nrfconnect/ncs-co-build-system @nrfconnect/ncs-ci +/scripts/west_commands/utils/ @gmarull /scripts/west_commands/create_board/ @gmarull +/scripts/west_commands/ncs-bicr.py @gmarull +/scripts/west_commands/ncs-board-actions.py @gmarull /scripts/west_commands/sbom/ @nrfconnect/ncs-si-muffin /scripts/west_commands/thingy91x_dfu.py @nrfconnect/ncs-cia /scripts/west_commands/ncs-provision.py @nrfconnect/ncs-pluto diff --git a/doc/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_custom_pcb.rst b/doc/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_custom_pcb.rst index 625039648fab..0914e36378b8 100644 --- a/doc/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_custom_pcb.rst +++ b/doc/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_custom_pcb.rst @@ -16,23 +16,22 @@ First, you need to create your PCB for the nRF54H20 SoC. We highly recommend using the PCB layouts and component values provided by Nordic Semiconductor, especially for clock and power sources, considering the following limitations: -* The DC/DC inductor must be present on the PCB, and the ``inductor-present;`` node must be configured either in the :file:`zephyr/boards/your_board/nrf54h20dk_bicr.dtsi` file or in the section where ``bicr: bicr@fff87b0`` is present in the devicetree. -* For the lowest sleep power consumption, use a 32 KHz crystal. -* The **P9** port cannot be used with internal or external pull-down resistors. -* For optimal performance, the output impedance of the **P6** and **P7** ports should match the PCB and external device pin impedance. -* Use one of the following power supply options: +* The DC/DC inductor must be present on the PCB for any of the supported power schemes. + Use one of the following power supply options: * VDDH higher than 2.05V. * VDDH shorted to VDD at 1.8V +* For the lowest sleep power consumption, use a 32 KHz crystal. +* The **P9** port cannot be used with internal or external pull-down resistors. +* For optimal performance, the output impedance of the **P6** and **P7** ports should match the PCB and external device pin impedance. + Prepare the configuration files for your custom board in the |NCS| ****************************************************************** -The nRF54H20 DK uses multiple board files for its configuration. -You can use these files as a starting point for configuring your own custom board. -When creating a :ref:`Zephyr repository application `, copy the files from :file:`sdk-zephyr/boards/nordic/nrf54h20dk` to the :file:`sdk-zephyr/boards//` file. +Use the `nRF Connect for VS Code Extension Pack`_ to generate a custom board skeleton. -You must edit the :file:`.dts` and :file:`.overlay` files for your project to match your board configuration, similarly to any new board added to the |NCS| or Zephyr. +Use the nRF54H20 DK board files found in :file:`sdk-zephyr/boards/nordic/nrf54h20dk` as a reference point for configuring your own custom board. See the following documentation pages for more information: @@ -60,16 +59,16 @@ The power and clock control firmware uses this information to apply the proper r BICR allows for the configuration of various components on your custom board, like the following: -* Power rails -* Low-frequency oscillator +* Power scheme +* Low-frequency oscillator (LFXO or LFRC) * High-frequency oscillator (HFXO) * GPIO ports power and drive control * Tamper switches * Active shield channels -You can find the details in the DTS specification for the BICR in :file:`sdk-zephyr/dts/bindings/misc/nordic,nrf-bicr.yaml` +You can find the details in the BICR configuration file scheme in :file:`sdk-zephyr/soc/nordic/nrf54h/bicr/bicr-schema.json`. -When not set, the registers' default value is ``0xFFFFFFFF``. +When the BICR has not been programmed, all the registers contain ``0xFFFFFFFF``. The ``LFOSC.LFXOCAL`` register is used by the device to store the calibration of the LFXO. @@ -81,9 +80,9 @@ Each subsequent start will use this initial calibration as the starting point. BICR configuration ================== -The nRF54H20 DK BICR configuration can be found in the board configuration directory as :file:`sdk-zephyr/boards/nordic/nrf54h20dk/nrf54h20dk_bicr.dtsi`. +The nRF54H20 DK BICR configuration can be found in the board configuration directory as :file:`sdk-zephyr/boards/nordic/nrf54h20dk/bicr.json`. This file is used by the |NCS| build system to generate a corresponding HEX file. -You can start from this file when editing the values of the devicetree properties inside your custom board folder (:file:`boards/nordic/your_custom_board`), according to your board configuration. +The scheme for this file can be found in :file:`sdk-zephyr/soc/nordic/nrf54h/bicr/bicr-schema.json`. .. caution:: A mismatch between the board and the configuration values in BICR can damage the device or set it in an unrecoverable state. @@ -91,15 +90,13 @@ You can start from this file when editing the values of the devicetree propertie Generate the BICR binary ======================== -To generate the BICR binary, you must first set the Kconfig option :kconfig:option:`CONFIG_NRF_REGTOOL_GENERATE_BICR` to ``y``. -When running ``west build``, the build system then creates the relevant HEX file (:file:`bicr.hex`) at build time. -Based on the peripheral definition extracted from the nRF54H20 SVD file, the modified registers from the configuration are mapped into their relevant position in memory. +To generate the BICR binary, you must first set the Kconfig option :kconfig:option:`CONFIG_SOC_NRF54H20_GENERATE_BICR` to ``y``. +When running ``west build`` for the ``cpuapp`` core, the build system creates the relevant HEX file (:file:`bicr.hex`) at build time. .. note:: - If the build system cannot locate the ``bicr`` node inside your custom board's devicetree, or if you did not create a custom :file:`.dtsi` file for it, the BICR generation cannot progress, and the build system will skip it. + If the build system is unable to locate the :file:`bicr.json` file inside your custom board's directory, the build system will skip it. -You can find the generated :file:`bicr.hex` file in the :file:`build_dir/zephyr/`. -The presence of a ``bicr`` node in the application devicetree will automatically trigger a build of the BICR binary, and will place this file alongside the other binary outputs such as ``zephyr.hex`` and ``uicr.hex``. +You can find the generated :file:`bicr.hex` file in the :file:`build_dir//zephyr/`. Program the BICR binary ======================= diff --git a/doc/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_suit_recovery.rst b/doc/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_suit_recovery.rst index fbaae3316add..a096bec68b0b 100644 --- a/doc/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_suit_recovery.rst +++ b/doc/nrf/app_dev/device_guides/nrf54h/ug_nrf54h20_suit_recovery.rst @@ -129,7 +129,7 @@ To turn an application into a recovery application, the following steps have to * :kconfig:option:`CONFIG_SUIT_RECOVERY` set to ``y`` * :kconfig:option:`CONFIG_NRF_REGTOOL_GENERATE_UICR` set to ``n`` - * :kconfig:option:`CONFIG_NRF_REGTOOL_GENERATE_BICR` set to ``n`` + * :kconfig:option:`CONFIG_SOC_NRF54H20_GENERATE_BICR` set to ``n`` To do that you can simply paste the following code snippet into your configuration files: @@ -137,7 +137,7 @@ To turn an application into a recovery application, the following steps have to CONFIG_SUIT_RECOVERY=y CONFIG_NRF_REGTOOL_GENERATE_UICR=n - CONFIG_NRF_REGTOOL_GENERATE_BICR=n + CONFIG_SOC_NRF54H20_GENERATE_BICR=n #. Create the overlay files to be used by the recovery application. In this guide it is assumed that for the application core they are placed in the custom recovery application directory in the :file:`boards/nrf54h20dk_nrf54h20_cpuapp.overlay` file. diff --git a/samples/suit/flash_companion/prj.conf b/samples/suit/flash_companion/prj.conf index 24223dfcadf2..02c6f19412f3 100644 --- a/samples/suit/flash_companion/prj.conf +++ b/samples/suit/flash_companion/prj.conf @@ -63,7 +63,7 @@ CONFIG_USE_DT_CODE_PARTITION=y CONFIG_SUIT_LOCAL_ENVELOPE_GENERATE=n CONFIG_SUIT_ENVELOPE_TARGET="" CONFIG_NRF_REGTOOL_GENERATE_UICR=n -CONFIG_NRF_REGTOOL_GENERATE_BICR=n +CONFIG_SOC_NRF54H20_GENERATE_BICR=n # Enable canonical zcbor encoding CONFIG_ZCBOR_CANONICAL=y diff --git a/samples/suit/recovery/prj.conf b/samples/suit/recovery/prj.conf index e038c67f3dc0..db1bcbcb6f1c 100644 --- a/samples/suit/recovery/prj.conf +++ b/samples/suit/recovery/prj.conf @@ -11,7 +11,7 @@ CONFIG_SUIT_RECOVERY=y # It is the main application which is responsible for flashing and generating the UICR # configuration - the recovery application should not do it. CONFIG_NRF_REGTOOL_GENERATE_UICR=n -CONFIG_NRF_REGTOOL_GENERATE_BICR=n +CONFIG_SOC_NRF54H20_GENERATE_BICR=n ############ diff --git a/samples/suit/recovery/sysbuild/hci_ipc.conf b/samples/suit/recovery/sysbuild/hci_ipc.conf index c2f546c93beb..9dcfcfa57d18 100644 --- a/samples/suit/recovery/sysbuild/hci_ipc.conf +++ b/samples/suit/recovery/sysbuild/hci_ipc.conf @@ -11,7 +11,7 @@ CONFIG_SUIT_RECOVERY=y # It is the main application which is responsible for flashing and generating the UICR # configuration - the recovery application should not do it. CONFIG_NRF_REGTOOL_GENERATE_UICR=n -CONFIG_NRF_REGTOOL_GENERATE_BICR=n +CONFIG_SOC_NRF54H20_GENERATE_BICR=n ########### CONFIG_BT_BUF_ACL_RX_SIZE=502 diff --git a/scripts/west-commands.yml b/scripts/west-commands.yml index 286044655a57..345b8476e04c 100644 --- a/scripts/west-commands.yml +++ b/scripts/west-commands.yml @@ -39,3 +39,13 @@ west-commands: - name: ncs-provision class: NcsProvision help: Provision utility + - file: scripts/west_commands/ncs-bicr.py + commands: + - name: ncs-bicr + class: NcsBICR + help: Assist with board BICR creation for any applicable Nordic SoC + - file: scripts/west_commands/ncs-board-actions.py + commands: + - name: ncs-board-actions + class: NcsBoardActions + help: Obtain available actions for any board diff --git a/scripts/west_commands/create_board/config.yml b/scripts/west_commands/create_board/config.yml index 74e302431e4c..0e4a81ef2b5f 100644 --- a/scripts/west_commands/create_board/config.yml +++ b/scripts/west_commands/create_board/config.yml @@ -71,6 +71,30 @@ products: arch: arm ram: 188 flash: 324 + - series: nrf54h + socs: + - name: nrf54h20 + variants: + - name: ckaa + cores: + - name: cpuapp + arch: arm + ram: 256 + flash: 296 + - name: cpurad + arch: arm + ram: 192 + flash: 256 + - name: cpuppr + arch: riscv + ram: 62 + flash: 62 + xip: true + - name: cpuflpr + arch: riscv + ram: 46 + flash: 46 + xip: true - series: nrf91 socs: - name: nrf9131 diff --git a/scripts/west_commands/create_board/ncs_create_board.py b/scripts/west_commands/create_board/ncs_create_board.py index aa6d7b8fde08..4286c82f609b 100644 --- a/scripts/west_commands/create_board/ncs_create_board.py +++ b/scripts/west_commands/create_board/ncs_create_board.py @@ -4,10 +4,10 @@ from pathlib import Path import json import shutil +import sys from jinja2 import Environment, FileSystemLoader from west.commands import WestCommand -from west import log from yaml import load import jsonschema @@ -16,6 +16,12 @@ except ImportError: from yaml import Loader +sys.path.append(str(Path(__file__).parents[1])) +import utils + + +utils.install_json_excepthook() + SCRIPT_DIR = Path(__file__).absolute().parent TEMPLATE_DIR = SCRIPT_DIR / "templates" @@ -50,6 +56,11 @@ def do_run(self, args, unknown_args): schema = json.loads(f.read()) if args.json_schema: + schema = { + "schema": schema, + "state": None, + } + print(json.dumps(schema)) return @@ -62,7 +73,7 @@ def do_run(self, args, unknown_args): try: jsonschema.validate(input, schema) except jsonschema.ValidationError as e: - raise Exception("Board configuration is not valid") from e + raise ValueError("Board configuration is not valid") from e soc_parts = input["soc"].split("-") req_soc = soc_parts[0].lower() @@ -81,8 +92,7 @@ def do_run(self, args, unknown_args): break if not series: - log.err(f"Invalid/unsupported SoC: {req_soc}") - return + raise ValueError(f"Invalid/unsupported SoC: {req_soc}") targets = [] for variant in soc["variants"]: @@ -125,8 +135,7 @@ def do_run(self, args, unknown_args): break if not targets: - log.err(f"Invalid/unsupported variant: {req_variant}") - return + raise ValueError(f"Invalid/unsupported variant: {req_variant}") # prepare Jinja environment env = Environment( @@ -180,6 +189,14 @@ def do_run(self, args, unknown_args): tmpl = TEMPLATE_DIR / series / "board-shared_sram.dtsi" shutil.copy(tmpl, out_dir / f"{ input['board'] }-shared_sram.dtsi") + # nrf54H specific files + if series == "nrf54h": + tmpl = TEMPLATE_DIR / series / "board-ipc_conf.dtsi" + shutil.copy(tmpl, out_dir / f"{ input['board'] }-ipc_conf.dtsi") + + tmpl = TEMPLATE_DIR / series / "board-memory_map.dtsi" + shutil.copy(tmpl, out_dir / f"{ input['board'] }-memory_map.dtsi") + # nrf91 specific files if series == "nrf91": tmpl = env.get_template("board-partitioning.dtsi.jinja2") @@ -200,7 +217,11 @@ def do_run(self, args, unknown_args): with open(out_dir / f"{ name }_defconfig", "w") as f: f.write(tmpl.render(target=target)) - tmpl = env.get_template("board.dts.jinja2") + if not target["xip"]: + tmpl = env.get_template("board.dts.jinja2") + else: + tmpl = env.get_template("board-xip.dts.jinja2") + with open(out_dir / f"{name}.dts", "w") as f: f.write(tmpl.render(target=target)) @@ -208,4 +229,19 @@ def do_run(self, args, unknown_args): with open(out_dir / f"{name}.yml", "w") as f: f.write(tmpl.render(target=target)) - print(f"Board {input['board']} created successfully") + # return post-commands + commands = [] + + if series == "nrf54h": + commands.append( + { + "name": "Create BICR", + "command": "west", + "args": ["ncs-bicr", "--board-dir", str(out_dir.resolve())], + "properties": { + "providesJsonSchema": True, + }, + } + ) + + print(json.dumps({"commands": commands})) diff --git a/scripts/west_commands/create_board/schema.json b/scripts/west_commands/create_board/schema.json index 08036d8747bb..e0ea939d56e9 100644 --- a/scripts/west_commands/create_board/schema.json +++ b/scripts/west_commands/create_board/schema.json @@ -39,6 +39,7 @@ "nRF52840-QFAA", "nRF52840-QIAA", "nRF5340-QKAA", + "nRF54H20-CKAA", "nRF54L15-QFAA", "nRF9131-LACA", "nRF9151-LACA", diff --git a/scripts/west_commands/create_board/templates/nrf54h/Kconfig.board.jinja2 b/scripts/west_commands/create_board/templates/nrf54h/Kconfig.board.jinja2 new file mode 100644 index 000000000000..acba90903a74 --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/Kconfig.board.jinja2 @@ -0,0 +1,7 @@ +config BOARD_{{ board | upper }} + select SOC_NRF54H20_CPUAPP if BOARD_{{ board | upper }}_NRF54H20_CPUAPP + select SOC_NRF54H20_CPURAD if BOARD_{{ board | upper }}_NRF54H20_CPURAD + select SOC_NRF54H20_CPUPPR if BOARD_{{ board | upper }}_NRF54H20_CPUPPR || \ + BOARD_{{ board | upper }}_NRF54H20_CPUPPR_XIP + select SOC_NRF54H20_CPUFLPR if BOARD_{{ board | upper }}_NRF54H20_CPUFLPR || \ + BOARD_{{ board | upper }}_NRF54H20_CPUFLPR_XIP diff --git a/scripts/west_commands/create_board/templates/nrf54h/Kconfig.defconfig.jinja2 b/scripts/west_commands/create_board/templates/nrf54h/Kconfig.defconfig.jinja2 new file mode 100644 index 000000000000..6d9824d7ddea --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/Kconfig.defconfig.jinja2 @@ -0,0 +1,13 @@ +if BOARD_{{ board | upper }}_NRF54H20_CPUAPP + +config BT_HCI_IPC + default y if BT + +endif # BOARD_{{ board | upper }}_NRF54H20_CPUAPP + +if BOARD_{{ board | upper }}_NRF54H20_CPURAD + +config BT_CTLR + default y if BT + +endif # BOARD_{{ board | upper }}_NRF54H20_CPURAD diff --git a/scripts/west_commands/create_board/templates/nrf54h/board-common.dtsi b/scripts/west_commands/create_board/templates/nrf54h/board-common.dtsi new file mode 100644 index 000000000000..fc2d70f6c52a --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/board-common.dtsi @@ -0,0 +1,17 @@ +#include "{{ board }}-memory_map.dtsi" +#include "{{ board }}-ipc_conf.dtsi" +#include "{{ board }}-pinctrl.dtsi" + +&hfxo { + status = "okay"; + accuracy-ppm = <30>; + startup-time-us = <850>; + mode = "crystal"; +}; + +&lfxo { + status = "okay"; + accuracy-ppm = <20>; + startup-time-us = <600000>; + mode = "crystal"; +}; diff --git a/scripts/west_commands/create_board/templates/nrf54h/board-ipc_conf.dtsi b/scripts/west_commands/create_board/templates/nrf54h/board-ipc_conf.dtsi new file mode 100644 index 000000000000..d5ef5157a08e --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/board-ipc_conf.dtsi @@ -0,0 +1,59 @@ +/ { + ipc { + cpusec_cpuapp_ipc: ipc-1-2 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + dcache-alignment = <32>; + mboxes = <&cpusec_bellboard 12>, + <&cpuapp_bellboard 0>; + }; + + cpusec_cpurad_ipc: ipc-1-3 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + dcache-alignment = <32>; + mboxes = <&cpusec_bellboard 18>, + <&cpurad_bellboard 0>; + }; + + cpuapp_cpurad_ipc: ipc-2-3 { + compatible = "zephyr,ipc-icbmsg"; + dcache-alignment = <32>; + status = "disabled"; + mboxes = <&cpuapp_bellboard 18>, + <&cpurad_bellboard 12>; + }; + + cpuapp_cpusys_ipc: ipc-2-12 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + dcache-alignment = <32>; + mboxes = <&cpuapp_bellboard 6>, + <&cpusys_vevif 12>; + }; + + cpuapp_cpuppr_ipc: ipc-2-13 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + dcache-alignment = <32>; + mboxes = <&cpuapp_bellboard 13>, + <&cpuppr_vevif 12>; + }; + + cpuapp_cpuflpr_ipc: ipc-2-14 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + dcache-alignment = <32>; + mboxes = <&cpuapp_bellboard 14>, + <&cpuflpr_vevif 16>; + }; + + cpurad_cpusys_ipc: ipc-3-12 { + compatible = "zephyr,ipc-icmsg"; + status = "disabled"; + dcache-alignment = <32>; + mboxes = <&cpurad_bellboard 6>, + <&cpusys_vevif 18>; + }; + }; +}; diff --git a/scripts/west_commands/create_board/templates/nrf54h/board-memory_map.dtsi b/scripts/west_commands/create_board/templates/nrf54h/board-memory_map.dtsi new file mode 100644 index 000000000000..fb31c6ea790b --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/board-memory_map.dtsi @@ -0,0 +1,227 @@ + #include + +&suit_storage_partition { + reg = <0xe1eb000 DT_SIZE_K(24)>; +}; + +/ { + reserved-memory { + cpuapp_ram0x_region: memory@2f010000 { + compatible = "nordic,owned-memory"; + reg = <0x2f010000 DT_SIZE_K(260)>; + status = "disabled"; + nordic,access = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f010000 0x41000>; + + cpusec_cpuapp_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpuapp_cpusec_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + + cpuapp_data: memory@1000 { + reg = <0x1000 DT_SIZE_K(256)>; + }; + }; + + cpurad_ram0x_region: memory@2f051000 { + compatible = "nordic,owned-memory"; + reg = <0x2f051000 DT_SIZE_K(4)>; + status = "disabled"; + nordic,access = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f051000 0x1000>; + + cpusec_cpurad_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpurad_cpusec_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + }; + + etr_buf_ram0x_region: memory@2f0be000 { + compatible = "nordic,owned-memory"; + reg = <0x2f0be000 DT_SIZE_K(4)>; + status = "disabled"; + nordic,access = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f0be000 0x1000>; + + /* TODO In future move this region to cpuapp_ram0x_region. */ + etr_buffer: memory@0 { + reg = <0x0 DT_SIZE_K(4)>; + }; + }; + + cpuapp_cpurad_ram0x_region: memory@2f0bf000 { + compatible = "nordic,owned-memory"; + reg = <0x2f0bf000 DT_SIZE_K(4)>; + status = "disabled"; + nordic,access = , + ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f0bf000 0x1000>; + + cpuapp_cpurad_ipc_shm: memory@0 { + reg = <0x0 DT_SIZE_K(2)>; + }; + + cpurad_cpuapp_ipc_shm: memory@800 { + reg = <0x800 DT_SIZE_K(2)>; + }; + }; + + cpuapp_cpusys_ipc_shm: memory@2f88fce0 { + reg = <0x2f88fce0 0x80>; + }; + + cpusys_cpuapp_ipc_shm: memory@2f88fd60 { + reg = <0x2f88fd60 0x80>; + }; + + cpurad_cpusys_ipc_shm: memory@2f88fe00 { + reg = <0x2f88fe00 0x80>; + }; + + cpusys_cpurad_ipc_shm: memory@2f88fe80 { + reg = <0x2f88fe80 0x80>; + }; + + /* + * NOTE: FLPR has a direct bridge with RAM21 that bypasses MPC. + * This means that when this region is marked as non-executable, + * only FLPR can execute code from it. + */ + ram21_region: memory@2f890000 { + compatible = "nordic,owned-memory"; + status = "disabled"; + reg = <0x2f890000 DT_SIZE_K(64)>; + nordic,access = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2f890000 0x10000>; + + cpuflpr_code_data: memory@0 { + reg = <0x0 DT_SIZE_K(46)>; + }; + + cpuapp_cpuflpr_ipc_shm: memory@b800 { + reg = <0xb800 DT_SIZE_K(1)>; + }; + + cpuflpr_cpuapp_ipc_shm: memory@bc00 { + reg = <0xbc00 DT_SIZE_K(1)>; + }; + + dma_fast_region: memory@c000 { + compatible = "zephyr,memory-region"; + reg = <0xc000 DT_SIZE_K(16)>; + status = "disabled"; + #memory-region-cells = <0>; + zephyr,memory-region = "DMA_RAM21"; + zephyr,memory-attr = <( DT_MEM_DMA | DT_MEM_CACHEABLE )>; + }; + }; + + cpuppr_ram3x_region: memory@2fc00000 { + compatible = "nordic,owned-memory"; + reg = <0x2fc00000 DT_SIZE_K(64)>; + status = "disabled"; + nordic,access = ; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x2fc00000 0x10000>; + + cpuppr_code_data: memory@0 { + reg = <0x0 DT_SIZE_K(62)>; + }; + + cpuapp_cpuppr_ipc_shm: memory@f800 { + reg = <0xf800 DT_SIZE_K(1)>; + }; + + cpuppr_cpuapp_ipc_shm: memory@fc00 { + reg = <0xfc00 DT_SIZE_K(1)>; + }; + }; + + cpuapp_dma_region: memory@2fc12000 { + compatible = "nordic,owned-memory", "zephyr,memory-region"; + reg = <0x2fc12000 DT_SIZE_K(4)>; + status = "disabled"; + #memory-region-cells = <0>; + nordic,access = ; + zephyr,memory-region = "DMA_RAM3x_APP"; + zephyr,memory-attr = <( DT_MEM_DMA )>; + }; + + cpurad_dma_region: memory@2fc13000 { + compatible = "nordic,owned-memory", "zephyr,memory-region"; + reg = <0x2fc13000 DT_SIZE_K(1)>; + status = "disabled"; + #memory-region-cells = <0>; + nordic,access = ; + zephyr,memory-region = "DMA_RAM3x_RAD"; + zephyr,memory-attr = <( DT_MEM_DMA )>; + }; + }; +}; + +&mram1x { + cpurad_rx_partitions: cpurad-rx-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + nordic,access = ; + #address-cells = <1>; + #size-cells = <1>; + + cpurad_slot0_partition: partition@66000 { + reg = <0x66000 DT_SIZE_K(256)>; + }; + }; + + cpuapp_rx_partitions: cpuapp-rx-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + nordic,access = ; + #address-cells = <1>; + #size-cells = <1>; + + cpuapp_slot0_partition: partition@a6000 { + reg = <0xa6000 DT_SIZE_K(248)>; + }; + + cpuppr_code_partition: partition@e4000 { + reg = <0xe4000 DT_SIZE_K(64)>; + }; + + cpuflpr_code_partition: partition@f4000 { + reg = <0xf4000 DT_SIZE_K(48)>; + }; + }; + + cpuapp_rw_partitions: cpuapp-rw-partitions { + compatible = "nordic,owned-partitions", "fixed-partitions"; + status = "disabled"; + nordic,access = ; + #address-cells = <1>; + #size-cells = <1>; + + dfu_partition: partition@100000 { + reg = < 0x100000 DT_SIZE_K(908) >; + }; + + storage_partition: partition@1e3000 { + reg = < 0x1e3000 DT_SIZE_K(24) >; + }; + }; +}; diff --git a/scripts/west_commands/create_board/templates/nrf54h/board-pinctrl.dtsi b/scripts/west_commands/create_board/templates/nrf54h/board-pinctrl.dtsi new file mode 100644 index 000000000000..eb124f540995 --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/board-pinctrl.dtsi @@ -0,0 +1,2 @@ +&pinctrl { +}; diff --git a/scripts/west_commands/create_board/templates/nrf54h/board-xip.dts.jinja2 b/scripts/west_commands/create_board/templates/nrf54h/board-xip.dts.jinja2 new file mode 100644 index 000000000000..ff1050e68336 --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/board-xip.dts.jinja2 @@ -0,0 +1 @@ +#include "{{ board }}_nrf54h20_{{ target["core"] }}.dts" diff --git a/scripts/west_commands/create_board/templates/nrf54h/board.cmake.jinja2 b/scripts/west_commands/create_board/templates/nrf54h/board.cmake.jinja2 new file mode 100644 index 000000000000..a52336ec7441 --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/board.cmake.jinja2 @@ -0,0 +1 @@ +include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake) diff --git a/scripts/west_commands/create_board/templates/nrf54h/board.dts.jinja2 b/scripts/west_commands/create_board/templates/nrf54h/board.dts.jinja2 new file mode 100644 index 000000000000..bca0b22a73af --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/board.dts.jinja2 @@ -0,0 +1,312 @@ +/dts-v1/; + +#include +#include "{{ board }}-memory_map.dtsi" +#include "{{ board }}-ipc_conf.dtsi" +#include "{{ board }}-pinctrl.dtsi" + +{% if target['core'] == 'cpuapp' %} +/delete-node/ &cpurad_cpusys_ipc; +/delete-node/ &cpusec_cpurad_ipc; + +/ { + model = "{{ board_desc }} (CPUAPP)"; + compatible = "{{ vendor }},{{ board | replace("_", "-") }}-cpuapp"; + + chosen { + zephyr,code-partition = &cpuapp_slot0_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpuapp_data; + zephyr,bt-hci = &bt_hci_ipc0; + zephyr,entropy = &prng; + }; + + aliases { + ipc-to-cpusys = &cpuapp_cpusys_ipc; + }; + + prng: prng { + compatible = "nordic,entropy-prng"; + status = "okay"; + }; +}; + +&cpuapp_ram0x_region { + status = "okay"; +}; + +&etr_buf_ram0x_region { + status = "okay"; +}; + +&ram21_region { + status = "okay"; +}; + +&cpuapp_bellboard { + status = "okay"; + interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0"; + /* irq0: + * - 0: cpuapp-cpusec + * - 6: cpuapp-cpusys + * - 13: cpuapp-cpuppr + * - 14: cpuapp-cpuflpr + * - 18: cpuapp-cpurad + */ + nordic,interrupt-mapping = <0x00046041 0>; +}; + +&cpurad_bellboard { + status = "okay"; +}; + +&cpusys_vevif { + status = "okay"; +}; + +&cpusec_cpuapp_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuapp_cpusec_ipc_shm>; + rx-region = <&cpusec_cpuapp_ipc_shm>; +}; + +ipc0: &cpuapp_cpurad_ipc { + status = "okay"; + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpurad_ipc_shm>; + rx-region = <&cpurad_cpuapp_ipc_shm>; + tx-blocks = <32>; + rx-blocks = <32>; + + bt_hci_ipc0: bt_hci_ipc0 { + compatible = "zephyr,bt-hci-ipc"; + status = "okay"; + }; +}; + +&cpuapp_cpusys_ipc { + status = "okay"; + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpusys_ipc_shm>; + rx-region = <&cpusys_cpuapp_ipc_shm>; +}; + +&cpuapp_cpuppr_ipc { + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpuppr_ipc_shm>; + rx-region = <&cpuppr_cpuapp_ipc_shm>; +}; + +&cpuapp_cpuflpr_ipc { + mbox-names = "rx", "tx"; + tx-region = <&cpuapp_cpuflpr_ipc_shm>; + rx-region = <&cpuflpr_cpuapp_ipc_shm>; +}; + +&cpuapp_dma_region { + status = "okay"; +}; + +&dma_fast_region { + status = "okay"; +}; + +&cpuapp_rx_partitions { + status = "okay"; +}; + +&cpuapp_rw_partitions { + status = "okay"; +}; + +&cpuppr_vpr { + execution-memory = <&cpuppr_code_data>; + source-memory = <&cpuppr_code_partition>; +}; + +&cpuflpr_vpr { + execution-memory = <&cpuflpr_code_data>; + source-memory = <&cpuflpr_code_partition>; +}; + +&hfxo { + status = "okay"; + accuracy-ppm = <30>; + startup-time-us = <850>; + mode = "crystal"; +}; + +&lfxo { + status = "okay"; + accuracy-ppm = <20>; + startup-time-us = <600000>; + mode = "crystal"; +}; + +&grtc { + status = "okay"; + child-owned-channels = <5 6>; + nonsecure-channels = <5 6>; + owned-channels = <4 5 6>; +}; +{% elif target['core'] == 'cpurad' %} +/delete-node/ &cpuapp_cpuppr_ipc; +/delete-node/ &cpuapp_cpusys_ipc; +/delete-node/ &cpuapp_cpuflpr_ipc; +/delete-node/ &cpusec_cpuapp_ipc; + +/ { + model = "{{ board_desc }} (CPURAD)"; + compatible = "{{ vendor }},{{ board | replace("_", "-") }}-cpurad"; + + chosen { + zephyr,code-partition = &cpurad_slot0_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpurad_ram0; + zephyr,bt-hci-ipc = &ipc0; + zephyr,entropy = &prng; + }; + + prng: prng { + compatible = "nordic,entropy-prng"; + status = "okay"; + }; + + aliases { + ipc-to-cpusys = &cpurad_cpusys_ipc; + }; +}; + +&cpuapp_cpurad_ram0x_region { + status = "okay"; +}; + +&cpurad_bellboard { + status = "okay"; + interrupts = <96 NRF_DEFAULT_IRQ_PRIORITY>; + interrupt-names = "irq0"; + /* irq0: 0: cpurad-cpusec, 6: cpurad-cpusys, 12: cpurad-cpuapp */ + nordic,interrupt-mapping = <0x00001041 0>; +}; + +&cpuapp_bellboard { + status = "okay"; +}; + +&cpusys_vevif { + status = "okay"; +}; + +&cpusec_cpurad_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpurad_cpusec_ipc_shm>; + rx-region = <&cpusec_cpurad_ipc_shm>; +}; + +ipc0: &cpuapp_cpurad_ipc { + status = "okay"; + mbox-names = "tx", "rx"; + tx-region = <&cpurad_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpurad_ipc_shm>; + tx-blocks = <32>; + rx-blocks = <32>; +}; + +&cpurad_cpusys_ipc { + status = "okay"; + mbox-names = "rx", "tx"; + tx-region = <&cpurad_cpusys_ipc_shm>; + rx-region = <&cpusys_cpurad_ipc_shm>; +}; + +&cpurad_dma_region { + status = "okay"; +}; + +&cpurad_rx_partitions { + status = "okay"; +}; + +&hfxo { + status = "okay"; + accuracy-ppm = <30>; + startup-time-us = <850>; + mode = "crystal"; +}; + +&lfxo { + status = "okay"; + accuracy-ppm = <20>; + startup-time-us = <600000>; + mode = "crystal"; +}; + +&grtc { + status = "okay"; +}; +{% elif target['core'] == 'cpuppr' %} +/delete-node/ &cpuapp_cpurad_ipc; +/delete-node/ &cpuapp_cpusys_ipc; +/delete-node/ &cpuapp_cpuflpr_ipc; +/delete-node/ &cpurad_cpusys_ipc; +/delete-node/ &cpusec_cpuapp_ipc; +/delete-node/ &cpusec_cpurad_ipc; + +/ { + model = "{{ board_desc }} (CPUPPR)"; + compatible = "{{ vendor }},{{ board | replace("_", "-") }}-cpuppr"; + + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,code-partition = &cpuppr_code_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpuppr_code_data; + }; +}; + +&cpuapp_cpuppr_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuppr_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpuppr_ipc_shm>; +}; + +&grtc { + status = "okay"; + owned-channels = <5>; +}; +{% elif target['core'] == 'cpuflpr' %} +/delete-node/ &cpuapp_cpurad_ipc; +/delete-node/ &cpuapp_cpusys_ipc; +/delete-node/ &cpuapp_cpuppr_ipc; +/delete-node/ &cpurad_cpusys_ipc; +/delete-node/ &cpusec_cpuapp_ipc; +/delete-node/ &cpusec_cpurad_ipc; + +/ { + model = "{{ board_desc }} (CPUAPP)"; + compatible = "{{ vendor }},{{ board | replace("_", "-") }}-cpuflpr"; + + #address-cells = <1>; + #size-cells = <1>; + + chosen { + zephyr,code-partition = &cpuflpr_code_partition; + zephyr,flash = &mram1x; + zephyr,sram = &cpuflpr_code_data; + }; +}; + +&cpuapp_cpuflpr_ipc { + mbox-names = "tx", "rx"; + tx-region = <&cpuflpr_cpuapp_ipc_shm>; + rx-region = <&cpuapp_cpuflpr_ipc_shm>; +}; + +&grtc { + status = "okay"; + owned-channels = <6>; +}; +{% endif %} diff --git a/scripts/west_commands/create_board/templates/nrf54h/board.yml.jinja2 b/scripts/west_commands/create_board/templates/nrf54h/board.yml.jinja2 new file mode 100644 index 000000000000..63cbbfc93572 --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/board.yml.jinja2 @@ -0,0 +1,10 @@ +board: + name: {{ board }} + vendor: {{ vendor }} + socs: + - name: nrf54h20 + variants: + - name: xip + cpucluster: cpuppr + - name: xip + cpucluster: cpuflpr diff --git a/scripts/west_commands/create_board/templates/nrf54h/board_defconfig.jinja2 b/scripts/west_commands/create_board/templates/nrf54h/board_defconfig.jinja2 new file mode 100644 index 000000000000..0bc77075a8e4 --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/board_defconfig.jinja2 @@ -0,0 +1,17 @@ +{% if target['core'] == 'cpuapp' or target['core'] == 'cpurad' %} +CONFIG_USE_DT_CODE_PARTITION=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y + +CONFIG_CACHE_MANAGEMENT=y +CONFIG_EXTERNAL_CACHE=y +{% elif target['core'] == 'cpuppr' or target['core'] == 'cpuflpr' %} +CONFIG_USE_DT_CODE_PARTITION=y +{% if target['xip'] %} +CONFIG_XIP=y +{% else %} +CONFIG_XIP=n +{% endif %} +{% endif %} diff --git a/scripts/west_commands/create_board/templates/nrf54h/board_twister.yml.jinja2 b/scripts/west_commands/create_board/templates/nrf54h/board_twister.yml.jinja2 new file mode 100644 index 000000000000..6220470ace5f --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/board_twister.yml.jinja2 @@ -0,0 +1,11 @@ +identifier: {{ board }}/nrf54h20/{{ target['core'] }} +name: {{ board_desc }} +vendor: {{ vendor }} +type: mcu +arch: {{ target["arch"] }} +toolchain: + - zephyr +sysbuild: true +ram: {{ target["ram"] }} +flash: {{ target["flash"] }} +supported: [] diff --git a/scripts/west_commands/create_board/templates/nrf54h/pre_dt_board.cmake b/scripts/west_commands/create_board/templates/nrf54h/pre_dt_board.cmake new file mode 100644 index 000000000000..519d7844635e --- /dev/null +++ b/scripts/west_commands/create_board/templates/nrf54h/pre_dt_board.cmake @@ -0,0 +1,2 @@ +# Suppress "unique_unit_address_if_enabled" to handle some overlaps +list(APPEND EXTRA_DTC_FLAGS "-Wno-unique_unit_address_if_enabled") diff --git a/scripts/west_commands/create_board/west-ncs-create-board-test.sh b/scripts/west_commands/create_board/west-ncs-create-board-test.sh index 8e85a549c0f9..d24b7e081e39 100755 --- a/scripts/west_commands/create_board/west-ncs-create-board-test.sh +++ b/scripts/west_commands/create_board/west-ncs-create-board-test.sh @@ -20,6 +20,7 @@ declare -a SOCS=( "nRF52840-QFAA" "nRF52840-QIAA" "nRF5340-QKAA" + "nRF54H20-CKAA" "nRF54L15-QFAA" "nRF9131-LACA" "nRF9151-LACA" @@ -56,6 +57,13 @@ for soc in "${SOCS[@]}"; do west build -p -b $board/$soc_name/cpuapp $HELLO_WORLD west build -p -b $board/$soc_name/cpuapp/ns $HELLO_WORLD west build -p -b $board/$soc_name/cpunet $HELLO_WORLD + elif [[ $soc == nRF54H* ]]; then + west build -p -b $board/$soc_name/cpuapp $HELLO_WORLD + west build -p -b $board/$soc_name/cpurad $HELLO_WORLD + # west build -p -b $board/$soc_name/cpuppr $HELLO_WORLD + # west build -p -b $board/$soc_name/cpuppr/xip $HELLO_WORLD + # west build -p -b $board/$soc_name/cpuflpr $HELLO_WORLD + # west build -p -b $board/$soc_name/cpuflpr/xip $HELLO_WORLD elif [[ $soc == nRF54L* ]]; then west build -p -b $board/$soc_name/cpuapp $HELLO_WORLD # west build -p -b $board/$soc_name/cpuflpr $HELLO_WORLD diff --git a/scripts/west_commands/ncs-bicr.py b/scripts/west_commands/ncs-bicr.py new file mode 100644 index 000000000000..251432dce1df --- /dev/null +++ b/scripts/west_commands/ncs-bicr.py @@ -0,0 +1,88 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +import json +import os +import sys +from pathlib import Path + +import jsonschema +from west.commands import WestCommand + +sys.path.append(str(Path(__file__).parent)) +import utils + + +utils.install_json_excepthook() + + +SCRIPT_DIR = Path(__file__).absolute().parent +SCHEMA = SCRIPT_DIR.parents[2] / "zephyr" / "soc" / "nordic" / "nrf54h" / "bicr" / "bicr-schema.json" + + +class NcsBICR(WestCommand): + def __init__(self): + super().__init__( + "ncs-bicr", + "Assist with board BICR creation for any applicable Nordic SoC", + "" + ) + + def do_add_parser(self, parser_adder): + parser = parser_adder.add_parser( + self.name, help=self.help, description=self.description + ) + + parser.add_argument( + "-d", "--board-dir", type=Path, help="Target board directory" + ) + + group = parser.add_mutually_exclusive_group(required=True) + group.add_argument( + "-s", "--json-schema", action="store_true", help="Provide JSON schema" + ) + group.add_argument( + "-r", "--json-schema-response", type=str, help="JSON schema response" + ) + + return parser + + def do_run(self, args, unknown_args): + board_dir = args.board_dir + if not board_dir: + board_dir = Path(os.getcwd()) + + board_spec = board_dir / "board.yml" + if not board_spec.exists(): + raise FileNotFoundError("Invalid board directory") + + with open(SCHEMA, "r") as f: + schema = json.loads(f.read()) + + bicr_file = board_dir / "bicr.json" + + bicr = None + if args.json_schema and bicr_file.exists(): + with open(bicr_file, "r") as f: + bicr = json.loads(f.read()) + elif args.json_schema_response: + bicr = json.loads(args.json_schema_response) + + if bicr: + try: + jsonschema.validate(bicr, schema) + except jsonschema.ValidationError as e: + raise ValueError("Invalid BICR") from e + + if args.json_schema: + schema = { + "schema": schema, + "state": bicr + } + + print(json.dumps(schema)) + else: + with open(bicr_file, "w") as f: + json.dump(bicr, f, indent=4) + + print(json.dumps({"commands": []})) diff --git a/scripts/west_commands/ncs-board-actions.py b/scripts/west_commands/ncs-board-actions.py new file mode 100644 index 000000000000..83ae770d4446 --- /dev/null +++ b/scripts/west_commands/ncs-board-actions.py @@ -0,0 +1,116 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +import json +import os +import re +import sys +from pathlib import Path + +from west.commands import WestCommand + +sys.path.append(str(Path(__file__).parent)) +import utils + + +utils.install_json_excepthook() + + +SCRIPT_DIR = Path(__file__).absolute().parent +BICRGEN = ( + SCRIPT_DIR.parents[2] + / "zephyr" + / "soc" + / "nordic" + / "nrf54h" + / "bicr" + / "bicrgen.py" +) + + +def soc_series_detect(board_dir): + found_defconfig = None + for defconfig in board_dir.glob("Kconfig.*"): + if defconfig.name == "Kconfig.defconfig": + continue + + found_defconfig = defconfig + break + + if not found_defconfig: + raise FileNotFoundError("Board defconfig file not found") + + with open(found_defconfig, "r") as f: + for line in f.readlines(): + m = re.match(".*select SOC_(NRF[0-9]{2}[A-Z]{,1}).*", line) + if not m: + continue + + return m.group(1).lower() + + raise ValueError("Unsupported board") + + +class NcsBoardActions(WestCommand): + def __init__(self): + super().__init__( + "ncs-board-actions", "Obtain available actions for any board", "" + ) + + def do_add_parser(self, parser_adder): + parser = parser_adder.add_parser( + self.name, help=self.help, description=self.description + ) + + parser.add_argument( + "-d", + "--board-dir", + type=Path, + help="Target board directory (defaults to current working directory)", + ) + + return parser + + def do_run(self, args, unknown_args): + board_dir = args.board_dir + if not board_dir: + board_dir = Path(os.getcwd()) + + board_spec = board_dir / "board.yml" + if not board_spec.exists(): + raise FileNotFoundError("Invalid board directory") + + series = soc_series_detect(board_dir) + commands = [] + + if series == "nrf54h": + commands.extend( + [ + { + "name": "Create/Edit BICR", + "command": "west", + "args": ["ncs-bicr", "--board-dir", str(board_dir.resolve())], + "properties": { + "providesJsonSchema": True, + } + }, + { + "name": "Generate BICR binary", + "command": sys.executable, + "args": [ + str(BICRGEN), + "--svd", + "${SVD_FILE}", + "--input", + str((board_dir / "bicr.json").resolve()), + "--output", + "${BICR_HEX_FILE}", + ], + "properties": { + "providesJsonSchema": False, + } + }, + ] + ) + + print(json.dumps({"commands": commands})) diff --git a/scripts/west_commands/utils/__init__.py b/scripts/west_commands/utils/__init__.py new file mode 100644 index 000000000000..391733757135 --- /dev/null +++ b/scripts/west_commands/utils/__init__.py @@ -0,0 +1,24 @@ +# Copyright (c) 2024 Nordic Semiconductor ASA +# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + +import json +import sys +import traceback + + +def install_json_excepthook(): + def excepthook(type, value, tb): + output = { + "errors": [ + { + "type": type.__name__, + "message": str(value), + "traceback": "".join(traceback.format_tb(tb)) + } + ] + } + + print(json.dumps(output, indent=2), file=sys.stderr) + sys.exit(1) + + sys.excepthook = excepthook diff --git a/west.yml b/west.yml index 2e17d8112053..817075364e28 100644 --- a/west.yml +++ b/west.yml @@ -69,7 +69,7 @@ manifest: # https://developer.nordicsemi.com/nRF_Connect_SDK/doc/latest/zephyr/guides/modules.html - name: zephyr repo-path: sdk-zephyr - revision: ba1d06f7241c1a899b43bdef7b731fa244646a2f + revision: pull/2298/head import: # In addition to the zephyr repository itself, NCS also # imports the contents of zephyr/west.yml at the above