diff --git a/applications/sdp/mspi/src/main.c b/applications/sdp/mspi/src/main.c
index c3e4a6444900..1df6f2e91078 100644
--- a/applications/sdp/mspi/src/main.c
+++ b/applications/sdp/mspi/src/main.c
@@ -24,6 +24,10 @@
 #define DATA_PINS_MAX 8
 #define VIO_COUNT     11
 
+#define STD_PAD_BIAS_CNT0_THRESHOLD 1
+
+#define PAD_BIAS_VALUE 1
+
 #define MAX_SHIFT_COUNT 63
 
 #define CE_PIN_UNUSED UINT8_MAX
@@ -35,6 +39,12 @@
 #define VEVIF_IRQN(vevif)   VEVIF_IRQN_1(vevif)
 #define VEVIF_IRQN_1(vevif) VPRCLIC_##vevif##_IRQn
 
+#ifdef CONFIG_SOC_NRF54L15
+#define NRF_GPIOHSPADCTRL ((NRF_GPIOHSPADCTRL_Type *)NRF_P2_S_BASE)
+#else
+#error "Unsupported SoC for SDP MSPI"
+#endif
+
 BUILD_ASSERT(CONFIG_SDP_MSPI_MAX_RESPONSE_SIZE > 0, "Response max size should be greater that 0");
 
 static const uint8_t pin_to_vio_map[VIO_COUNT] = {
@@ -443,6 +453,13 @@ static void ep_recv(const void *data, size_t len, void *priv)
 		nrfe_mspi_xfer_config = xfer_config->xfer_config;
 #endif
 		configure_clock(nrfe_mspi_devices[nrfe_mspi_xfer_config_ptr->device_index].cpp);
+
+		/* Tune up pad bias for frequencies above 32MHz */
+		if (nrfe_mspi_devices[nrfe_mspi_xfer_config_ptr->device_index].cnt0_value <=
+		    STD_PAD_BIAS_CNT0_THRESHOLD) {
+			NRF_GPIOHSPADCTRL->BIAS = PAD_BIAS_VALUE;
+		}
+
 		break;
 	}
 	case NRFE_MSPI_TX:
diff --git a/drivers/mspi/mspi_nrfe.c b/drivers/mspi/mspi_nrfe.c
index 720dfbffc029..862b042712c7 100644
--- a/drivers/mspi/mspi_nrfe.c
+++ b/drivers/mspi/mspi_nrfe.c
@@ -21,12 +21,13 @@ LOG_MODULE_REGISTER(mspi_nrfe, CONFIG_MSPI_LOG_LEVEL);
 #include <hal/nrf_gpio.h>
 #include <drivers/mspi/nrfe_mspi.h>
 
-#define MSPI_NRFE_NODE		 DT_DRV_INST(0)
-#define MAX_TX_MSG_SIZE		 (DT_REG_SIZE(DT_NODELABEL(sram_tx)))
-#define MAX_RX_MSG_SIZE		 (DT_REG_SIZE(DT_NODELABEL(sram_rx)))
-#define IPC_TIMEOUT_MS		 100
-#define EP_SEND_TIMEOUT_MS	 10
-#define CNT0_TOP_CALCULATE(freq) (NRFX_CEIL_DIV(SystemCoreClock, freq * 2) - 1)
+#define MSPI_NRFE_NODE		     DT_DRV_INST(0)
+#define MAX_TX_MSG_SIZE		     (DT_REG_SIZE(DT_NODELABEL(sram_tx)))
+#define MAX_RX_MSG_SIZE		     (DT_REG_SIZE(DT_NODELABEL(sram_rx)))
+#define IPC_TIMEOUT_MS		     100
+#define EP_SEND_TIMEOUT_MS	     10
+#define EXTREME_DRIVE_FREQ_THRESHOLD 32000000
+#define CNT0_TOP_CALCULATE(freq)     (NRFX_CEIL_DIV(SystemCoreClock, freq * 2) - 1)
 
 #define SDP_MPSI_PINCTRL_DEV_CONFIG_INIT(node_id)                                                  \
 	{                                                                                          \
@@ -439,6 +440,23 @@ static int api_dev_config(const struct device *dev, const struct mspi_dev_id *de
 	}
 
 	if (param_mask & MSPI_DEVICE_CONFIG_FREQUENCY) {
+
+		uint8_t state_id;
+
+		for (state_id = 0; state_id < drv_cfg->pcfg->state_cnt; state_id++) {
+			if (drv_cfg->pcfg->states[state_id].id == PINCTRL_STATE_DEFAULT) {
+				break;
+			}
+		}
+
+		if ((cfg->freq >= EXTREME_DRIVE_FREQ_THRESHOLD) &&
+		    (NRF_GET_DRIVE(drv_cfg->pcfg->states[state_id].pins[0]) != NRF_DRIVE_E0E1)) {
+			LOG_ERR("Invalid pin drive for this frequency: %u, expected: %u",
+				NRF_GET_DRIVE(drv_cfg->pcfg->states[state_id].pins[0]),
+				NRF_DRIVE_E0E1);
+			return -EINVAL;
+		}
+
 		if (cfg->freq > drv_cfg->mspicfg.max_freq) {
 			LOG_ERR("Invalid frequency: %u, MAX: %u", cfg->freq,
 				drv_cfg->mspicfg.max_freq);