doc: nrfxlib doc check fixes

Applied several formatting and style edits.
Checked documentation before NCS 1.7.0 release.
NCSDK-11020.

Signed-off-by: Grzegorz Ferenc <[email protected]>

Author: greg-fer

mpsl/doc/clock.rst

@@ -1,22 +1,23 @@
 .. _mpsl_clock:
 
 MPSL Clock
-**********
+##########
 
-The MPSL clock module provides access to the low-frequency clock (LFCLK) configuration and allows the application to request the crystal oscillator source of the high-frequency clock (HFCLK).
+.. contents::
+    :local:
+    :depth: 2
 
-Design description
-==================
+The MPSL clock module provides access to the low-frequency clock (LFCLK) configuration and allows the application to request the crystal oscillator source of the high-frequency clock (HFCLK).
 
-See the following <Low-frequency clock (LFCLK)>_ and <High-frequency clock (HFCLK)>_ sections for a description of the design.
+See the following `Low-frequency clock (LFCLK)`_ and `High-frequency clock (HFCLK)`_ sections for a description of the design.
 
 Low-frequency clock (LFCLK)
----------------------------
+***************************
 
-MPSL can use one of the two available low-frequency clock (LFCLK) sources:
+MPSL can use one of the following available low-frequency clock (LFCLK) sources:
 
-* the 32.768 kHz internal RC oscillator (LFRC)
-* the 32.768 kHz crystal oscillator (LFXO)
+* 32.768 kHz internal RC oscillator (LFRC)
+* 32.768 kHz crystal oscillator (LFXO)
 
 When MPSL is enabled, the application must provide the selected LFCLK source, calibration configurations, and clock accuracy.
 The selected accuracy is meant to be forwarded only to the protocol stacks.
@@ -35,7 +36,7 @@ As the MPSL clock module runs the calibration automatically, the application mus
    It is recommended to use a temperature polling interval of 4 seconds, and to force the clock calibration every second interval (``.rc_ctiv=16``, ``.rc_temp_ctiv=2``).
 
 High-frequency clock (HFCLK)
-----------------------------
+****************************
 
 The high-frequency clock (HFCLK) controller supports the following HFCLK sources:
 

mpsl/doc/fem.rst

@@ -20,11 +20,12 @@ Implementation
 
 Two FEM implementations are provided:
 
-* *nRF21540 GPIO*.
-  It is compatible with the nRF21540 FEM and implements a 3-pin interface.
-* *Simple GPIO*.
-  It is a simplified version, made to be compatible with other front-end modules.
-  It implements a 2-pin interface.
+* nRF21540 GPIO.
+   It is compatible with the nRF21540 FEM and implements a 3-pin interface.
+
+* Simple GPIO.
+   It is a simplified version, made to be compatible with other front-end modules.
+   It implements a 2-pin interface.
 
 Both implementations use PA and LNA pins for controlling the FEM.
 Additionally, the nRF21540 GPIO implementation uses the PDN pin for powering down the FEM internal circuits, to reduce energy consumption.

mpsl/doc/mpsl.rst

@@ -13,6 +13,7 @@ The descriptions are valid for both RTOS and RTOS-free environments.
 For the nRF53 Series, the requirements described are only relevant for applications running alongside the MPSL on the network processor.
 
 The following peripherals are owned by MPSL and must not be accessed directly by the application:
+
  * ``RTC0``
  * ``TIMER0``
  * ``TIMER1`` (for the nRF53 Series)