diff --git a/CODEOWNERS b/CODEOWNERS index f486614bd1..e5aba96e99 100644 --- a/CODEOWNERS +++ b/CODEOWNERS @@ -47,4 +47,4 @@ doc/* @b-gent /lc3/ @koffes @alexsven /nrf_fuel_gauge/ @nordic-auko /nrf_wifi/ @udaynordic @rajb9 @srkanordic -/softperipheral/ @lopeztel +/softperipheral/ @lopeztel @nordavid531 @ostenholkestad @bikleppe diff --git a/softperipheral/CHANGELOG.rst b/softperipheral/CHANGELOG.rst index b06e8ccfc4..73c7817a95 100644 --- a/softperipheral/CHANGELOG.rst +++ b/softperipheral/CHANGELOG.rst @@ -9,6 +9,21 @@ Changelog All the notable changes to this project are documented on this page. +nRF Connect SDK v3.2.0 +********************** + +This version contains an initial release of the Soft Peripheral sEMMC. +See the following list of changes: + +* Added: + + * The first implementation of Soft Peripheral sEMMC for nRF54H Series and nRF54L Series SoCs. + For details, see the :ref:`semmc_changelog` page. + + * New virtual register for sQSPI. + It updates sQSPI to version 1.2.0 and also supports the nRF54LM20 device. + For details, see the :ref:`sqspi_changelog` page. + nRF Connect SDK v3.1.0 ********************** diff --git a/softperipheral/README.rst b/softperipheral/README.rst index 93d0e4ee29..37f2c4baf7 100644 --- a/softperipheral/README.rst +++ b/softperipheral/README.rst @@ -17,4 +17,5 @@ It covers setup, integration, and operational guidelines for using each soft per doc/introduction.rst doc/sQSPI/README.rst + doc/sEMMC/README.rst CHANGELOG.rst diff --git a/softperipheral/doc/introduction.rst b/softperipheral/doc/introduction.rst index a52a2b6fde..5073f0006a 100644 --- a/softperipheral/doc/introduction.rst +++ b/softperipheral/doc/introduction.rst @@ -13,7 +13,7 @@ It also allows to include additional instances of a peripheral in case the platf In most cases, the features and performance of a soft peripheral are equivalent to those of a hardware peripheral. However, there may be some limitations. -For more information, see the :ref:`sqspi_limitations` page. +For more information, see the :ref:`sqspi_limitations` and :ref:`semmc_limitations` pages. The operation of a soft peripheral is abstracted, and its control is facilitated through a user interface managed through the nrfx driver API. This user interface is a set of functions that the application can call to interact with the peripheral. @@ -26,7 +26,9 @@ The following image shows the software stack of an application: .. note:: Note that in both the documentation and source files, soft peripherals are referred to by prefixing the letter *s* before the name of the peripheral. - For example, ``sQSPI``. + For example, ``sQSPI`` or ``sEMMC``. + +.. _intro_soft_peripherals_platform_support: Platform support **************** @@ -41,12 +43,25 @@ The following table shows which soft peripherals and their versions are supporte - Hardware platform - Version * - sQSPI - - - nRF54L15 SoC - - nRF54H20 SoC + - - nRF54L Series SoCs + - nRF54H Series SoCs + - - nRF54L15 SoC: + - v0.1.0 with the NCS v3.0.0 + - v1.0.0 with the NCS v3.1.0 + - v1.1.0 with the NCS v3.1.0 + - v1.2.0 with the NCS v3.2.0 + - nRF54LM20 SoC: + - v1.2.0 with the NCS v3.2.0 + - nRF54H20 SoC: + - v0.1.0 with the NCS v3.0.0 + - v1.1.0 with the NCS v3.1.0 + - v1.2.0 with the NCS v3.2.0 + * - sEMMC + - - nRF54L Series SoCs + - nRF54H Series SoCs - - nRF54L15 SoC: - - v0.1.0 with NCS v3.0.0 - - v1.0.0 with NCS v3.1.0 - - v1.1.0 with NCS v3.1.0 + - v0.1.0 with the NCS v3.2.0 + - nRF54LM20 SoC: + - v0.1.0 with the NCS v3.2.0 - nRF54H20 SoC: - - v0.1.0 with NCS v3.0.0 - - v1.1.0 with NCS v3.1.0 + - v0.1.0 with the NCS v3.2.0 diff --git a/softperipheral/doc/sEMMC/CHANGELOG.rst b/softperipheral/doc/sEMMC/CHANGELOG.rst new file mode 100644 index 0000000000..9c37c35917 --- /dev/null +++ b/softperipheral/doc/sEMMC/CHANGELOG.rst @@ -0,0 +1,28 @@ +.. _semmc_changelog: + +sEMMC changelog +############### + +.. contents:: + :local: + :depth: 2 + +All the notable changes to sEMMC are documented on this page. +Refer to :ref:`intro_soft_peripherals_platform_support` for supported Nordic devices for each version. + +v0.1.0 +****** + +This is an initial release. + +* Added the following support for the nRF54H Series and nRF54L Series devices: + + * 1-lane and 4-lane data transmission + * Class 0 commands - Basic + * Class 2 commands - Block read + * Class 4 commands - Block write + * Class 5 commands - Erase + * Class 6 commands - Write protection + * Class 7 commands - Lock device + * Class 11 commands - Command queuing + * All response types diff --git a/softperipheral/doc/sEMMC/README.rst b/softperipheral/doc/sEMMC/README.rst new file mode 100644 index 0000000000..ff72ff7925 --- /dev/null +++ b/softperipheral/doc/sEMMC/README.rst @@ -0,0 +1,27 @@ +.. _sEMMC: + +sEMMC +##### + +.. contents:: + :local: + :depth: 2 + +This documentation outlines the sEMMC Soft Peripheral. +It covers setup, integration, and operational guidelines for using sEMMC through the nrfx driver API, alongside detailed descriptions of limitations and performance considerations. + +.. note:: + The current version of sEMMC is based on JEDEC Standard No. 84-B51A. + +.. toctree:: + :maxdepth: 1 + :glob: + :caption: Subpages: + + features.rst + semmc_nrf54L_series_porting_v0_1_0.rst + semmc_nrf54H_series_porting_v0_1_0.rst + timing.rst + CHANGELOG.rst + limitations.rst + api_reference.rst diff --git a/softperipheral/doc/sEMMC/api_reference.rst b/softperipheral/doc/sEMMC/api_reference.rst new file mode 100644 index 0000000000..1535962e79 --- /dev/null +++ b/softperipheral/doc/sEMMC/api_reference.rst @@ -0,0 +1,4 @@ +API Reference +############# + +.. doxygengroup:: nrf_semmc diff --git a/softperipheral/doc/sEMMC/features.rst b/softperipheral/doc/sEMMC/features.rst new file mode 100644 index 0000000000..7278899fe7 --- /dev/null +++ b/softperipheral/doc/sEMMC/features.rst @@ -0,0 +1,41 @@ +.. _semmc_features: + +sEMMC features +############## + +.. contents:: + :local: + :depth: 2 + +This page provides an overview of the functionalities and configurations available for the Soft Peripheral sEMMC for the current state of development. +See the following sections for more details. + +.. _semmc_features_command_support: + +Command support +*************** + +sEMMC supports the following JEDEC Standard No. 84-B51A command groups: + +* Class 0 - Basic +* Class 2 - Block read +* Class 4 - Block write +* Class 5 - Erase +* Class 6 - Write protection +* Class 7 - Lock device +* Class 11 - Command queuing + +.. note:: + Refer to the :file:`nrf_semmc.h` header for a list of supported commands. + +.. _semmc_features_hs200_mode: + +HS200 mode support +****************** + +sEMMC supports the HS200 mode for high-speed transfers. +This allows sEMMC to operate at frequencies up to 80MHz on the nRF54H20 device. + +.. note:: + You need to perform a tuning cycle using CMD21 to find the optimal sampling point for reads. + After completing the tuning cycle, set the sampling value in the :c:var:`nrf_semmc_config_t.read_delay` variable. diff --git a/softperipheral/doc/sEMMC/limitations.rst b/softperipheral/doc/sEMMC/limitations.rst new file mode 100644 index 0000000000..3121863766 --- /dev/null +++ b/softperipheral/doc/sEMMC/limitations.rst @@ -0,0 +1,27 @@ +.. _semmc_limitations: + +sEMMC limitations +################# + +When working with sEMMC, you should be aware of the following limitations. + +.. contents:: + :local: + :depth: 2 + +v0.1.0 +****** + +Refer to the following detailed descriptions of current limitations: + +* sEMMC does not support octal-lane data transmissions. +* sEMMC does not support dual data rate, and as such no support for HS400. +* :c:var:`nrf_semmc_config_t.read_delay` can not be equal to or higher than the :c:var:`clkdiv` parameter in :ref:`semmc_timing`. +* :c:var:`clkdiv` parameter in :ref:`semmc_timing` must be even. +* Maximum frequency is limited to 80MHz on nRF54H Series (assuming a maximum device frequency of 320MHz, in HS200 mode) and 32MHz on nRF54L Series devices. +* A tuning cycle using CMD21 might be needed to set the proper value of :c:var:`nrf_semmc_config_t.read_delay`. +* Data buffers and response buffers needs to be pointers with a 32-bit aligned address. +* :c:var:`nrf_emmc_data_t.block_size` needs to be minimum 4 bytes for quad-lane data transmissions. +* Setting :c:var:`nrf_semmc_config_t.process_response` to ``NRF_EMMC_RESPONSE_PROC_IGNORE`` will only apply to any transaction in the read direction. +* sEMMC is not able to process response and data at the same time. See for example :ref:`semmc_nrf54H_series_porting_guide_read_response` on how to mitigate this. +* Any prepared transfer with :c:func:`nrf_semmc_cmd_prepare` will be discarded when using :c:func:`nrf_semmc_disable`. diff --git a/softperipheral/doc/sEMMC/semmc_nrf54H_series_porting_v0_1_0.rst b/softperipheral/doc/sEMMC/semmc_nrf54H_series_porting_v0_1_0.rst new file mode 100644 index 0000000000..9b87a655f3 --- /dev/null +++ b/softperipheral/doc/sEMMC/semmc_nrf54H_series_porting_v0_1_0.rst @@ -0,0 +1,319 @@ +.. _semmc_nrf54H_series_porting_guide: + +sEMMC nRF54H Series porting guide +################################# + +.. contents:: + :local: + :depth: 2 + +This page provides a comprehensive overview of the code structure, file hierarchy, and essential configurations and requirements needed to successfully port and implement an sEMMC application on an nRF54H Series device. + +.. _semmc_nrf54h_series_porting_guide_code: + +sEMMC application code +********************** + +This structure shows the relevant files and directories in the `sdk-nrfxlib`_ repository: + +.. code-block:: + + nrfxlib/ + ├──... + └── softperipheral/ + ├── include + │ ├── softperipheral_meta.h + │ └── softperipheral_regif.h + ├── ... + └── sEMMC + ├── include + │ ├── hal + │ │ └── nrf_emmc.h + │ ├── nrf54h + │ │ ├── semmc_firmware.h + │ │ └── semmc_firmware_v0.1.0.h + │ │ └── ... + │ ├── nrf_config_semmc.h + │ ├── nrf_sp_emmc.h + │ ├── nrf_semmc.h + └── src + └── nrf_semmc.c + +.. note:: + The main interface for sEMMC is in the :file:`nrf_semmc.h` file. + It contains a list of supported and tested EMMC commands. + +Header files +============ + +sEMMC application requires specific header files used by the driver code. +You must include paths to these files in the build environment's list of include paths. +The following list is a detailed breakdown of the necessary paths: + +* Repository internal paths: + + * :file:`softperipheral/include` - Soft peripherals register interface and metadata + * :file:`softperipheral/sEMMC/include` - sEMMC register interface and driver header + * :file:`softperipheral/sEMMC/include/nrf54h` - The sEMMC firmware for the Fast Lightweight Perpipheral Processor (FLPR) + +To override the configuration enums in :file:`nrf_config_semmc.h`, use the ``zephyr_compile_definitions`` macro in your application: + +.. code-block:: c + + // Example call for enabling the sEMMC + zephyr_compile_definitions("NRF_SEMMC_ENABLED=1") + +Compiling source files +====================== + +For a sEMMC application to function properly, you must compile the driver implementation from the source file :file:`nrf_semmc.c`. + +Application core and FLPR configuration +*************************************** + +You must adjust the settings for the nRF54H Series SoC to run at highest base clock frequency. + +To work with any of the following settings, ensure you have allocated memory for the data pointers used by the sEMMC driver. +The memory is independent from the one outlined in the :ref:`semmc_nrf54H_series_porting_guide_ram_configuration` subsection. +It is designated to function as shared memory for communication purposes, rather than containing the sEMMC executable code. + +Security configuration +====================== + +Configure the security settings for the nRF54H Series device based on the operational requirements of your application. + +Secure environment +------------------ + +In a secure configuration, both the application core and the FLPR core of the nRF54H Series device must operate within a secure environment enabled by TrustZone Secure. + +Non-secure environment +---------------------- + +In a non-secure configuration, both the application core and the FLPR core of the nRF54H Series device must operate outside the secure environment (without TrustZone Secure). + +.. _semmc_nrf54h_series_porting_guide_gpio_config: + +GPIO configuration +****************** + +The provided table details the configuration for each GPIO pin used in the sEMMC application. +The following options are available, assuming that the FLPR core has access to these ports and pins: + + .. list-table:: + :widths: 10 10 20 20 20 + :header-rows: 1 + + * - GPIO pin + - sEMMC role + - Direction config + - Input config + - Pin pull config + * - **P7.0** + - D3 + - Output + - Disconnected + - Pull-up + * - **P7.1** + - CLK + - Output + - Disconnected + - Pull-down + * - **P7.2** + - D0 + - Output + - Disconnected + - Pull-up + * - **P7.3** + - D2 + - Output + - Disconnected + - Pull-up + * - **P7.4** + - D1 + - Output + - Disconnected + - Pull-up + * - **P7.5** + - CMMD + - Output + - Disconnected + - Pull-up + +Configuring pins +================ + +In some cases, you might have to modify the sEMMC driver configuration. +For example, you might need to change the pin drive strength to guarantee signal integrity for a new PCB design. +You must address these cases on the sEMMC application code. + +.. note:: + When using a custom PCB with the nRF54H20 device you might need to match the output impedance on the port you are using. + Refer to the :ref:`nrf:ug_nrf54h20_custom_pcb` page for details. + +GPIO multiplexing must be handled by setting the correct ``CTRLSEL`` value in UICR. + +Any conflicting peripherals and existing memory partitions on the same port as sEMMC must be disabled in the devicetree overlay, depending on your requirements. +See an example code snippet of a devicetree overlay that grants FLPR access to the necessary pins. + +The first part of the snippet, the ``pinctrl`` block, configures the relevant GPIOs as described in the :ref:`semmc_nrf54h_series_porting_guide_gpio_config` section. + +Next, the ``cpuflpr_vpr`` block and the subsequent block handle the allocation of the VPR memory region and the RAM used by sEMMC. + +.. code-block:: dts + + &pinctrl { + semmc_default: semmc_default { + group1 { + psels = ; + nordic,drive-mode = ; + bias-pull-down; + }; + group2 { + psels = , + , + , + , + , + ; + nordic,drive-mode = ; + bias-pull-up; + }; + }; + semmc_sleep: semmc_sleep { + group1 { + low-power-enable; + psels = , + , + , + , + , + , + ; + }; + }; + }; + + &cpuflpr_vpr { + pinctrl-0 = <&semmc_default>; + pinctrl-1 = <&semmc_sleep>; + pinctrl-names = "default"; + interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>; + status = "okay"; + /delete-property/ execution-memory; + }; + + /delete-node/ &cpuflpr_code_data; + /delete-node/ &cpuapp_cpuflpr_ipc_shm; + /delete-node/ &cpuflpr_cpuapp_ipc_shm; + /delete-node/ &cpuapp_cpuflpr_ipc; + / { + reserved-memory { + softperiph_ram: memory@2f890000 { + reg = <0x2f890000 0x4140>; + ranges = <0 0x2f890000 0x4140>; + #address-cells = <1>; + #size-cells = <1>; + + dut: semmc: semmc@3f40 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3f40 0x200>; + zephyr,pm-device-runtime-auto; + memory-regions = <&semmc_buffers>; + }; + }; + + semmc_buffers: memory@2f894140 { + compatible = "zephyr,memory-region"; + reg = <0x2f894140 0x4000>; + #memory-region-cells = <0>; + zephyr,memory-region = "SEMMC_BUFFERS"; + zephyr,memory-attr = ; + }; + }; + }; + +You will need the following lines in your application to apply the pin configuration from your sEMMC board DTS overlay, as well as to initialize the Soft Peripheral: + +.. code-block:: c + + #define VPR_NODE DT_NODELABEL(cpuflpr_vpr) + #define SP_REGIF_BASE DT_REG_ADDR(DT_NODELABEL(semmc)) + + // The following lines in your setup function will apply the FLPR pins to PINCTRL + PINCTRL_DT_DEFINE(VPR_NODE); + int rc = pinctrl_apply_state(PINCTRL_DT_DEV_CONFIG_GET(VPR_NODE), PINCTRL_STATE_DEFAULT); + zassert_true(rc >= 0, "Pins not configured properly! Returned with code: 0x&X\t\n", rc); + + // The following line initializes sEMMC + static nrf_semmc_t m_semmc = {.p_reg = (void *)SP_REGIF_BASE, .drv_inst_idx = 0}; + + +.. _semmc_nrf54H_series_porting_guide_ram_configuration: + +RAM configuration +***************** + +The sEMMC Soft Peripheral operates from RAM. + +.. note:: + sEMMC supports Position Independent Code (PIC), which allows an application to determine where to load the Soft Peripheral firmware. + +Your build environment must reserve the required RAM and ensure that it is readable and writable by both the application core and the FLPR core. +The following table details the memory region, which should be non-cacheable: + +.. list-table:: RAM Configuration Table + :widths: auto + :header-rows: 1 + + * - Component + - Address offset + - Size + * - sEMMC firmware + - ``SP_FIRMWARE_ADDR`` + - 0x3740 + * - sEMMC execution RAM + - ``SP_FIRMWARE_ADDR`` + 0x3740 + - 0x600 + * - sEMMC virtual register interface + - ``SP_FIRMWARE_ADDR`` + 0x3D40 + - 0x200 + * - Context saving + - 0x2f890000 + - 0x200 (but the entire block should be retained) + +The build environment described in the :ref:`semmc_nrf54h_series_porting_guide_code` section, you must comply with these requirements. +This includes proper settings in linker scripts, device tree specifications (DTS), and resource allocation. + +Ensure that ``SP_FIRMWARE_ADDR`` is set so that it does not overlap with the context saving address. +For nRF54H Series devices, the firmware has been tested using values that follow the context saving address. +This means, that ``SP_FIRMWARE_ADDR`` should be set higher than the context saving address plus the context saving offset. +The value ``0x2f890200`` for ``SP_FIRMWARE_ADDR`` has been tested and is considered production-ready. + + +IRQ connection +************** + +For sEMMC to communicate with the application core, the sEMMC IRQ handler must be registered. +The following code line registers the IRQ handler to FLPR: + +.. code-block:: c + + IRQ_CONNECT(DT_IRQN(VPR_NODE), DT_IRQ(VPR_NODE, priority), nrfx_isr, nrf_semmc_irq_handler, 0); + + +.. _semmc_nrf54H_series_porting_guide_read_response: + +Read responses +************** + +sEMMC cannot process read data and response at the same time (see the :ref:`semmc_limitations`). +However, you can mitigate it in the following ways: + +* The recommended way is to perform the read operation with the :c:var:`nrf_semmc_config_t.process_response` variable set to ``NRF_EMMC_RESPONSE_PROC_PROCESS``. + The response is available in the :c:var:`nrf_semmc_cmd_desc_t.err` variable. + If the response is ``NRF_SEMMC_SUCCESS``, the read was successful. + If you receive a different response, retry the read operation, this time with the :c:var:`nrf_semmc_config_t.process_response` variable set to ``NRF_EMMC_RESPONSE_PROC_IGNORE``. + +* Alternatively, you can perform the read operation with the :c:var:`nrf_semmc_config_t.process_response` variable set to ``NRF_EMMC_RESPONSE_PROC_IGNORE``, and then follow it with a CMD13 command to verify if the status is correct. diff --git a/softperipheral/doc/sEMMC/semmc_nrf54L_series_porting_v0_1_0.rst b/softperipheral/doc/sEMMC/semmc_nrf54L_series_porting_v0_1_0.rst new file mode 100644 index 0000000000..8d7be8a23b --- /dev/null +++ b/softperipheral/doc/sEMMC/semmc_nrf54L_series_porting_v0_1_0.rst @@ -0,0 +1,324 @@ +.. _semmc_nrf54l_series_porting_guide: + +sEMMC nRF54L Series porting guide +################################# + +.. contents:: + :local: + :depth: 2 + +This page provides a comprehensive overview of the code structure, file hierarchy, and essential configurations and requirements needed to successfully port and implement an sEMMC application on the nRF54L Series device. + +.. _semmc_nrf54l_series_porting_guide_code: + +sEMMC application code +********************** + +This structure shows the relevant files and directories in the `sdk-nrfxlib`_ repository: + +.. code-block:: + + nrfxlib/ + ├──... + └── softperipheral/ + ├── include + │ ├── softperipheral_meta.h + │ └── softperipheral_regif.h + ├── ... + └── sEMMC + ├── include + │ ├── hal + │ │ └── nrf_emmc.h + │ ├── nrf54l + │ │ ├── semmc_firmware.h + │ │ └── semmc_firmware_v0.1.0.h + │ │ └── ... + │ ├── nrf_config_semmc.h + │ ├── nrf_sp_emmc.h + │ ├── nrf_semmc.h + └── src + └── nrf_semmc.c + +.. note:: + The main interface for sEMMC is the :file:`nrf_semmc.h` file. + It contains a list of supported and tested EMMC commands. + +Header files +============ + +sEMMC application requires specific header files used by the driver code (internal paths) and specific header files for nrfx (external dependencies). +You must include paths to these files in the build environment's list of include paths. +The following list is a detailed breakdown of the necessary paths: + +* Repository internal paths: + + * :file:`softperipheral/include` - Soft peripherals register interface and metadata + * :file:`softperipheral/sEMMC/include` - sEMMC register interface and driver header + * :file:`softperipheral/sEMMC/include/nrf54l` - The sEMMC firmware for the Fast Lightweight Perpipheral Processor (FLPR) + +* External dependencies: + + * :file:`nrfx` - Includes the main nrfx header file (:file:`nrfx.h`) and hal, which is sometimes necessary for additional GPIO configuration. + * :file:`nrfx/drivers/include` - Includes the nrfx driver header files. + For example, the :file:`nrfx_dppi.h` file. + * Path to the application-specific headers and macros. + For example, the :file:`nrfx_glue.h`, :file:`nrfx_log.h`, or a configuration header file. + See an example configuration for the :file:`nrfx_config.h` file (valid for all nRF54L Series devices): + +.. code-block:: c + + #ifndef NRFX_CONFIG_H__ + #define NRFX_CONFIG_H__ + + #include "softperipheral_regif.h" // To Resolve correct VPR IRQn for the SoC. + #define nrf_semmc_irq_handler SP_VPR_IRQHandler + + #define NRF_SEMMC_ENABLED (1) + #define NRF_SEMMC_RESPONSE_SIZE (4) + + + #endif // NRFX_CONFIG_H__ + +Compiling source files +====================== + +For an sEMMC application to function properly, you must compile the driver implementation from the source file by including :file:`nrf_semmc.c` at the top of your application. + +Application core and FLPR configuration +*************************************** + +You must adjust the settings for the nRF54L Series SoC to run at highest base clock frequency. +To work with any of the following settings, ensure you have completed the following: + +* You have allocated memory for the data pointers used by the sEMMC driver. + The memory is independent from the one outlined in the :ref:`semmc_nrf54l_series_porting_guide_ram_configuration` subsection. + It is designated to function as shared memory for communication purposes, rather than containing the sEMMC executable code. + +* You have enabled the FLPR access to the ``MEMCONF`` peripheral. + This access is necessary to properly disable sEMMC. + +Security configuration +====================== + +Configure the security settings for the nRF54L Series device based on the operational requirements of your application. + +Secure environment +------------------ + +In a secure configuration, both the application core and the FLPR core of the nRF54L Series device must operate within a secure environment enabled by TrustZone Secure. + +The following example code snippet shows how the application code can configure permissions for the FLPR instance: + +.. code-block:: c + + // NOTE: Setting FLPR to secure + NRF_SPU00_S->PERIPH[0xC].PERM = (SPU_PERIPH_PERM_SECATTR_Secure << SPU_PERIPH_PERM_SECATTR_Pos); + +Non-secure environment +---------------------- + +In a non-secure configuration, both the application core and the FLPR core of the nRF54L Series device must operate outside the secure environment (without TrustZone Secure). + +GPIO configuration +****************** + +The provided table details the configuration for each GPIO pin used in the sEMMC application. +You will also need to set the drive strength of the pins to extra high drive. +The following option is possible on nRF54L Series devices, assuming that the FLPR core has access to these ports and pins: + +.. list-table:: + :widths: 10 10 20 20 20 + :header-rows: 1 + + * - GPIO pin + - sEMMC role + - Direction config + - Input config + - Pin pull config + * - **P2.0** + - D3 + - Output + - Disconnected + - Pull-up + * - **P2.1** + - CLK + - Output + - Disconnected + - Pull-down + * - **P2.2** + - D0 + - Output + - Disconnected + - Pull-up + * - **P2.3** + - D2 + - Output + - Disconnected + - Pull-up + * - **P2.4** + - D1 + - Output + - Disconnected + - Pull-up + * - **P2.5** + - CMMD + - Output + - Disconnected + - Pull-up + +This code snippet shows how you can set up these pins in your application: + +.. code-block:: c + + uint32_t io[6] = { + NRF_PIN_PORT_TO_PIN_NUMBER(1, 2), //CLK + NRF_PIN_PORT_TO_PIN_NUMBER(2, 2), //D0 + NRF_PIN_PORT_TO_PIN_NUMBER(4, 2), //D1 + NRF_PIN_PORT_TO_PIN_NUMBER(3, 2), //D2 + NRF_PIN_PORT_TO_PIN_NUMBER(0, 2), //D3 + NRF_PIN_PORT_TO_PIN_NUMBER(5, 2) //CMMD + }; + nrf_gpio_cfg(io[0], NRF_GPIO_PIN_DIR_OUTPUT, + NRF_GPIO_PIN_INPUT_DISCONNECT, NRF_GPIO_PIN_PULLDOWN, + NRF_GPIO_PIN_E0E1, NRF_GPIO_PIN_NOSENSE); + for (int i = 1; i < 6; i++) { + nrf_gpio_cfg(io[i], NRF_GPIO_PIN_DIR_OUTPUT, NRF_GPIO_PIN_INPUT_DISCONNECT, + NRF_GPIO_PIN_PULLUP, NRF_GPIO_PIN_E0E1, NRF_GPIO_PIN_NOSENSE); + } + for (int i = 0; i < 6; i++) { + nrf_gpio_pin_control_select(io[i], NRF_GPIO_PIN_SEL_VPR); + } + +.. _semmc_nrf54L_series_porting_guide_high_speed_transfers: + +High speed transfers +==================== + +To enable communcation at 32MHz on an nRF54L Series device, you need to set the bias of the GPIOHSPADCTRL module. +The following code snippet shows how you can set the value in your application: + +.. code-block:: c + + gpiohs_bias_val = 0x2; + NRF_GPIOHSPADCTRL->BIAS = gpiohs_bias_val; + +Memory retention configuration +****************************** + +The sEMMC soft peripheral requires RAM retention in order to go into the lowest power consumption mode, which can be called through the :c:func:`nrf_semmc_disable` function. + +Assuming there is an access to the peripheral ``MEMCONF``, the following code snippet illustrates how to enable FLPR RAM retention, followed by disabling and re-enabling, and finally how to disable RAM retention: + +.. code-block:: c + + // Disable sequence + nrf_memconf_ramblock_ret_enable_set(NRF_MEMCONF, 1, MEMCONF_POWER_RET_MEM0_Pos, true); + nrf_semmc_disable(&m_semmc); + // Enable sequence + nrf_semmc_enable(&m_semmc); + nrf_memconf_ramblock_ret_enable_set(NRF_MEMCONF, 1, MEMCONF_POWER_RET_MEM0_Pos, false); + +.. _semmc_nrf54L_series_porting_guide_ram_configuration: + +RAM configuration +***************** + +The sEMMC Soft Peripheral operates from RAM. + +.. note:: + sEMMC supports Position Independent Code (PIC). + This allows an application to determine where to load the Soft Peripheral firmware. + +Your build environment must reserve the required RAM and ensure that it is readable and writable by both the application core and the FLPR core. +The following table details the memory regions required for your nRF54L Series device: + +.. tabs:: + + .. tab:: **nRF54L15** + + .. list-table:: nRF54L15 RAM Configuration Table + :widths: auto + :header-rows: 1 + + * - Component + - Address offset + - Size + * - sEMMC firmware + - ``SP_FIRMWARE_ADDR`` + - 0x3C00 + * - sEMMC execution RAM + - ``SP_FIRMWARE_ADDR`` + 0x3C00 + - 0x600 + * - sEMMC virtual register interface + - ``SP_FIRMWARE_ADDR`` + 0x4200 + - 0x200 + * - Context saving + - 0x2003FE00 + - 0x200 (but the entire block should be retained) + + .. tab:: **nRF54LM20** + + .. list-table:: nRF54LM20 RAM Configuration Table + :widths: auto + :header-rows: 1 + + * - Component + - Address offset + - Size + * - sEMMC firmware + - ``SP_FIRMWARE_ADDR`` + - 0x3C00 + * - sEMMC execution RAM + - ``SP_FIRMWARE_ADDR`` + 0x3C00 + - 0x600 + * - sEMMC virtual register interface + - ``SP_FIRMWARE_ADDR`` + 0x4200 + - 0x200 + * - Context saving + - 0x2007FD40 + - 0x200 (but the entire block should be retained) + +The build environment described in the :ref:`semmc_nrf54l_series_porting_guide_code` section must comply with these requirements. +This includes proper settings in linker scripts, device tree specifications (DTS), and resource allocation. + +To initialize the sEMMC struct on an nRF54L Series device, use the following lines: + + .. code-block:: c + + #define SP_REGIF_BASE (SP_FIRMWARE_ADDR + 0x4200) + + // Initialize sEMMC with the virtual register interface placed at SP_REGIF_BASE + static nrf_semmc_t m_semmc = {.p_reg = (void *)SP_REGIF_BASE, .drv_inst_idx = 0}; + +Ensure that ``SP_FIRMWARE_ADDR`` is set so that it does not overlap with the context saving address. +For nRF54L Series devices, the firmware is placed before the context saving address. +This means, that ``SP_FIRMWARE_ADDR`` plus the component sizes listed in the table must be of a lower value than the context saving address. + +The values in the table below have been tested and are considered production-ready for ``SP_FIRMWARE_ADDR``: + +.. list-table:: sEMMC firmware address values + :widths: 15 20 + :header-rows: 1 + + * - Device + - `SP_FIRMWARE_ADDR` + * - nRF54L15 + - 0x2003B400 + * - nRF54LM20 + - 0x2007B400 + + +.. _semmc_nrf54L_series_porting_guide_read_response: + +Read responses +************** + +sEMMC cannot process read data and response at the same time (see the :ref:`semmc_limitations`). +However, you can mitigate it in the following ways: + +* The recommended way is to perform the read operation with the :c:var:`nrf_semmc_config_t.process_response` variable set to ``NRF_EMMC_RESPONSE_PROC_PROCESS``. + The response is available in the :c:var:`nrf_semmc_cmd_desc_t.err` variable. + If the response is ``NRF_SEMMC_SUCCESS``, the read was successful. + If you receive a different response, retry the read operation, this time with the :c:var:`nrf_semmc_config_t.process_response` variable set to ``NRF_EMMC_RESPONSE_PROC_IGNORE``. + +* Alternatively, you can perform the read operation with the :c:var:`nrf_semmc_config_t.process_response` variable set to ``NRF_EMMC_RESPONSE_PROC_IGNORE``, and then follow it with a CMD13 command to verify if the status is correct. diff --git a/softperipheral/doc/sEMMC/timing.rst b/softperipheral/doc/sEMMC/timing.rst new file mode 100644 index 0000000000..e1c72bb3ac --- /dev/null +++ b/softperipheral/doc/sEMMC/timing.rst @@ -0,0 +1,33 @@ +.. _semmc_timing: + +sEMMC and FLPR counters +####################### + +The sEMMC API translates the parameter :c:var:`nrf_semmc_config_t.clk_freq_hz` into a value that can be used by FLPR's internal counters. +The translation has the following constraints (assuming the SoC is running at highest base clock frequency): + +.. tabs:: + + .. tab:: **nRF54L15** + .. math:: + max\_device\_freq\_hz=128000000 + + .. tab:: **nRF54LM20** + .. math:: + max\_device\_freq\_hz=128000000 + + .. tab:: **nRF54H20** + .. math:: + max\_device\_freq\_hz=320000000 + +The maximum core frequency of the device translates to a clock divider used in FLPR's internal counters: + +.. math:: + clkdiv=\frac{max\_device\_freq\_hz}{nrf\_semmc\_config\_t.clk\_freq\_hz} + +.. math:: + FLPR\_counter= + \begin{cases} + \frac{clkdiv}{2}-1,& \text{if } clkdiv > 2\\ + 0, & \text{otherwise} + \end{cases} diff --git a/softperipheral/doc/sQSPI/CHANGELOG.rst b/softperipheral/doc/sQSPI/CHANGELOG.rst index 9815448761..8af3fd091a 100644 --- a/softperipheral/doc/sQSPI/CHANGELOG.rst +++ b/softperipheral/doc/sQSPI/CHANGELOG.rst @@ -1,49 +1,66 @@ -.. _sqspi_changelog: - -sQSPI changelog -############### - -.. contents:: - :local: - :depth: 2 - -All the notable changes to sQSPI are documented on this page. - -v1.1.0 -****** - -See the list of changes for the current release. - -* Added: - - * Fixes on API communication layer for nRF54L15 devices. - * Fixes for a booting bug and on API communication layer for nRF54H20 devices. - -v1.0.0 -****** - -See the list of changes for the current release. - -.. note:: - This release introduces a change in the API, updating the naming convention from ``nrfx_qspi2`` to ``nrf_sqspi`` prefix, which breaks backward compatibility. - -* Added: - - * The following for nRF54L15 devices: - - * Support for preparing (holding) transfers. - * Higher speed transfers are now supported (>=33 MHz) by using GPIOHSPADCTL. - * Position Independent Code for more flexibility when placing the firmware. - * Initial support to use with displays. - -v0.1.0 -****** - -This is an initial release. - -* Added the following for the nRF54L15 and nRF54H20 devices: - - * TX, RX, and TX/RX :ref:`SPI transfer modes` support. - * Configurable :ref:`clock phase and polarity`. - * :ref:`Delayed read sampling `. - * Support for :ref:`various packet formats `. +.. _sqspi_changelog: + +sQSPI changelog +############### + +.. contents:: + :local: + :depth: 2 + +All the notable changes to sQSPI are documented on this page. +Refer to :ref:`intro_soft_peripherals_platform_support` for supported devices for each version. + +v1.2.0 +****** + +See the list of changes for the current release. + +* Added: + + * Support for the nRF54LM20 device. + * A new virtual register on API communication layer for both nRF54H Series and nRF54L Series devices. + +* Updated: + + * Documentation regarding prepared transfers - they are now discarded upon deactivation. + * Porting guides for the nRF54H Series and nRF54L Series devices. + * Naming convention for the Soft Peripheral, which now uses the device series instead of specific product names. + +v1.1.0 +****** + +See the list of changes for the current release. + +* Added: + + * Fixes on API communication layer for nRF54L15 devices. + * Fixes for a booting bug and on API communication layer for nRF54H20 devices. + +v1.0.0 +****** + +See the list of changes for the current release. + +.. note:: + This release introduces a change in the API, updating the naming convention from ``nrfx_qspi2`` to ``nrf_sqspi`` prefix, which breaks backward compatibility. + +* Added: + + * The following for nRF54L15 devices: + + * Support for preparing (holding) transfers. + * Higher speed transfers are now supported (>=33 MHz) by using GPIOHSPADCTL. + * Position Independent Code for more flexibility when placing the firmware. + * Initial support to use with displays. + +v0.1.0 +****** + +This is an initial release. + +* Added the following for the nRF54L15 and nRF54H20 devices: + + * TX, RX, and TX/RX :ref:`SPI transfer modes` support. + * Configurable :ref:`clock phase and polarity`. + * :ref:`Delayed read sampling `. + * Support for :ref:`various packet formats `. diff --git a/softperipheral/doc/sQSPI/README.rst b/softperipheral/doc/sQSPI/README.rst index a372617997..18bb36b15c 100644 --- a/softperipheral/doc/sQSPI/README.rst +++ b/softperipheral/doc/sQSPI/README.rst @@ -61,8 +61,8 @@ To better understand the capabilities and limitations of sQSPI, see its comparis :caption: Subpages: features.rst - nrf54L15_porting_v1_1_0.rst - nrf54H20_porting_v1_1_0.rst + sqspi_nrf54L_series_porting_v1_2_0.rst + sqspi_nrf54H_series_porting_v1_2_0.rst display.rst timing.rst CHANGELOG.rst diff --git a/softperipheral/doc/sQSPI/features.rst b/softperipheral/doc/sQSPI/features.rst index 0ecc66b837..8ab5fc3b2f 100644 --- a/softperipheral/doc/sQSPI/features.rst +++ b/softperipheral/doc/sQSPI/features.rst @@ -1,13 +1,13 @@ .. _sqspi_features: -Features -######## +sQSPI features +############## .. contents:: :local: :depth: 2 -This page provides an overview of the functionalities and configurations available for soft peripherals for the current state of development. +This page provides an overview of the functionalities and configurations available for the soft peripheral sQSPI for the current state of development. See the following sections for more details. .. _sqspi_features_spi_modes: diff --git a/softperipheral/doc/sQSPI/limitations.rst b/softperipheral/doc/sQSPI/limitations.rst index 75f500362b..beeb0ac0c1 100644 --- a/softperipheral/doc/sQSPI/limitations.rst +++ b/softperipheral/doc/sQSPI/limitations.rst @@ -1,7 +1,7 @@ .. _sqspi_limitations: -Limitations -########### +sQSPI limitations +################# When working with sQSPI, you should be aware of the following limitations. @@ -9,7 +9,7 @@ When working with sQSPI, you should be aware of the following limitations. :local: :depth: 2 -v1.1.0 +v1.2.0 ****** Refer to the following detailed descriptions of current limitations: @@ -20,13 +20,14 @@ Refer to the following detailed descriptions of current limitations: This has no effect on data integrity. * The nrfx API for sQSPI does not support configuring the use of the positive or negative edge of SCLK delayed read sampling. * sQSPI employs the :c:var:`nrf_sqspi_dev_cfg_t.sample_delay_cyc` parameter as an offset to FLPR's base clock counter , not SLCK clock cycles (see the :c:struct:`nrf_sqspi_dev_cfg_t` struct). -* sQSPI :c:var:`nrf_sqspi_dev_cfg_t.sample_delay_cyc` is constrained to either a value of ``0`` if using ``GPIOHSPADCTRL`` for high-speed transfers (see :ref:`nrf54L15_porting_guide_high_speed_transfers`) or a value greater than ``0`` but lower than that of ``FLPR_counter`` if a high-speed transfer is not needed (see :ref:`sqspi_timing`). +* sQSPI :c:var:`nrf_sqspi_dev_cfg_t.sample_delay_cyc` is constrained to either a value of ``0`` if using ``GPIOHSPADCTRL`` for high-speed transfers (see :ref:`nrf54L_series_porting_guide_high_speed_transfers`) or a value greater than ``0`` but lower than that of ``FLPR_counter`` if a high-speed transfer is not needed (see :ref:`sqspi_timing`). * Implementation of sQSPI quad or dual lane for command transmission (for example, ``2_2_2`` and ``4_4_4`` modes) is implemented but has not been tested. * sQSPI does not support a configurable pin for the CSN line; only **PIN 5** is supported (see :c:var:`nrf_sqspi_dev_cfg_t.csn_pin`). * :c:var:`nrf_sqspi_xfer_t.p_data` needs to be a pointer with a 32-bit aligned address. * sQSPI high-speed reading cannot happen directly when changing from SPI mode 0 to 3. Either do a high-speed write or a slow read (5.8 MHz) in between. * :c:var:`nrf_sqspi_xfer_t.addr_length` must be greater than :c:var:`nrf_sqspi_dev_cfg_t.mspi_lines`. +* Any prepared transfer with :c:func:`nrf_sqspi_xfer_prepare` will be discarded when using :c:func:`nrf_sqspi_deactivate`. * sQSPI will present undefined behavior in the following cases: diff --git a/softperipheral/doc/sQSPI/nrf54H20_porting_v1_1_0.rst b/softperipheral/doc/sQSPI/nrf54H20_porting_v1_1_0.rst deleted file mode 100644 index d2b5584f2b..0000000000 --- a/softperipheral/doc/sQSPI/nrf54H20_porting_v1_1_0.rst +++ /dev/null @@ -1,258 +0,0 @@ -.. _nrf54H20_porting_guide: - -nRF54H20 porting guide -###################### - -.. contents:: - :local: - :depth: 2 - -This page provides a comprehensive overview of the code structure, file hierarchy, and essential configurations and requirements needed to successfully port and implement an sQSPI application on the nRF54H20 device. - -.. _nrf54h20_porting_guide_code: - -sQSPI application code -********************** - -This structure shows the relevant files and directories in the `sdk-nrfxlib`_ repository: - -.. code-block:: - - nrfxlib/ - ├──... - └── softperipheral/ - ├── include - │ ├── softperipheral_meta.h - │ └── softperipheral_regif.h - ├── ... - └── sQSPI - ├── include - │ ├── hal - │ │ └── nrf_qspi2.h - │ ├── nrf54h20 - │ │ ├── sqspi_firmware.h - │ │ ├── sqspi_firmware_v1.1.0.h - │ │ └── ... - │ ├── nrf_config_sqspi.h - │ ├── nrf_sp_qspi.h - │ ├── nrf_sqspi.h - └── src - └── nrf_sqspi.c - -.. note:: - The main interface for sQSPI is the :file:`nrf_sqspi.h` file. - -Header files -============ - -For an sQSPI application to function correctly, it requires specific header files used by the driver code (internal paths) and specific header files for nrfx (external dependencies). -You must include paths to these files in the build environment's list of include paths. -The following list is a detailed breakdown of the necessary paths: - -* Repository internal paths: - - * :file:`softperipheral/include` - Soft peripherals register interface and metadata - * :file:`softperipheral/sQSPI/include` - sQSPI register interface and driver header - * :file:`softperipheral/sQSPI/include/nrf54h20` - The sQSPI firmware for the Fast Lightweight Perpipheral Processor (FLPR) - -* External dependencies: - - * :file:`nrfx` - Includes the main nrfx header file (:file:`nrfx.h`). - * :file:`nrfx/drivers/include` - Includes the nrfx driver header files. - For example, the :file:`nrfx_dppi.h` file. - * Path to the application-specific headers and macros. - For example, the :file:`nrfx_glue.h`, :file:`nrfx_log.h`, or a configuration header file. - See an example configuration for the :file:`nrfx_config.h` file: - - .. code-block:: c - - #ifndef NRFX_CONFIG_H__ - #define NRFX_CONFIG_H__ - - #define nrf_sqspi_irq_handler SP_VPR_IRQHandler - - #define NRF_SQSPI_ENABLED (1) - #define NRF_SQSPI_MAX_NUM_DATA_LINES (4) - #define NRF_SQSPI_SP_FIRMWARE_ADDR 0x2f890200 - //^ This address is user defined, the location for the sQSPI firmware - - #endif // NRFX_CONFIG_H__ - -Compiling source files -====================== - -For an sQSPI application to function properly, you must compile the driver implementation from the source file :file:`nrf_sqspi.c`. - -Application core and FLPR configuration -*************************************** - -You must adjust the settings for the nRF54H20 SoC to run at highest base clock frequency. - -To work with any of the following settings, ensure you have completed the following: - -* You have allocated memory for the data pointers used by the sQSPI driver. - The memory is independent from the one outlined in the :ref:`nrf54H20_porting_guide_ram_configuration` subsection. - It is designated to function as shared memory for communication purposes, rather than containing the sQSPI executable code. - -Security configuration -====================== - -Configure the security settings for the nRF54H20 device based on the operational requirements of your application. - -Secure environment ------------------- - -In a secure configuration, both the application core and the FLPR core of the nRF54H20 device must operate within a secure environment enabled by TrustZone Secure. - -Non-secure environment ----------------------- - -In a non-secure configuration, both the application core and the FLPR core of the nRF54H20 device must operate outside the secure environment (without TrustZone Secure). - -GPIO configuration -****************** - -The provided table details the configuration for each GPIO pin used in the sQSPI application. -The following options are available, assuming that the FLPR core has access to these ports and pins: - -.. tabs:: - - .. tab:: **P7** GPIO pins - - .. list-table:: - :widths: 10 10 20 20 20 - :header-rows: 1 - - * - GPIO pin - - sQSPI role - - Direction config - - Input config - - Pin pull config - * - **P7.0** - - SCK - - Output - - Disconnected - - No pull - * - **P7.1** - - IO0 - - Output - - Connected - - Pull-up - * - **P7.2** - - IO1 - - Output - - Connected - - Pull-up - * - **P7.3** - - IO2 - - Output - - Connected - - Pull-up - * - **P7.4** - - IO3 - - Output - - Connected - - Pull-up - * - **P7.5** - - CSN - - Output - - Disconnected - - No pull - - .. tab:: **P9** GPIO pins - - .. list-table:: - :widths: 10 10 20 20 20 - :header-rows: 1 - - * - GPIO pin - - sQSPI role - - Direction config - - Input config - - Pin pull config - * - **P9.0** - - SCK - - Output - - Disconnected - - No pull - * - **P9.1** - - IO0 - - Output - - Connected - - Pull-up - * - **P9.2** - - IO1 - - Output - - Connected - - Pull-up - * - **P9.3** - - IO2 - - Output - - Connected - - Pull-up - * - **P9.4** - - IO3 - - Output - - Connected - - Pull-up - * - **P9.5** - - CSN - - Output - - Disconnected - - No pull - -.. note:: - sQSPI driver provides a default GPIO configuration and multiplexing. - You can apply this setup by setting :c:var:`nrf_sqspi_cfg_t.skip_gpio_cfg` and :c:var:`nrf_sqspi_cfg_t.skip_pmux_cfg` to ``false``. - -Configuring pins -================ - -In some cases you might have to modify the sQSPI driver configuration. -For example, when changing pin drive strength to guarantee signal integrity for a new PCB design. -You must address these cases on the sQSPI application code: - -* If you set the :c:var:`nrf_sqspi_cfg_t.skip_gpio_cfg` variable to ``true``, the GPIO configuration is not managed by the sQSPI driver and it must be manually handled by the application. - This is a requirement for the nRF54H20 device. -* If you set the :c:var:`nrf_sqspi_cfg_t.skip_pmux_cfg` variable to ``true``, the GPIO multiplexing is not managed by the sQSPI driver and it must be manually handled by the application. - This is a requirement for the nRF54H20 device. - -GPIO multiplexing must be handled by setting the correct ``CTRLSEL`` value in UICR. - -Additionally, the sQSPI application requires FastPad bias configuration to run at high frequency on SCLK. - -.. _nrf54H20_porting_guide_ram_configuration: - -RAM configuration -***************** - -The sQSPI Soft Peripheral operates from RAM. - -.. note:: - Starting from sQSPI 1.0.0, Position Independent Code (PIC) is supported. - This allows an application to determine where to load the Soft Peripheral firmware. - The start address default value is defined in the :file:`nrf_config_sqspi.h` file but you can override it, for example, in :file:`nrfx_config.h`. - Start address has been verified to work as described in the provided example configuration for :file:`nrfx_config.h` and is ready for production, while other locations should be considered experimental. - -Your build environment must reserve the required RAM and ensure that it is readable and writable by both the application core and the FLPR core. -This table details the memory region, it should be non-cacheable: - -.. list-table:: RAM Configuration Table - :widths: auto - :header-rows: 1 - - * - Component - - Address offset - - Size - * - sQSPI firmware - - `NRF_SQSPI_SP_FIRMWARE_ADDR` - - 0x3740 - * - sQSPI RAM - - `NRF_SQSPI_SP_FIRMWARE_ADDR` + 0x3740 - - 0x600 - * - Context saving - - 0x2f890000 - - 0x200 (but the entire block should be retained) - -The build environment described in the :ref:`nrf54h20_porting_guide_code` section must comply with these requirements. -This includes proper settings in linker scripts, device tree specifications (DTS), and resource allocation. diff --git a/softperipheral/doc/sQSPI/sqspi_nrf54H_series_porting_v1_2_0.rst b/softperipheral/doc/sQSPI/sqspi_nrf54H_series_porting_v1_2_0.rst new file mode 100644 index 0000000000..9c6d7d1f27 --- /dev/null +++ b/softperipheral/doc/sQSPI/sqspi_nrf54H_series_porting_v1_2_0.rst @@ -0,0 +1,364 @@ +.. _sqspi_nrf54H_series_porting_guide: + +sQSPI nRF54H Series porting guide +################################# + +.. contents:: + :local: + :depth: 2 + +This page provides a comprehensive overview of the code structure, file hierarchy, and essential configurations and requirements needed to successfully port and implement an sQSPI application on an nRF54H Series device. + +.. _nrf54h_series_porting_guide_code: + +sQSPI application code +********************** + +This structure shows the relevant files and directories in the `sdk-nrfxlib`_ repository: + +.. code-block:: + + nrfxlib/ + ├──... + └── softperipheral/ + ├── include + │ ├── softperipheral_meta.h + │ └── softperipheral_regif.h + ├── ... + └── sQSPI + ├── include + │ ├── hal + │ │ └── nrf_qspi2.h + │ ├── nrf54h + │ │ ├── sqspi_firmware.h + │ │ ├── sqspi_firmware_v1.2.0.h + │ │ └── ... + │ ├── nrf_config_sqspi.h + │ ├── nrf_sp_qspi.h + │ ├── nrf_sqspi.h + └── src + └── nrf_sqspi.c + +.. note:: + The main interface for sQSPI is the :file:`nrf_sqspi.h` file. + +Header files +============ + +For an sQSPI application to function correctly, it requires specific header files used by the driver code. +You must include paths to these files in the build environment's list of include paths. +The following list is a detailed breakdown of the necessary paths: + +* Repository internal paths: + + * :file:`softperipheral/include` - Soft peripherals register interface and metadata + * :file:`softperipheral/sQSPI/include` - sQSPI register interface, driver header and the configuration header :file:`nrf_config_sqspi.h` + * :file:`softperipheral/sQSPI/include/nrf54h` - The sQSPI firmware for the Fast Lightweight Perpipheral Processor (FLPR) + +To override the configuration enums in :file:`nrf_config_sqspi.h`, you can use the ``zephyr_compile_definitions`` macro in your application: + +.. code-block:: c + + // Example call for enabling the sQSPI + zephyr_compile_definitions("NRF_SQSPI_ENABLED=1") + + +Compiling source files +====================== + +For an sQSPI application to function properly, you must compile the driver implementation from the source file :file:`nrf_sqspi.c`. + +Application core and FLPR configuration +*************************************** + +You must adjust the settings for the nRF54H Series SoC to run at highest base clock frequency. + +To work with any of the following settings, ensure you have allocated memory for the data pointers used by the sQSPI driver. +The memory is independent from the one outlined in the :ref:`nrf54H_series_porting_guide_ram_configuration` subsection. +It is designated to function as shared memory for communication purposes, rather than containing the sQSPI executable code. + +Security configuration +====================== + +Configure the security settings for the nRF54H Series device based on the operational requirements of your application. + +Secure environment +------------------ + +In a secure configuration, both the application core and the FLPR core of the nRF54H Series device must operate within a secure environment enabled by TrustZone Secure. + +Non-secure environment +---------------------- + +In a non-secure configuration, both the application core and the FLPR core of the nRF54H Series device must operate outside the secure environment (without TrustZone Secure). + +.. _sqspi_nrf54h_series_porting_guide_gpio_config: + +GPIO configuration +****************** + +The provided table details the configuration for each GPIO pin used in the sQSPI application. +The following options are available, assuming that the FLPR core has access to these ports and pins: + +.. tabs:: + + .. tab:: **P7** GPIO pins + + .. list-table:: + :widths: 10 10 20 20 20 + :header-rows: 1 + + * - GPIO pin + - sQSPI role + - Direction config + - Input config + - Pin pull config + * - **P7.0** + - SCK + - Output + - Disconnected + - No pull + * - **P7.1** + - IO0 + - Output + - Connected + - Pull-up + * - **P7.2** + - IO1 + - Output + - Connected + - Pull-up + * - **P7.3** + - IO2 + - Output + - Connected + - Pull-up + * - **P7.4** + - IO3 + - Output + - Connected + - Pull-up + * - **P7.5** + - CSN + - Output + - Disconnected + - No pull + + .. tab:: **P9** GPIO pins + + .. list-table:: + :widths: 10 10 20 20 20 + :header-rows: 1 + + * - GPIO pin + - sQSPI role + - Direction config + - Input config + - Pin pull config + * - **P9.0** + - SCK + - Output + - Disconnected + - No pull + * - **P9.1** + - IO0 + - Output + - Connected + - Pull-up + * - **P9.2** + - IO1 + - Output + - Connected + - Pull-up + * - **P9.3** + - IO2 + - Output + - Connected + - Pull-up + * - **P9.4** + - IO3 + - Output + - Connected + - Pull-up + * - **P9.5** + - CSN + - Output + - Disconnected + - No pull + +.. note:: + sQSPI driver provides a default GPIO configuration and multiplexing. + You can apply this setup by setting :c:var:`nrf_sqspi_cfg_t.skip_gpio_cfg` and :c:var:`nrf_sqspi_cfg_t.skip_pmux_cfg` to ``false``. + +Configuring pins +================ + +In some cases, you might have to modify the sQSPI driver configuration. +For example, you might need to change the pin drive strength to guarantee signal integrity for a new PCB design. + +.. note:: + When using a custom PCB with the nRF54H20 device you might need to match the output impedance on the port you are using. + Refer to the :ref:`nrf:ug_nrf54h20_custom_pcb` page for details. + +You must address these cases on the sQSPI application code: + +* If you set the :c:var:`nrf_sqspi_cfg_t.skip_gpio_cfg` variable to ``true``, the GPIO configuration is not managed by the sQSPI driver and it must be manually handled by the application. + This is a requirement for the nRF54H20 device. +* If you set the :c:var:`nrf_sqspi_cfg_t.skip_pmux_cfg` variable to ``true``, the GPIO multiplexing is not managed by the sQSPI driver and it must be manually handled by the application. + This is a requirement for the nRF54H20 device. + +GPIO multiplexing must be handled by setting the correct ``CTRLSEL`` value in UICR. + +Additionally, the sQSPI application requires FastPad bias configuration to run at high frequency on SCLK. + +Any conflicting peripherals and existing memory partitions on the same port as sQSPI must be disabled in the devicetree overlay, depending on your requirements. +See an example code snippet of a devicetree overlay that grants FLPR access to the **P7** port. + +The first part of the snippet, the ``pinctrl`` block, configures the relevant GPIOs as described in the :ref:`sqspi_nrf54h_series_porting_guide_gpio_config` section. + +Next, the ``cpuflpr_vpr`` block and the subsequent block handle the allocation of the VPR memory region and the RAM used by sQSPI. + +.. code-block:: dts + + &pinctrl { + sqspi_default: sqspi_default { + group1 { + psels = ; + nordic,drive-mode = ; + bias-pull-down; + }; + group2 { + psels = , + , + , + , + , + ; + nordic,drive-mode = ; + bias-pull-up; + }; + }; + + sqspi_sleep: sqspi_sleep { + group1 { + low-power-enable; + psels = , + , + , + , + , + , + ; + }; + }; + }; + + &cpuflpr_vpr { + pinctrl-0 = <&sqspi_default>; + pinctrl-1 = <&sqspi_sleep>; + pinctrl-names = "default"; + interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>; + status = "okay"; + /delete-property/ execution-memory; + }; + + /delete-node/ &cpuflpr_code_data; + /delete-node/ &cpuapp_cpuflpr_ipc_shm; + /delete-node/ &cpuflpr_cpuapp_ipc_shm; + /delete-node/ &cpuapp_cpuflpr_ipc; + + / { + reserved-memory { + softperiph_ram: memory@2f890000 { + reg = <0x2f890000 0x4000>; + ranges = <0 0x2f890000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + + dut: sqspi: sqspi@3d40 { + compatible = "nordic,nrf-sqspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x3d40 0x200>; + zephyr,pm-device-runtime-auto; + memory-regions = <&sqspi_buffers>; + }; + }; + + sqspi_buffers: memory@2f894000 { + compatible = "zephyr,memory-region"; + reg = <0x2f894000 0x4000>; + #memory-region-cells = <0>; + zephyr,memory-region = "SQSPI_BUFFERS"; + zephyr,memory-attr = ; + }; + }; + }; + + +You will need the following lines in your application to apply the pin configuration from your sQSPI board DTS overlay, as well as to initialize the Soft Peripheral: + +.. code-block:: c + + #define VPR_NODE DT_NODELABEL(cpuflpr_vpr) + #define SP_REGIF_BASE DT_REG_ADDR(DT_NODELABEL(sqspi)) + + // The following lines in your setup function will apply the FLPR pins to PINCTRL + PINCTRL_DT_DEFINE(VPR_NODE); + int rc = pinctrl_apply_state(PINCTRL_DT_DEV_CONFIG_GET(VPR_NODE), PINCTRL_STATE_DEFAULT); + zassert_true(rc >= 0, "Pins not configured properly! Returned with code: 0x&X\t\n", rc); + + // The following line initializes sQSPI + static nrf_sqpsi_t m_sqspi = {.p_reg = (void *)SP_REGIF_BASE, .drv_inst_idx = 0}; + +.. _nrf54h20_porting_guide_ram_configuration: +.. _nrf54H_series_porting_guide_ram_configuration: + +RAM configuration +***************** + +The sQSPI Soft Peripheral operates from RAM. + +.. note:: + Starting from sQSPI 1.0.0, sQSPI supports Position Independent Code (PIC), which allows an application to determine where to load the Soft Peripheral firmware. + +Your build environment must reserve the required RAM and ensure that it is readable and writable by both the application core and the FLPR core. +The following table details the memory region, which should be non-cacheable: + +.. list-table:: RAM Configuration Table + :widths: auto + :header-rows: 1 + + * - Component + - Address offset + - Size + * - sQSPI firmware + - ``SP_FIRMWARE_ADDR`` + - 0x3740 + * - sQSPI execution RAM + - ``SP_FIRMWARE_ADDR`` + 0x3740 + - 0x400 + * - sQSPI virtual register interface + - ``SP_FIRMWARE_ADDR`` + 0x3B40 + - 0x200 + * - Context saving + - 0x2f890000 + - 0x200 (but the entire block should be retained) + +The build environment described in the :ref:`nrf54h_series_porting_guide_code` section, you must comply with these requirements. +This includes proper settings in linker scripts, device tree specifications (DTS), and resource allocation. + +Ensure that ``SP_FIRMWARE_ADDR`` is set so that it does not overlap with the context saving address. +For nRF54H Series devices, the firmware has been tested using values that follow the context saving address. +This means, that ``SP_FIRMWARE_ADDR`` should be set higher than the context saving address plus the context saving offset. +The value ``0x2f890200`` for ``SP_FIRMWARE_ADDR`` has been tested and is considered production-ready. + +IRQ connection +************** + +For sQSPI to communicate with the application core, the sQSPI IRQ handler must be registered. +The following code line registers the IRQ handler to FLPR: + +.. code-block:: c + + IRQ_CONNECT(DT_IRQN(VPR_NODE), DT_IRQ(VPR_NODE, priority), nrfx_isr, nrf_sqspi_irq_handler, 0); diff --git a/softperipheral/doc/sQSPI/nrf54L15_porting_v1_1_0.rst b/softperipheral/doc/sQSPI/sqspi_nrf54L_series_porting_v1_2_0.rst similarity index 71% rename from softperipheral/doc/sQSPI/nrf54L15_porting_v1_1_0.rst rename to softperipheral/doc/sQSPI/sqspi_nrf54L_series_porting_v1_2_0.rst index adb5b133af..df177ad9dd 100644 --- a/softperipheral/doc/sQSPI/nrf54L15_porting_v1_1_0.rst +++ b/softperipheral/doc/sQSPI/sqspi_nrf54L_series_porting_v1_2_0.rst @@ -1,15 +1,15 @@ -.. _nrf54L15_porting_guide: +.. _sqspi_nrf54L_series_porting_guide: -nRF54L15 porting guide -###################### +sQSPI nRF54L Series porting guide +################################# .. contents:: :local: :depth: 2 -This page provides a comprehensive overview of the code structure, file hierarchy, and essential configurations and requirements needed to successfully port and implement an sQSPI application on the nRF54L15 device. +This page provides a comprehensive overview of the code structure, file hierarchy, and essential configurations and requirements needed to successfully port and implement an sQSPI application on nRF54L Series devices. -.. _nrf54l15_porting_guide_code: +.. _nrf54l_series_porting_guide_code: sQSPI application code ********************** @@ -29,9 +29,9 @@ This structure shows the relevant files and directories in the `sdk-nrfxlib`_ re ├── include │ ├── hal │ │ └── nrf_qspi2.h - │ ├── nrf54l15 + │ ├── nrf54l │ │ ├── sqspi_firmware.h - │ │ └── sqspi_firmware_v1.1.0.h + │ │ └── sqspi_firmware_v1.2.0.h │ │ └── ... │ ├── nrf_config_sqspi.h │ ├── nrf_sp_qspi.h @@ -44,7 +44,7 @@ This structure shows the relevant files and directories in the `sdk-nrfxlib`_ re Header files ============ -For an sQSPI application to function correctly, it requires specific header files used by the driver code (internal paths) and specific header files for nrfx (external dependencies). +sQSPI application requires specific header files used by the driver code (internal paths) and specific header files for nrfx (external dependencies). You must include paths to these files in the build environment's list of include paths. The following list is a detailed breakdown of the necessary paths: @@ -52,7 +52,7 @@ The following list is a detailed breakdown of the necessary paths: * :file:`softperipheral/include` - Soft peripherals register interface and metadata * :file:`softperipheral/sQSPI/include` - sQSPI register interface and driver header - * :file:`softperipheral/sQSPI/include/nrf54l15` - The sQSPI firmware for the Fast Lightweight Perpipheral Processor (FLPR) + * :file:`softperipheral/sQSPI/include/nrf54l` - The sQSPI firmware for the Fast Lightweight Perpipheral Processor (FLPR) * External dependencies: @@ -63,21 +63,20 @@ The following list is a detailed breakdown of the necessary paths: For example, the :file:`nrfx_glue.h`, :file:`nrfx_log.h`, or a configuration header file. See an example configuration for the :file:`nrfx_config.h` file: - .. code-block:: c +.. code-block:: c + + #ifndef NRFX_CONFIG_H__ + #define NRFX_CONFIG_H__ - #ifndef NRFX_CONFIG_H__ - #define NRFX_CONFIG_H__ + #include "softperipheral_regif.h" // To Resolve correct VPR IRQn for the SoC. + #define nrf_sqspi_irq_handler SP_VPR_IRQHandler - #include "softperipheral_regif.h" // To Resolve correct VPR IRQn for the SoC. - #define nrf_sqspi_irq_handler SP_VPR_IRQHandler + #define NRF_SQSPI_ENABLED (1) + #define NRF_SQSPI_MAX_NUM_DATA_LINES (4) - #define NRF_SQSPI_ENABLED (1) - #define NRF_SQSPI_MAX_NUM_DATA_LINES (4) - #define NRF_SQSPI_SP_FIRMWARE_ADDR 0x2003c000 - //^ This address is user defined, the location for the sQSPI firmware + #endif // NRFX_CONFIG_H__ - #endif // NRFX_CONFIG_H__ Compiling source files ====================== @@ -87,12 +86,11 @@ For an sQSPI application to function properly, you must compile the driver imple Application core and FLPR configuration *************************************** -You must adjust the settings for the nRF54L15 SoC to run at highest base clock frequency. - +You must adjust the settings for the nRF54L Series SoC to run at highest base clock frequency. To work with any of the following settings, ensure you have completed the following: * You have allocated memory for the data pointers used by the sQSPI driver. - The memory is independent from the one outlined in the :ref:`nrf54L15_porting_guide_ram_configuration` subsection. + The memory is independent from the one outlined in the :ref:`nrf54L_series_porting_guide_ram_configuration` subsection. It is designated to function as shared memory for communication purposes, rather than containing the sQSPI executable code. * You have enabled the FLPR access to the ``MEMCONF`` peripheral. @@ -101,12 +99,12 @@ To work with any of the following settings, ensure you have completed the follow Security configuration ====================== -Configure the security settings for the nRF54L15 device based on the operational requirements of your application. +Configure the security settings for the nRF54L Series device based on the operational requirements of your application. Secure environment ------------------ -In a secure configuration, both the application core and the FLPR core of the nRF54L15 device must operate within a secure environment enabled by TrustZone Secure. +In a secure configuration, both the application core and the FLPR core of the nRF54L Series device must operate within a secure environment enabled by TrustZone Secure. The following code snippet shows how the application code can configure permissions for the FLPR instance: @@ -118,7 +116,7 @@ The following code snippet shows how the application code can configure permissi Non-secure environment ---------------------- -In a non-secure configuration, both the application core and the FLPR core of the nRF54L15 device must operate outside the secure environment (without TrustZone Secure). +In a non-secure configuration, both the application core and the FLPR core of the nRF54L Series device must operate outside the secure environment (without TrustZone Secure). GPIO configuration ****************** @@ -228,25 +226,27 @@ The following code snippet shows how the application code can allocate the requi } } -.. _nrf54L15_porting_guide_high_speed_transfers: +.. _nrf54L_series_porting_guide_high_speed_transfers: High speed transfers ==================== -.. warning:: - High speed transfers (above 32 MHz) on the NRF54L15 DK are only supported starting from sQSPI v1.0.0. +.. note:: + High speed transfers (above 32 MHz) on the nRF54L15 DK are only supported starting from sQSPI v1.0.0. -A high speed transfer sQSPI application requires both extra high drive strength and access to the peripheral ``GPIOHSPADCTRL`` (GPIO High Speed Pad Control). -The following settings must be changed for ``GPIOHSPADCTRL.BIAS`` and ``GPIOHSPADCTRL.CTRL``: +To use high speed transfer in an sQSPI application, you must set extra high drive strength and provide access to the ``GPIOHSPADCTRL`` (GPIO High Speed Pad Control) peripheral. +You must apply the following settings to ``GPIOHSPADCTRL.BIAS`` and ``GPIOHSPADCTRL.CTRL``: -* Bias control: Highest slew setting for the high speed pad and activating replica clock. +* Bias control - Set the highest slew rate for the high speed pad and enable the replica clock. +* Input sampling and buffering control -* Input sampling and buffering control: - * For a high speed **read**, you must enable sampling clock, configure its phase (matching desired SPI mode), enable delayed data sampling and configuring the delay. - * For a high speed **write**, you must disable sampling clock and disable delayed data sampling + * For a high speed read - Enable the sampling clock, set its phase to match the required SPI mode, enable delayed data sampling, and configure the appropriate delay. + * For a high speed write - Disable the sampling clock and turn off delayed data sampling. .. note:: - High speed read transfers need to reset the pad configuration, this applies to **P2** as a whole, which is important if other pins are used besides the ones allocated for sQSPI. In this context reset means setting standard drive strength, then setting extra high drive strength again. + High speed read transfers require you to reset the pad configuration for **P2** as a whole. + This is important if other pins on **P2** are in use in addition to those assigned to sQSPI. + In this context, resetting means first setting the drive strength to standard, and then reapplying extra high drive strength again. The following code snippet shows how the application code can enable and disable delayed sampling: @@ -413,26 +413,27 @@ The following code snippet shows how the application code can enable and disable set_serialPadE0E1(qspi_dev_config); } -.. warning:: - High speed transfers are closely tied to API the parameter :c:var:`nrf_sqspi_dev_cfg_t.sample_delay_cyc`, which needs to be set to ``0`` (see :ref:`sqspi_limitations`). +.. note:: + High speed transfers are closely linked to the API parameter :c:var:`nrf_sqspi_dev_cfg_t.sample_delay_cyc`, which must be set to ``0`` (see :ref:`sqspi_limitations`). Memory retention configuration ****************************** The sQSPI soft peripheral requires RAM retention in order to go into the lowest power consumption mode, which can be called through the :c:func:`nrf_sqspi_deactivate` function. -Assuming there is an access to the peripheral `MEMCONF`, the following code snippet illustrates how to enable FLPR RAM retention, followed by deactivation and reactivation, and finally how to disable RAM retention: +Assuming there is an access to the peripheral ``MEMCONF``, the following code snippet illustrates how to enable FLPR RAM retention, followed by deactivation and reactivation, and finally how to disable RAM retention: - .. code-block:: c +.. code-block:: c - //Deactivate sequence - nrf_memconf_ramblock_ret_enable_set(NRF_MEMCONF, 1, MEMCONF_POWER_RET_MEM0_Pos, true); - nrf_sqspi_deactivate(&m_qspi); - //activate sequence - nrf_qspi_activate(&m_qspi); - nrf_memconf_ramblock_ret_enable_set(NRF_MEMCONF, 1, MEMCONF_POWER_RET_MEM0_Pos, false); + // Deactivate sequence + nrf_memconf_ramblock_ret_enable_set(NRF_MEMCONF, 1, MEMCONF_POWER_RET_MEM0_Pos, true); + nrf_sqspi_deactivate(&m_qspi); + // Activate sequence + nrf_qspi_activate(&m_qspi); + nrf_memconf_ramblock_ret_enable_set(NRF_MEMCONF, 1, MEMCONF_POWER_RET_MEM0_Pos, false); -.. _nrf54L15_porting_guide_ram_configuration: +.. _nrf54l15_porting_guide_ram_configuration: +.. _nrf54L_series_porting_guide_ram_configuration: RAM configuration ***************** @@ -442,28 +443,81 @@ The sQSPI Soft Peripheral operates from RAM. .. note:: Starting from sQSPI 1.0.0, Position Independent Code (PIC) is supported. This allows an application to determine where to load the Soft Peripheral firmware. - The start address default value is defined in the :file:`nrf_config_sqspi.h` file but you can override it, for example, in :file:`nrfx_config.h`. - Start address has been verified to work as described in the provided example configuration for :file:`nrfx_config.h` and is ready for production, while other locations should be considered experimental. Your build environment must reserve the required RAM and ensure that it is readable and writable by both the application core and the FLPR core. -This table details the memory region: +The following table details the memory regions required for your nRF54L Series device: + +.. tabs:: + + .. tab:: **nRF54L15** + + .. list-table:: nRF54L15 RAM Configuration Table + :widths: auto + :header-rows: 1 + + * - Component + - Address offset + - Size + * - sQSPI firmware + - ``SP_FIRMWARE_ADDR`` + - 0x3740 + * - sQSPI execution RAM + - ``SP_FIRMWARE_ADDR`` + 0x3740 + - 0x400 + * - sQSPI virtual register interface + - ``SP_FIRMWARE_ADDR`` + 0x3B40 + - 0x200 + * - Context saving + - 0x2003FE00 + - 0x200 (but the entire block should be retained) + + .. tab:: **nRF54LM20** + + .. list-table:: nRF54LM20 RAM Configuration Table + :widths: auto + :header-rows: 1 + + * - Component + - Address offset + - Size + * - sQSPI firmware + - ``SP_FIRMWARE_ADDR`` + - 0x3740 + * - sQSPI execution RAM + - ``SP_FIRMWARE_ADDR`` + 0x3740 + - 0x400 + * - sQSPI virtual register interface + - ``SP_FIRMWARE_ADDR`` + 0x3B40 + - 0x200 + * - Context saving + - 0x2007FD40 + - 0x200 (but the entire block should be retained) + +The build environment described in the :ref:`nrf54l_series_porting_guide_code` section must comply with these requirements. +This includes proper settings in linker scripts, device tree specifications (DTS), and resource allocation. -.. list-table:: RAM Configuration Table - :widths: auto +To initialize the sQSPI struct on an nRF54L Series device, use the following lines: + + .. code-block:: c + + #define SP_REGIF_BASE (SP_FIRMWARE_ADDR + 0x3B40) + + // Initialize sQSPI with the virtual register interface placed at SP_REGIF_BASE + static nrf_sqspi_t m_sqspi = {.p_reg = (void *)SP_REGIF_BASE, .drv_inst_idx = 0}; + +Ensure that ``SP_FIRMWARE_ADDR`` is set so that it does not overlap with the context saving address. +For nRF54L Series devices, the firmware is placed before the context saving address. +This means, that ``SP_FIRMWARE_ADDR`` plus the component sizes listed in the table must be of a lower value than the context saving address. + +The values in the table below have been tested and are considered production-ready for ``SP_FIRMWARE_ADDR``: + +.. list-table:: sQSPI firmware address values + :widths: 20 20 :header-rows: 1 - * - Component - - Address offset - - Size - * - sQSPI firmware - - `NRF_SQSPI_SP_FIRMWARE_ADDR` - - 0x3740 - * - sQSPI RAM - - `NRF_SQSPI_SP_FIRMWARE_ADDR` + 0x3740 - - 0x600 - * - Context saving - - 0x2003FE00 - - 0x200 (but the entire block should be retained) - -The build environment described in the :ref:`nrf54l15_porting_guide_code` section must comply with these requirements. -This includes proper settings in linker scripts, device tree specifications (DTS), and resource allocation. + * - Device + - `SP_FIRMWARE_ADDR` + * - nRF54L15 + - 0x2003C000 + * - nRF54LM20 + - 0x2007C000 diff --git a/softperipheral/doc/sQSPI/timing.rst b/softperipheral/doc/sQSPI/timing.rst index 439786b155..5b33556ed9 100644 --- a/softperipheral/doc/sQSPI/timing.rst +++ b/softperipheral/doc/sQSPI/timing.rst @@ -10,11 +10,20 @@ The translation has the following constraints (assuming the SoC is running at hi .. tab:: **nRF54L15** .. math:: - clkdiv=\frac{128000000}{1000 * nrf\_sqspi\_dev\_cfg\_t.sck\_freq\_khz} + max\_device\_freq\_hz=128000000 + + .. tab:: **nRF54LM20** + .. math:: + max\_device\_freq\_hz=128000000 .. tab:: **nRF54H20** .. math:: - clkdiv=\frac{320000000}{1000 * nrf\_sqspi\_dev\_cfg\_t.sck\_freq\_khz} + max\_device\_freq\_hz=320000000 + +The maximum core frequency of the device translates to a clock divider used in FLPR's internal counters: + +.. math:: + clkdiv=\frac{max\_device\_freq\_hz}{1000 * nrf\_sqspi\_dev\_cfg\_t.sck\_freq\_khz} .. math:: FLPR\_counter= @@ -34,7 +43,7 @@ When working with sQSPI, you should be aware of the associated timing parameters .. tabs:: - .. tab:: **nRF54L15** + .. tab:: **nRF54L15, without GPIOHSPADCTRL** .. list-table:: :widths: 20 20 10 10 10 10 @@ -71,6 +80,43 @@ When working with sQSPI, you should be aware of the associated timing parameters - 11.7 - ns + .. tab:: **nRF54L15, with GPIOHSPADCTRL** + + .. list-table:: + :widths: 20 20 10 10 10 10 + :header-rows: 1 + + * - Symbol + - Description + - Min + - Typ + - Max + - Units + * - F\ :sub:`sQSPI,SCLK` + - SCLK frequency + - + - + - 64 + - MHz + * - DC\ :sub:`sQSPI,SCLK` + - SCLK duty cycle + - + - 50 + - + - % + * - t\ :sub:`DOV` + - Data out valid + - + - + - 2.2 + - ns + * - t\ :sub:`SDI` + - Data in setup time + - + - + - 4.865 + - ns + .. tab:: **nRF54H20** .. list-table:: @@ -108,6 +154,11 @@ When working with sQSPI, you should be aware of the associated timing parameters - - ns +.. note:: + Achieving 64MHz on nRF54L15 is possible when the slave access time plus the flight time of signal propagation + is less than :math:`\frac{1}{64MHz} - t_{SDI}`. For example, to achieve 64MHz on nRF54L15 using GPIOHSPADCTRL gives a + maximum slave access time of :math:`15.625ns - 4.865ns = 10.76ns`. + The following timing diagrams provide a visual reference to show how the parameters t\ :sub:`DOV` and t\ :sub:`SDI` relate to SCLK. SDIO represents the data lines. diff --git a/softperipheral/include/softperipheral_regif.h b/softperipheral/include/softperipheral_regif.h index 3e55c1969b..8255e5980b 100644 --- a/softperipheral/include/softperipheral_regif.h +++ b/softperipheral/include/softperipheral_regif.h @@ -61,9 +61,9 @@ #if 1 #define __XSBx(R, P, T) \ do { \ - nrf_qspi2_core_dr_x(R, m_task_count, 20); \ + sp_handshake_set(R, m_task_count, 0); \ nrf_egu_task_trigger(P, (nrf_egu_task_t)offsetof(NRF_EGU_Type, TASKS_TRIGGER[T])); \ - while (nrf_qspi2_core_dr_x_get(R, 20) != nrf_qspi2_core_dr_x_get(R, 21)) { \ + while (sp_handshake_get(R, 0) != sp_handshake_get(R, 1)) { \ __NOP(); \ __NOP(); \ __NOP(); \ @@ -87,9 +87,9 @@ #if 1 #define __XSBx(R, P, T) \ do { \ - nrf_qspi2_core_dr_x(R, m_task_count, 20); \ + sp_handshake_set(R, m_task_count, 0); \ nrf_vpr_task_trigger(P, (nrf_vpr_task_t)offsetof(NRF_VPR_Type, TASKS_TRIGGER[T])); \ - while (nrf_qspi2_core_dr_x_get(R, 20) != nrf_qspi2_core_dr_x_get(R, 21)) { \ + while (sp_handshake_get(R, 0) != sp_handshake_get(R, 1)) { \ __NOP(); \ __NOP(); \ __NOP(); \ diff --git a/softperipheral/sEMMC/include/hal/nrf_emmc.h b/softperipheral/sEMMC/include/hal/nrf_emmc.h new file mode 100644 index 0000000000..2e3ef443af --- /dev/null +++ b/softperipheral/sEMMC/include/hal/nrf_emmc.h @@ -0,0 +1,379 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef NRF_EMMC_H__ +#define NRF_EMMC_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOFTPERIPHERAL_EMMC (1) +#if SOFTPERIPHERAL_EMMC +#include +#define NRF_EMMC_Type NRF_SP_EMMC_Type +#else +#define NRF_EMMC_Type NRF_EMMC_Type +#endif + +/** + * @defgroup nrf_emmc_hal EMMC HAL + * @{ + * @brief Hardware access layer for managing the EMMC peripheral. + */ + +/** @brief EMMC tasks. */ +typedef enum +{ + NRF_EMMC_TASK_START = offsetof(NRF_EMMC_Type, TASKS_START), /**< Trigger this task to send a command. */ + NRF_EMMC_TASK_RESET = offsetof(NRF_EMMC_Type, + TASKS_RESET), /**< Trigger this task to reset SEMMC to UNINITIALIZED state. */ +} nrf_emmc_task_t; + +/** @brief EMMC events. */ +typedef enum +{ + NRF_EMMC_EVENT_XFERCOMPLETE = offsetof(NRF_EMMC_Type, EVENTS_XFERCOMPLETE), /**< Command or transfer completed. */ + NRF_EMMC_EVENT_ABORTED = offsetof(NRF_EMMC_Type, EVENTS_ABORTED), /**< Command/transfer aborted or timed out. */ + NRF_EMMC_EVENT_READYTOTRANSFER = offsetof(NRF_EMMC_Type, EVENTS_READYTOTRANSFER), /**< Ready to transfer. */ +} nrf_emmc_event_t; + +/** @brief EMMC interrupt masks. */ +typedef enum +{ + NRF_EMMC_INT_XFERCOMPLETE_MASK = SP_EMMC_INTEN_XFERCOMPLETE_Msk, /**< Interrupt on transfer complete. */ + NRF_EMMC_INT_ABORTED_MASK = SP_EMMC_INTEN_ABORTED_Msk, /**< Interrupt on transfer aborted. */ + NRF_EMMC_INT_READYTOTRANSFER_MASK = SP_EMMC_INTEN_READYTOTRANSFER_Msk, /**< Interrupt on ready to transfer. */ +} nrf_emmc_int_mask_t; + +/** @brief EMMC response types. */ +typedef enum +{ + NRF_EMMC_RESPONSE_NONE = SP_EMMC_COMMAND_CMD_RESPTYPE_NONE, /**< No response. */ + NRF_EMMC_RESPONSE_R1 = SP_EMMC_COMMAND_CMD_RESPTYPE_R1, /**< R1 response. */ + NRF_EMMC_RESPONSE_R1B = SP_EMMC_COMMAND_CMD_RESPTYPE_R1B, /**< R1 response with busy signal. */ + NRF_EMMC_RESPONSE_R2 = SP_EMMC_COMMAND_CMD_RESPTYPE_R2, /**< R2 response. */ + NRF_EMMC_RESPONSE_R3 = SP_EMMC_COMMAND_CMD_RESPTYPE_R3, /**< R3 response. */ + NRF_EMMC_RESPONSE_R4 = SP_EMMC_COMMAND_CMD_RESPTYPE_R4, /**< R4 response. */ + NRF_EMMC_RESPONSE_R5 = SP_EMMC_COMMAND_CMD_RESPTYPE_R5, /**< R5 response. */ +} nrf_emmc_response_type_t; + +/** @brief EMMC response processing types. */ +typedef enum +{ + NRF_EMMC_RESPONSE_PROC_PROCESS = SP_EMMC_COMMAND_CMD_RESPPROC_PROCESS, /**< Process the response. */ + NRF_EMMC_RESPONSE_PROC_IGNORE = SP_EMMC_COMMAND_CMD_RESPPROC_IGNORE, /**< Ignore the response. */ +} nrf_emmc_response_proc_t; + +/** @brief EMMC bus width configurations. */ +typedef enum +{ + NRF_EMMC_BUS_WIDTH_1_LANE = SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_ONELANE, /**< 1-lane data transfer. */ + NRF_EMMC_BUS_WIDTH_4_LANES = SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_FOURLANES, /**< 4-lane data transfer. */ + NRF_EMMC_BUS_WIDTH_8_LANES = SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_EIGHTLANES, /**< 8-lane data transfer. */ +} nrf_emmc_bus_width_t; + +/** @brief EMMC configuration structure. */ +typedef struct +{ + uint32_t clkfreqhz; /**< Clock frequency in Hz. */ + nrf_emmc_bus_width_t bus_width; /**< Bus width configuration. */ + bool ready_to_transfer; /**< Ready to transfer flag. */ + uint32_t read_delay; +} nrf_emmc_config_t; + +/** @brief EMMC command structure. */ +typedef struct +{ + uint16_t idx; /**< Command index. */ + nrf_emmc_response_type_t resp_type; /**< Response type. */ + nrf_emmc_response_proc_t resp_proc; /**< Response processing. */ + uint32_t arg; /**< Command argument. */ + uint32_t resp_addr; /**< Response address. */ +} nrf_emmc_command_t; + +/** @brief EMMC data transfer structure. */ +typedef struct +{ + uint32_t buffer_addr; /**< Buffer address. */ + // uint32_t target_addr; /**< Target address. */ + uint32_t block_size; /**< Block size. */ + uint32_t block_num; /**< Number of blocks. */ +} nrf_emmc_data_t; + +NRF_STATIC_INLINE void nrf_emmc_task_trigger(NRF_EMMC_Type * p_reg, nrf_emmc_task_t task); + +NRF_STATIC_INLINE void nrf_emmc_enable(NRF_EMMC_Type * p_reg); + +NRF_STATIC_INLINE void nrf_emmc_disable(NRF_EMMC_Type * p_reg); + +NRF_STATIC_INLINE bool nrf_emmc_enable_check(NRF_EMMC_Type const * p_reg); + +NRF_STATIC_INLINE void nrf_emmc_event_clear(NRF_EMMC_Type * p_reg, nrf_emmc_event_t event); + +NRF_STATIC_INLINE bool nrf_emmc_event_check(NRF_EMMC_Type const * p_reg, nrf_emmc_event_t event); + +NRF_STATIC_INLINE uint32_t nrf_emmc_event_address_get(NRF_EMMC_Type const * p_reg, + nrf_emmc_event_t event); + +NRF_STATIC_INLINE void nrf_emmc_int_enable(NRF_EMMC_Type * p_reg, uint32_t mask); + +NRF_STATIC_INLINE uint32_t nrf_emmc_int_enable_check(NRF_EMMC_Type const * p_reg, uint32_t mask); + +NRF_STATIC_INLINE void nrf_emmc_int_disable(NRF_EMMC_Type * p_reg, uint32_t mask); + +NRF_STATIC_INLINE void nrf_emmc_config_set(NRF_EMMC_Type * p_reg, + nrf_emmc_config_t const * p_config); + +NRF_STATIC_INLINE void nrf_emmc_config_get(NRF_EMMC_Type const * p_reg, + nrf_emmc_config_t * p_config); + +NRF_STATIC_INLINE void nrf_emmc_command_set(NRF_EMMC_Type * p_reg, + nrf_emmc_command_t const * p_cmd); + +NRF_STATIC_INLINE void nrf_emmc_config_set_ready_to_transfer(NRF_EMMC_Type * p_reg, + nrf_emmc_config_t const * p_config); + +NRF_STATIC_INLINE void nrf_emmc_config_get_ready_to_transfer(NRF_EMMC_Type const * p_reg, + nrf_emmc_config_t * p_config); + +NRF_STATIC_INLINE void nrf_emmc_command_set_response(NRF_EMMC_Type * p_reg, + const uint32_t * response); + +NRF_STATIC_INLINE void nrf_emmc_command_get_response(NRF_EMMC_Type const * p_reg, + uint32_t * response); + +NRF_STATIC_INLINE void nrf_emmc_command_get(NRF_EMMC_Type const * p_reg, + nrf_emmc_command_t * p_cmd); + +NRF_STATIC_INLINE void nrf_emmc_data_set(NRF_EMMC_Type * p_reg, nrf_emmc_data_t const * p_data); + +NRF_STATIC_INLINE void nrf_emmc_data_get(NRF_EMMC_Type const * p_reg, nrf_emmc_data_t * p_data); + +NRF_STATIC_INLINE void nrf_emmc_set_num_blocks(NRF_EMMC_Type * p_reg, + nrf_emmc_data_t const * p_data); + +NRF_STATIC_INLINE void nrf_emmc_get_num_blocks(NRF_EMMC_Type const * p_reg, + nrf_emmc_data_t * p_data); + +NRF_STATIC_INLINE void nrf_emmc_status_set(NRF_EMMC_Type * p_reg, + uint32_t error_mask); + +NRF_STATIC_INLINE uint32_t nrf_emmc_status_get(NRF_EMMC_Type const * p_reg); + +NRF_STATIC_INLINE bool nrf_emmc_status_error_check(uint32_t status); + +NRF_STATIC_INLINE void nrf_emmc_handshake_set(NRF_EMMC_Type * p_reg, uint32_t val, uint8_t idx); + +NRF_STATIC_INLINE uint32_t nrf_emmc_handshake_get(NRF_EMMC_Type const * p_reg, uint8_t idx); + +#ifndef NRF_DECLARE_ONLY + +NRF_STATIC_INLINE void nrf_emmc_task_trigger(NRF_EMMC_Type * p_reg, nrf_emmc_task_t task) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL; +} + +NRF_STATIC_INLINE void nrf_emmc_enable(NRF_EMMC_Type * p_reg) +{ + p_reg->ENABLE = SP_EMMC_ENABLE_ENABLE_Enabled; +} + +NRF_STATIC_INLINE void nrf_emmc_disable(NRF_EMMC_Type * p_reg) +{ + p_reg->ENABLE = SP_EMMC_ENABLE_ENABLE_Disabled; +} + +NRF_STATIC_INLINE bool nrf_emmc_enable_check(NRF_EMMC_Type const * p_reg) +{ + return (bool)(p_reg->ENABLE & SP_EMMC_ENABLE_ENABLE_Msk); +} + +NRF_STATIC_INLINE void nrf_emmc_event_clear(NRF_EMMC_Type * p_reg, nrf_emmc_event_t event) +{ + *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL; + nrf_event_readback((uint8_t *)p_reg + (uint32_t)event); +} + +NRF_STATIC_INLINE bool nrf_emmc_event_check(NRF_EMMC_Type const * p_reg, nrf_emmc_event_t event) +{ + return nrf_event_check(p_reg, event); +} + +NRF_STATIC_INLINE uint32_t nrf_emmc_event_address_get(NRF_EMMC_Type const * p_reg, + nrf_emmc_event_t event) +{ + return nrf_task_event_address_get(p_reg, event); +} + +NRF_STATIC_INLINE void nrf_emmc_int_enable(NRF_EMMC_Type * p_reg, uint32_t mask) +{ + p_reg->INTEN |= mask; +} + +NRF_STATIC_INLINE uint32_t nrf_emmc_int_enable_check(NRF_EMMC_Type const * p_reg, uint32_t mask) +{ + return p_reg->INTEN & mask; +} + +NRF_STATIC_INLINE void nrf_emmc_int_disable(NRF_EMMC_Type * p_reg, uint32_t mask) +{ + p_reg->INTEN &= ~mask; +} + +NRF_STATIC_INLINE void nrf_emmc_config_set(NRF_EMMC_Type * p_reg, + nrf_emmc_config_t const * p_config) +{ + p_reg->CONFIG.CLKFREQHZ = p_config->clkfreqhz; + p_reg->CONFIG.BUSWIDTH = ((uint32_t)p_config->bus_width) & + SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Msk; + p_reg->CONFIG.READDELAY = (uint32_t)p_config->read_delay; + p_reg->CONFIG.READYTOTRANSFER = p_config->ready_to_transfer + ? SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Ready + : SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_NotReady; +} + +NRF_STATIC_INLINE void nrf_emmc_config_get(NRF_EMMC_Type const * p_reg, + nrf_emmc_config_t * p_config) +{ + p_config->clkfreqhz = p_reg->CONFIG.CLKFREQHZ; + p_config->bus_width = (nrf_emmc_bus_width_t)(p_reg->CONFIG.BUSWIDTH & + SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Msk); + p_config->read_delay = p_reg->CONFIG.READDELAY; + p_config->ready_to_transfer = p_reg->CONFIG.READYTOTRANSFER; +} + +NRF_STATIC_INLINE void nrf_emmc_config_set_ready_to_transfer(NRF_EMMC_Type * p_reg, + nrf_emmc_config_t const * p_config) +{ + p_reg->CONFIG.READYTOTRANSFER = p_config->ready_to_transfer + ? SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Ready + : SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_NotReady; +} + +NRF_STATIC_INLINE void nrf_emmc_config_get_ready_to_transfer(NRF_EMMC_Type const * p_reg, + nrf_emmc_config_t * p_config) +{ + p_config->ready_to_transfer = (p_reg->CONFIG.READYTOTRANSFER & + SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Msk) != + 0; +} + +NRF_STATIC_INLINE void nrf_emmc_command_set(NRF_EMMC_Type * p_reg, nrf_emmc_command_t const * p_cmd) +{ + p_reg->COMMAND.CMD = ((p_cmd->idx + << SP_EMMC_COMMAND_CMD_IDX_Pos) & SP_EMMC_COMMAND_CMD_IDX_Msk) | + ((p_cmd->resp_type + << SP_EMMC_COMMAND_CMD_RESPTYPE_Pos) & + SP_EMMC_COMMAND_CMD_RESPTYPE_Msk) | + ((p_cmd->resp_proc + << SP_EMMC_COMMAND_CMD_RESPPROC_Pos) & SP_EMMC_COMMAND_CMD_RESPPROC_Msk); + + p_reg->COMMAND.ARG = p_cmd->arg; + p_reg->COMMAND.RESPONSEADDR = p_cmd->resp_addr; +} + +NRF_STATIC_INLINE void nrf_emmc_command_get(NRF_EMMC_Type const * p_reg, nrf_emmc_command_t * p_cmd) +{ + uint32_t cmd_reg = p_reg->COMMAND.CMD; + + p_cmd->idx = (uint16_t)((cmd_reg & SP_EMMC_COMMAND_CMD_IDX_Msk) + >> SP_EMMC_COMMAND_CMD_IDX_Pos); + p_cmd->resp_type = (nrf_emmc_response_type_t)((cmd_reg & SP_EMMC_COMMAND_CMD_RESPTYPE_Msk) + >> SP_EMMC_COMMAND_CMD_RESPTYPE_Pos); + p_cmd->resp_proc = (nrf_emmc_response_proc_t)((cmd_reg & SP_EMMC_COMMAND_CMD_RESPPROC_Msk) + >> SP_EMMC_COMMAND_CMD_RESPPROC_Pos); + p_cmd->arg = p_reg->COMMAND.ARG; + p_cmd->resp_addr = p_reg->COMMAND.RESPONSEADDR; +} + +NRF_STATIC_INLINE void nrf_emmc_command_set_response(NRF_EMMC_Type * p_reg, + const uint32_t * response) +{ + for (uint8_t i = SP_EMMC_COMMAND_RESPONSE_MinIndex; i < SP_EMMC_COMMAND_RESPONSE_MaxCount; i++) + { + p_reg->COMMAND.RESPONSE[i] = response[i]; + } +} + +NRF_STATIC_INLINE void nrf_emmc_command_get_response(NRF_EMMC_Type const * p_reg, + uint32_t * response) +{ + for (uint8_t i = SP_EMMC_COMMAND_RESPONSE_MinIndex; i < SP_EMMC_COMMAND_RESPONSE_MaxCount; i++) + { + response[i] = p_reg->COMMAND.RESPONSE[i]; + } +} + +NRF_STATIC_INLINE void nrf_emmc_data_set(NRF_EMMC_Type * p_reg, nrf_emmc_data_t const * p_data) +{ + p_reg->DATA.BUFFERADDR = p_data->buffer_addr; + // p_reg->DATA.TARGETADDR = p_data->target_addr; + p_reg->DATA.BLOCKSIZE = p_data->block_size; + p_reg->DATA.BLOCKNUM = p_data->block_num; +} + +NRF_STATIC_INLINE void nrf_emmc_data_get(NRF_EMMC_Type const * p_reg, nrf_emmc_data_t * p_data) +{ + p_data->buffer_addr = p_reg->DATA.BUFFERADDR; + // p_data->target_addr = p_reg->DATA.TARGETADDR; + p_data->block_size = p_reg->DATA.BLOCKSIZE; + p_data->block_num = p_reg->DATA.BLOCKNUM; +} + +NRF_STATIC_INLINE void nrf_emmc_set_num_blocks(NRF_EMMC_Type * p_reg, + nrf_emmc_data_t const * p_data) +{ + p_reg->DATA.BLOCKNUM = p_data->block_num; +} + +NRF_STATIC_INLINE void nrf_emmc_get_num_blocks(NRF_EMMC_Type const * p_reg, + nrf_emmc_data_t * p_data) +{ + p_data->block_num = p_reg->DATA.BLOCKNUM; +} + +NRF_STATIC_INLINE void nrf_emmc_status_set(NRF_EMMC_Type * p_reg, + uint32_t error_mask) +{ + p_reg->STATUS.STATUS = error_mask; +} + +NRF_STATIC_INLINE uint32_t nrf_emmc_status_get(NRF_EMMC_Type const * p_reg) +{ + return p_reg->STATUS.STATUS; +} + +NRF_STATIC_INLINE bool nrf_emmc_status_error_check(uint32_t status) +{ + return (status & + (SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Msk | SP_EMMC_STATUS_STATUS_CMDCRCERROR_Msk | + SP_EMMC_STATUS_STATUS_DATACRCERROR_Msk | + SP_EMMC_STATUS_STATUS_RETRYEXCEEDED_Msk | SP_EMMC_STATUS_STATUS_PROTOCOLERR_Msk)) != + 0; +} + +NRF_STATIC_INLINE void nrf_emmc_handshake_set(NRF_EMMC_Type * p_reg, uint32_t val, uint8_t idx) +{ + p_reg->SPSYNC.AUX[idx] = val; +} + +NRF_STATIC_INLINE uint32_t nrf_emmc_handshake_get(NRF_EMMC_Type const * p_reg, uint8_t idx) +{ + return p_reg->SPSYNC.AUX[idx]; +} + +#endif // NRF_DECLARE_ONLY + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_EMMC_H__ diff --git a/softperipheral/sEMMC/include/nrf54h/semmc_firmware.h b/softperipheral/sEMMC/include/nrf54h/semmc_firmware.h new file mode 100644 index 0000000000..48af556491 --- /dev/null +++ b/softperipheral/sEMMC/include/nrf54h/semmc_firmware.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef SEMMC_FIRMWARE_H__ +#define SEMMC_FIRMWARE_H__ +#include "semmc_firmware_v0.1.0.h" +#define SOFTPERIPHERAL_META_HEADER_VERSION 2 +#endif diff --git a/softperipheral/sEMMC/include/nrf54h/semmc_firmware_v0.1.0.h b/softperipheral/sEMMC/include/nrf54h/semmc_firmware_v0.1.0.h new file mode 100644 index 0000000000..11abef2f29 --- /dev/null +++ b/softperipheral/sEMMC/include/nrf54h/semmc_firmware_v0.1.0.h @@ -0,0 +1,1156 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef SP_SEMMC_FIRMWARE_H__ +#define SP_SEMMC_FIRMWARE_H__ + +#include + +const uint8_t semmc_firmware_bin[] = { + 0x05, 0xa0, 0x12, 0x00, 0x3c, 0xe3, 0x10, 0x24, 0x00, 0x00, 0x01, 0x00, + 0x74, 0x03, 0x80, 0x00, 0x7a, 0xda, 0xe5, 0x12, 0x40, 0x37, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x06, 0x7a, 0xda, 0xe5, 0x12, 0x97, 0x02, 0x00, 0x00, + 0x81, 0x12, 0x03, 0xa3, 0xc2, 0x1e, 0x63, 0x02, 0x03, 0x06, 0x23, 0xa6, + 0x02, 0x1e, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xa3, 0x9e, 0x16, 0x93, + 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x43, 0x9a, 0x96, 0x93, 0x81, 0x45, + 0x7d, 0x56, 0x63, 0x0d, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x07, + 0xb5, 0x00, 0x63, 0x05, 0xc5, 0x00, 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, + 0x11, 0x03, 0xe5, 0xb7, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xc3, 0x9d, + 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xc3, 0x9c, 0xf1, 0x13, 0x81, 0x45, + 0x63, 0x0b, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x05, 0xb5, 0x00, + 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, 0x11, 0x03, 0xf5, 0xb7, 0x97, 0x11, + 0x00, 0x00, 0x83, 0xa1, 0x21, 0x94, 0x17, 0x11, 0x00, 0x00, 0x03, 0x21, + 0xa1, 0x9c, 0x33, 0x04, 0x01, 0x00, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0xe2, 0x9a, 0x73, 0x90, 0x72, 0x30, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0xe2, 0x91, 0x73, 0x90, 0x52, 0x30, 0x73, 0x10, 0x20, 0x34, 0x97, 0x12, + 0x00, 0x00, 0x83, 0xa2, 0x62, 0x9b, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, + 0x63, 0x96, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xa3, 0x92, 0x89, 0x28, + 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x82, 0x91, 0x17, 0x13, 0x00, 0x00, + 0x03, 0x23, 0x83, 0x97, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x83, 0x93, + 0x25, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x62, 0x95, 0x17, 0x13, + 0x00, 0x00, 0x03, 0x23, 0x23, 0x95, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, + 0x23, 0x92, 0x39, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x82, 0x92, + 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xc3, 0x95, 0x97, 0x13, 0x00, 0x00, + 0x83, 0xa3, 0x03, 0x8d, 0x11, 0x20, 0x21, 0xa8, 0x63, 0x8a, 0x62, 0x00, + 0x03, 0xa5, 0x03, 0x00, 0x23, 0xa0, 0xa2, 0x00, 0x91, 0x02, 0x91, 0x03, + 0xe3, 0x9a, 0x62, 0xfe, 0x82, 0x80, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0x62, 0x90, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x63, 0x8b, 0x25, 0x20, + 0x97, 0x12, 0x00, 0x00, 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0xe7, 0x04, + 0x92, 0x40, 0x02, 0x44, 0x21, 0x01, 0x82, 0x80, 0x37, 0x47, 0x0e, 0x00, + 0x13, 0x07, 0x07, 0x10, 0xb3, 0x57, 0xf7, 0x00, 0x85, 0x8b, 0xe3, 0x89, + 0x07, 0xea, 0x93, 0x05, 0x84, 0x05, 0x13, 0x05, 0x04, 0x03, 0xef, 0xf0, + 0xaf, 0x8d, 0x83, 0x47, 0xe4, 0x04, 0x49, 0x47, 0x63, 0x85, 0xe7, 0x00, + 0x65, 0x47, 0xe3, 0x90, 0xe7, 0xea, 0x38, 0x54, 0x97, 0xd7, 0xff, 0xff, + 0x83, 0xa7, 0x07, 0x7a, 0x58, 0xd4, 0x93, 0x76, 0xf7, 0x0f, 0x13, 0x56, + 0x87, 0x00, 0x83, 0xc5, 0xc7, 0x06, 0x13, 0x76, 0xf6, 0x0f, 0x23, 0x86, + 0xd7, 0x06, 0x93, 0x56, 0x07, 0x01, 0x83, 0xc5, 0xd7, 0x06, 0x93, 0xf6, + 0xf6, 0x0f, 0xa3, 0x86, 0xc7, 0x06, 0x03, 0xc6, 0xe7, 0x06, 0x61, 0x83, + 0x23, 0x87, 0xd7, 0x06, 0x83, 0xc6, 0xf7, 0x06, 0xa3, 0x87, 0xe7, 0x06, + 0x8d, 0xb5, 0xad, 0x17, 0x93, 0xf7, 0xf7, 0x0f, 0x71, 0x47, 0xe3, 0x63, + 0xf7, 0xe4, 0x37, 0x07, 0x20, 0x16, 0x13, 0x07, 0x97, 0x67, 0xb3, 0x57, + 0xf7, 0x00, 0x85, 0x8b, 0xd9, 0xf3, 0x0d, 0xbd, 0x09, 0x47, 0x83, 0xc6, + 0x07, 0x07, 0x23, 0x88, 0xe7, 0x06, 0x9d, 0xb5, 0x21, 0x47, 0x83, 0xc6, + 0x07, 0x07, 0x23, 0x88, 0xe7, 0x06, 0xa9, 0xbd, 0x7d, 0x57, 0x63, 0x18, + 0xe5, 0x00, 0x05, 0x47, 0x83, 0xc6, 0x07, 0x07, 0x23, 0x88, 0xe7, 0x06, + 0xa1, 0xb5, 0x41, 0x47, 0x83, 0xc6, 0x07, 0x07, 0x23, 0x88, 0xe7, 0x06, + 0x35, 0xbd, 0x41, 0x11, 0x06, 0xc6, 0x2e, 0xc0, 0x15, 0xc9, 0x26, 0xc2, + 0x81, 0x45, 0xb2, 0x84, 0x13, 0x06, 0x40, 0x19, 0x22, 0xc4, 0x2a, 0x84, + 0x95, 0x22, 0x82, 0x47, 0x23, 0x28, 0x94, 0x18, 0x23, 0x22, 0x04, 0x18, + 0x23, 0x20, 0xf4, 0x18, 0x23, 0x24, 0x04, 0x18, 0x23, 0x26, 0x04, 0x18, + 0x22, 0x44, 0x92, 0x44, 0x01, 0x45, 0xb2, 0x40, 0x41, 0x01, 0x82, 0x80, + 0x7d, 0x55, 0xe5, 0xbf, 0x1d, 0xc1, 0x15, 0xc2, 0xfd, 0x47, 0x63, 0xe0, + 0xb7, 0x02, 0x93, 0x97, 0x35, 0x00, 0xaa, 0x97, 0x90, 0xc3, 0xd4, 0xc3, + 0x83, 0x27, 0x85, 0x18, 0x63, 0xe5, 0xf5, 0x00, 0x85, 0x05, 0x23, 0x24, + 0xb5, 0x18, 0x01, 0x45, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x05, 0xc1, + 0x83, 0x27, 0xc5, 0x18, 0x7d, 0x47, 0x63, 0x6c, 0xf7, 0x00, 0x13, 0x97, + 0x27, 0x00, 0x2a, 0x97, 0x23, 0x20, 0xb7, 0x10, 0x85, 0x07, 0x23, 0x26, + 0xf5, 0x18, 0x01, 0x45, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0xaa, 0x87, + 0x01, 0xc9, 0x03, 0x27, 0x45, 0x18, 0x01, 0x45, 0x4d, 0x8f, 0x23, 0xa2, + 0xe7, 0x18, 0x82, 0x80, 0x7d, 0x55, 0x82, 0x80, 0x5d, 0xc5, 0x21, 0x11, + 0x22, 0xc8, 0x06, 0xca, 0x83, 0x27, 0x05, 0x18, 0x03, 0x27, 0x85, 0x18, + 0x2a, 0x84, 0x63, 0xfc, 0xe7, 0x08, 0x26, 0xc6, 0x29, 0x47, 0x93, 0x96, + 0x37, 0x00, 0xa2, 0x96, 0x03, 0xa3, 0x06, 0x00, 0x2c, 0x00, 0x22, 0x85, + 0x63, 0x05, 0x03, 0x06, 0xd4, 0x42, 0x83, 0x24, 0x44, 0x18, 0xf5, 0x8c, + 0x26, 0xc4, 0x91, 0xe0, 0xb9, 0xe6, 0x03, 0x26, 0x04, 0x19, 0x3a, 0xc0, + 0x3e, 0xc2, 0x02, 0x93, 0x02, 0x47, 0x03, 0x26, 0x84, 0x18, 0x93, 0x16, + 0x35, 0x00, 0x93, 0xc4, 0xf4, 0xff, 0xa2, 0x96, 0x7d, 0x17, 0x63, 0x74, + 0xc5, 0x04, 0xa2, 0x45, 0x03, 0x26, 0x44, 0x18, 0x92, 0x47, 0xcd, 0x8c, + 0x65, 0x8e, 0x23, 0x20, 0xa4, 0x18, 0x23, 0x22, 0xc4, 0x18, 0x63, 0x0c, + 0xf5, 0x00, 0xd4, 0x42, 0xaa, 0x87, 0x81, 0xea, 0x4d, 0xf3, 0xb2, 0x44, + 0x7d, 0x55, 0xd2, 0x40, 0x42, 0x44, 0x61, 0x01, 0x82, 0x80, 0xd2, 0x40, + 0x42, 0x44, 0xb2, 0x44, 0x01, 0x45, 0x61, 0x01, 0x82, 0x80, 0xd2, 0x40, + 0x42, 0x44, 0xb2, 0x44, 0x71, 0x55, 0x61, 0x01, 0x82, 0x80, 0xd2, 0x40, + 0x42, 0x44, 0xb2, 0x44, 0x6d, 0x55, 0x61, 0x01, 0x82, 0x80, 0x79, 0x55, + 0xc9, 0xbf, 0x79, 0x55, 0x82, 0x80, 0x01, 0xc5, 0x03, 0x25, 0x05, 0x18, + 0x82, 0x80, 0x01, 0x45, 0x82, 0x80, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, + 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, + 0x01, 0xa0, 0x01, 0xa0, 0x82, 0x80, 0x00, 0x00, 0x13, 0x03, 0xf0, 0x00, + 0x13, 0x07, 0x05, 0x00, 0x63, 0x7e, 0xc3, 0x02, 0x93, 0x77, 0xf7, 0x00, + 0x63, 0x90, 0x07, 0x0a, 0x63, 0x92, 0x05, 0x08, 0x93, 0x76, 0x06, 0xff, + 0x13, 0x76, 0xf6, 0x00, 0xb3, 0x86, 0xe6, 0x00, 0x23, 0x20, 0xb7, 0x00, + 0x23, 0x22, 0xb7, 0x00, 0x23, 0x24, 0xb7, 0x00, 0x23, 0x26, 0xb7, 0x00, + 0x13, 0x07, 0x07, 0x01, 0xe3, 0x66, 0xd7, 0xfe, 0x63, 0x14, 0x06, 0x00, + 0x67, 0x80, 0x00, 0x00, 0xb3, 0x06, 0xc3, 0x40, 0x93, 0x96, 0x26, 0x00, + 0x97, 0x02, 0x00, 0x00, 0xb3, 0x86, 0x56, 0x00, 0x67, 0x80, 0xc6, 0x00, + 0x23, 0x07, 0xb7, 0x00, 0xa3, 0x06, 0xb7, 0x00, 0x23, 0x06, 0xb7, 0x00, + 0xa3, 0x05, 0xb7, 0x00, 0x23, 0x05, 0xb7, 0x00, 0xa3, 0x04, 0xb7, 0x00, + 0x23, 0x04, 0xb7, 0x00, 0xa3, 0x03, 0xb7, 0x00, 0x23, 0x03, 0xb7, 0x00, + 0xa3, 0x02, 0xb7, 0x00, 0x23, 0x02, 0xb7, 0x00, 0xa3, 0x01, 0xb7, 0x00, + 0x23, 0x01, 0xb7, 0x00, 0xa3, 0x00, 0xb7, 0x00, 0x23, 0x00, 0xb7, 0x00, + 0x67, 0x80, 0x00, 0x00, 0x93, 0xf5, 0xf5, 0x0f, 0x93, 0x96, 0x85, 0x00, + 0xb3, 0xe5, 0xd5, 0x00, 0x93, 0x96, 0x05, 0x01, 0xb3, 0xe5, 0xd5, 0x00, + 0x6f, 0xf0, 0xdf, 0xf6, 0x93, 0x96, 0x27, 0x00, 0x97, 0x02, 0x00, 0x00, + 0xb3, 0x86, 0x56, 0x00, 0x93, 0x82, 0x00, 0x00, 0xe7, 0x80, 0x06, 0xfa, + 0x93, 0x80, 0x02, 0x00, 0x93, 0x87, 0x07, 0xff, 0x33, 0x07, 0xf7, 0x40, + 0x33, 0x06, 0xf6, 0x00, 0xe3, 0x78, 0xc3, 0xf6, 0x6f, 0xf0, 0xdf, 0xf3, + 0x7c, 0x35, 0x00, 0x00, 0x40, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7c, 0x35, 0x00, 0x00, 0x40, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7c, 0x35, 0x00, 0x00, 0x40, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x7c, 0x35, 0x00, 0x00, 0x40, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x40, 0x37, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, 0x94, 0x39, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x94, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +const uint32_t semmc_firmware_bin_len = 13692; +#endif // SP_SEMMC_FIRMWARE_H__ diff --git a/softperipheral/sEMMC/include/nrf54l/semmc_firmware.h b/softperipheral/sEMMC/include/nrf54l/semmc_firmware.h new file mode 100644 index 0000000000..48af556491 --- /dev/null +++ b/softperipheral/sEMMC/include/nrf54l/semmc_firmware.h @@ -0,0 +1,11 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef SEMMC_FIRMWARE_H__ +#define SEMMC_FIRMWARE_H__ +#include "semmc_firmware_v0.1.0.h" +#define SOFTPERIPHERAL_META_HEADER_VERSION 2 +#endif diff --git a/softperipheral/sEMMC/include/nrf54l/semmc_firmware_v0.1.0.h b/softperipheral/sEMMC/include/nrf54l/semmc_firmware_v0.1.0.h new file mode 100644 index 0000000000..1ae8609e1f --- /dev/null +++ b/softperipheral/sEMMC/include/nrf54l/semmc_firmware_v0.1.0.h @@ -0,0 +1,1152 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef SP_SEMMC_FIRMWARE_H__ +#define SP_SEMMC_FIRMWARE_H__ + +#include + +const uint8_t semmc_firmware_bin[] = { + 0x05, 0xa0, 0x12, 0x00, 0x3c, 0xe3, 0x08, 0x22, 0x00, 0x00, 0x01, 0x00, + 0xc0, 0x03, 0x80, 0x00, 0x7a, 0xda, 0xe5, 0x12, 0x00, 0x3c, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x06, 0x7a, 0xda, 0xe5, 0x12, 0x97, 0x02, 0x00, 0x00, + 0x81, 0x12, 0x03, 0xa3, 0xc2, 0x1e, 0x63, 0x02, 0x03, 0x06, 0x23, 0xa6, + 0x02, 0x1e, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xa3, 0x9e, 0x16, 0x93, + 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x43, 0x9a, 0x96, 0x93, 0x81, 0x45, + 0x7d, 0x56, 0x63, 0x0d, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x07, + 0xb5, 0x00, 0x63, 0x05, 0xc5, 0x00, 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, + 0x11, 0x03, 0xe5, 0xb7, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xc3, 0x9d, + 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xc3, 0x9c, 0xf1, 0x13, 0x81, 0x45, + 0x63, 0x0b, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x05, 0xb5, 0x00, + 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, 0x11, 0x03, 0xf5, 0xb7, 0x97, 0x11, + 0x00, 0x00, 0x83, 0xa1, 0x21, 0x94, 0x17, 0x11, 0x00, 0x00, 0x03, 0x21, + 0xa1, 0x9c, 0x33, 0x04, 0x01, 0x00, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0xe2, 0x9a, 0x73, 0x90, 0x72, 0x30, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0xe2, 0x91, 0x73, 0x90, 0x52, 0x30, 0x73, 0x10, 0x20, 0x34, 0x97, 0x12, + 0x00, 0x00, 0x83, 0xa2, 0x62, 0x9b, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, + 0x63, 0x96, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xa3, 0x92, 0x89, 0x28, + 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x82, 0x91, 0x17, 0x13, 0x00, 0x00, + 0x03, 0x23, 0x83, 0x97, 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0x6f, 0xf0, 0xdf, 0xf6, 0x93, 0x96, 0x27, 0x00, + 0x97, 0x02, 0x00, 0x00, 0xb3, 0x86, 0x56, 0x00, 0x93, 0x82, 0x00, 0x00, + 0xe7, 0x80, 0x06, 0xfa, 0x93, 0x80, 0x02, 0x00, 0x93, 0x87, 0x07, 0xff, + 0x33, 0x07, 0xf7, 0x40, 0x33, 0x06, 0xf6, 0x00, 0xe3, 0x78, 0xc3, 0xf6, + 0x6f, 0xf0, 0xdf, 0xf3, 0x44, 0x35, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x44, 0x35, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x44, 0x35, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x44, 0x35, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, + 0x54, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x3e, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +const uint32_t semmc_firmware_bin_len = 13636; +#endif // SP_SEMMC_FIRMWARE_H__ diff --git a/softperipheral/sEMMC/include/nrf_config_semmc.h b/softperipheral/sEMMC/include/nrf_config_semmc.h new file mode 100644 index 0000000000..9f6faf2bbc --- /dev/null +++ b/softperipheral/sEMMC/include/nrf_config_semmc.h @@ -0,0 +1,37 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef NRF_SEMMC_CONFIG_H__ +#define NRF_SEMMC_CONFIG_H__ + +/** + * @brief NRF_SEMMC_ENABLED + * + * Boolean. Accepted values: 0 and 1. + */ +#ifndef NRF_SEMMC_ENABLED +#define NRF_SEMMC_ENABLED 0 +#endif + +/** + * @brief NRF_SEMMC_RESPONSE_SIZE + * + * Integer value. Word size of eMMC response + */ +#ifndef NRF_SEMMC_RESPONSE_SIZE +#define NRF_SEMMC_RESPONSE_SIZE 4 +#endif // NRF_SEMMC_T_SIZE + +/** + * @brief NRF_SEMMC_TRANSFERS_PER_REQUEST - Maximal number of transfers that can be passed in an array for a single request. It is the maximal value in the cmd_count parameter. + * + * Integer value. + */ +#ifndef NRF_SEMMC_TRANSFERS_PER_REQUEST +#define NRF_SEMMC_TRANSFERS_PER_REQUEST 1 +#endif + +#endif // NRF_SEMMC_CONFIG_H__ diff --git a/softperipheral/sEMMC/include/nrf_semmc.h b/softperipheral/sEMMC/include/nrf_semmc.h new file mode 100644 index 0000000000..6aef6b7de7 --- /dev/null +++ b/softperipheral/sEMMC/include/nrf_semmc.h @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef NRF_SEMMC_H__ +#define NRF_SEMMC_H__ + +#include +#include +#include "nrf_config_semmc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @defgroup nrf_semmc Soft eMMC + * @{ + * + * @brief Soft eMMC driver + * + * This API describes the driver operation of a Software eMMC emulated in a VPR CPU. Based on JEDEC Standard No. 84-B51A. + * + * The functions in this driver are not reentrant if they operate on the same eMMC peripheral. It is + * the responsibility of the API user to ensure the functions are not preempted by each other. + * An exception is the callback function context. Multiple functions from this API can be called + * from the callback. + * + * @note The nrf_semmc_irq_handler() function must be called from an external IRQ handler that has + * been properly registered with the interrupt controller system. + * + * @note The GPIO pins required for eMMC operation must be properly configured by the user before + * initializing the driver with nrf_semmc_init(). + */ + +/** @brief eMMC command index definitions */ +typedef enum +{ + NRF_SEMMC_CMD0_GO_IDLE_STATE = 0, + NRF_SEMMC_CMD1_SEND_OP_COND = 1, + NRF_SEMMC_CMD2_ALL_SEND_CID = 2, + NRF_SEMMC_CMD3_SET_RELATIVE_ADDR = 3, + NRF_SEMMC_CMD4_SET_DSR = 4, + NRF_SEMMC_CMD5_SLEEP_AWAKE = 5, + NRF_SEMMC_CMD6_SWITCH = 6, + NRF_SEMMC_CMD7_SELECT_DESELECT = 7, + NRF_SEMMC_CMD8_SEND_EXT_CSD = 8, + NRF_SEMMC_CMD9_SEND_CSD = 9, + NRF_SEMMC_CMD10_SEND_CID = 10, + NRF_SEMMC_CMD12_STOP_TRANSMISSION = 12, + NRF_SEMMC_CMD13_SEND_STATUS = 13, + NRF_SEMMC_CMD14_BUSTEST_R = 14, + NRF_SEMMC_CMD15_GO_INACTIVE_STATE = 15, + NRF_SEMMC_CMD16_SET_BLOCKLEN = 16, + NRF_SEMMC_CMD17_READ_SINGLE = 17, + NRF_SEMMC_CMD18_READ_MULTIPLE = 18, + NRF_SEMMC_CMD19_BUSTEST_W = 19, + NRF_SEMMC_CMD21_SEND_TUNING_BLOCK = 21, + NRF_SEMMC_CMD23_SET_BLOCK_COUNT = 23, + NRF_SEMMC_CMD24_WRITE_BLOCK = 24, + NRF_SEMMC_CMD25_WRITE_MULTIPLE = 25, + NRF_SEMMC_CMD26_PROGRAM_CID = 26, + NRF_SEMMC_CMD27_PROGRAM_CSD = 27, + NRF_SEMMC_CMD28_SET_WRITE_PROT = 28, + NRF_SEMMC_CMD29_CLR_WRITE_PROT = 29, + NRF_SEMMC_CMD30_SEND_WRITE_PROT = 30, + NRF_SEMMC_CMD31_SEND_WRITE_PROT_TYPE = 31, + NRF_SEMMC_CMD35_ERASE_GROUP_START = 35, + NRF_SEMMC_CMD36_ERASE_GROUP_END = 36, + NRF_SEMMC_CMD38_ERASE = 38, + NRF_SEMMC_CMD42_LOCK_UNLOCK = 42, + NRF_SEMMC_CMD44_QUEUED_TASK_PARAMS = 44, + NRF_SEMMC_CMD45_QUEUED_TASK_ADDRESS = 45, + NRF_SEMMC_CMD46_EXECUTE_READ_TASK = 46, + NRF_SEMMC_CMD47_EXECUTE_WRITE_TASK = 47, + NRF_SEMMC_CMD48_CMDQ_TASK_MGMT = 48, + NRF_SEMMC_CMD49_SET_TIME = 49, +} nrf_semmc_cmd_t; + +typedef enum +{ + NRF_SEMMC_RESP_NONE, + NRF_SEMMC_RESP_R1, + NRF_SEMMC_RESP_R1B, + NRF_SEMMC_RESP_R2, + NRF_SEMMC_RESP_R3, + NRF_SEMMC_RESP_R4, + NRF_SEMMC_RESP_R5, +} nrf_semmc_resp_type_t; + +typedef enum +{ + NRF_SEMMC_SUCCESS = 0, + NRF_SEMMC_ERROR_TIMEOUT, + NRF_SEMMC_ERROR_CMDTIMEOUT, + NRF_SEMMC_ERROR_CMDCRCERROR, + NRF_SEMMC_ERROR_DATACRCERROR, + NRF_SEMMC_ERROR_ILLEGAL_CMD, + NRF_SEMMC_ERROR_DEVICE_REJECTED, + NRF_SEMMC_ERROR_INTERNAL_OR_PROTOCOL, + NRF_SEMMC_ERROR_BUSY, + NRF_SEMMC_ERROR_UNSUPPORTED, + NRF_SEMMC_ERROR_INVALID_PARAM, + NRF_SEMMC_ERROR_INVALID_STATE, + NRF_SEMMC_ERROR_HW_FAULT, +} nrf_semmc_error_t; + +typedef enum +{ + NRF_SEMMC_BUS_WIDTH_1 = 1, + NRF_SEMMC_BUS_WIDTH_4 = 4, + NRF_SEMMC_BUS_WIDTH_8 = 8, +} nrf_semmc_bus_width_t; + +typedef enum +{ + NRF_SEMMC_EVT_XFER_DONE, ///< Transfer operation has finished + NRF_SEMMC_EVT_XFER_STARTED, ///< The operation has been accepted and scheduled to be started. +} nrf_semmc_event_type_t; + +typedef enum +{ + NRF_SEMMC_RESULT_OK, ///< Operation finished successfully + NRF_SEMMC_RESULT_ABORTED, ///< Operation was aborted +} nrf_semmc_event_xfer_done_t; + +typedef struct +{ + nrf_semmc_event_type_t type; ///< Event type + union + { + nrf_semmc_event_xfer_done_t xfer_done; ///< Data for @ref NRF_SQSPI_EVT_XFER_DONE event + } data; ///< Event-type-specific data +} nrf_semmc_event_t; + +/** + * @brief Callback function type for eMMC driver events. + * + * This handler is invoked when an asynchronous operation (such as a command or data transfer) + * completes or when an error or device interrupt occurs. + * + * The function may be called from interrupt context. + * + * @param p_event Pointer to the event structure describing the event. + * @param p_context Pointer to user-provided context data (as supplied during initialization). + */ +typedef void (* nrf_semmc_event_handler_t)(nrf_semmc_event_t const * p_event, void * p_context); + +/** + * @brief Configuration for initializing an eMMC driver instance. + */ +typedef struct +{ + void * spis_instance; ///< Hardware instance pointer or base address of optional SPI slave(implementation-defined). + uint32_t process_response; ///< How to process a command's response + uint32_t clk_freq_hz; ///< Clock frequency in Hz to set during initialization. + uint32_t read_delay; ///< FLPR clock cycle number to delay data sampling. + nrf_semmc_bus_width_t bus_width; ///< 1, 4, or 8 bits. +} nrf_semmc_config_t; + +typedef struct +{ + uint8_t cmd; ///< Command code. @ref nrf_semmc_cmd_t can be used to set this value. + uint32_t arg; ///< Command argument + nrf_semmc_resp_type_t resp_type; ///< Response type. @ref nrf_semmc_resp_type_t can be used to set this value + void * resp_buffer; ///< Pointer to the response buffer for transfer. Used for raw response sampling, VPR must have access tho this memory location. + uint32_t response[NRF_SEMMC_RESPONSE_SIZE]; ///< Array to hold processed response. Application logic uses this + nrf_semmc_error_t err; ///< Command error code. It will be set by API after a transfer. A subset of @ref nrf_semmc_error_t +} nrf_semmc_cmd_desc_t; + +/** + * @brief Descriptor for data transfer operations. + * + * Note that the eMMC device address for an addressed transfer is specified in the 'arg' field + * of the associated nrf_semmc_cmd_desc_t structure, so there's no need for a separate + * block_addr field in this structure. + */ +typedef struct +{ + void * buffer; ///< MCU bus address - pointer to data buffer for transfer + uint32_t block_size; ///< Size of each block in bytes + uint32_t num_blocks; ///< Number of blocks to transfer + /* + * The block_addr is intentionally not included here as it's supplied in the + * 'arg' field of the associated command descriptor (nrf_semmc_cmd_desc_t) + */ +} nrf_semmc_transfer_desc_t; + +/** @brief Flag indicating that the transfer is prepared but not started */ +#define NRF_SEMMC_FLAG_HOLD_XFER (1UL << 0) + +/** + * @brief sEMMC driver instance structure. + */ +typedef struct +{ + void * p_reg; ///< Pointer to a structure with sEMMC virtual register interface. + uint8_t + drv_inst_idx; ///< Index of the driver instance. For internal use only. +} nrf_semmc_t; + +/** + * @brief Initialize the eMMC controller driver for a given instance. + * + * The data buffer pointed by @p p_semmc is managed by the API user. It must be valid as long + * as the device driver is initialized and used. After the device driver finishes all its + * operations and the controller is disabled, the buffer can be freed. + * + * @note The GPIO pins required for eMMC operation must be properly configured by the API user + * before calling this function. + * + * @param[out] p_semmc Pointer to the eMMC driver instance to initialize. + * @param[in] handler Event handler callback function. + * @param[in] p_context User context passed to the event handler. + * + * @retval NRF_SEMMC_SUCCESS Initialization successful. + * @retval NRF_SEMMC_ERROR_INVALID_PARAM Invalid or NULL parameter provided. + * @retval NRF_SEMMC_ERROR_HW_FAULT Hardware initialization failed. + * @retval NRF_SEMMC_ERROR_INTERNAL Internal error during initialization. + */ +nrf_semmc_error_t nrf_semmc_init(nrf_semmc_t const * p_semmc, + nrf_semmc_event_handler_t handler, + void * p_context); + +/** + * @brief Uninitialize the sEMMC driver instance. + * + * This function deconfigures the peripheral. + * + * @note The function deactivates the peripheral instance if it is active. + * The deactivation process releases the clock requests and the power + * states restrictions related to VPR. + * + * @param[in] p_semmc Identifier of the sEMMC instance to uninitialize. + */ +void nrf_semmc_uninit(nrf_semmc_t const * p_semmc); + +/** + * @brief Explicitly power up and configure the controller. + * + * Optional: Recommended around sequences of operations to avoid repeated power toggling latency. + * + * @param[in] p_semmc Pointer to the eMMC driver instance. + * + * @retval NRF_SEMMC_SUCCESS Controller powered up successfully. + * @retval NRF_SEMMC_ERROR_INVALID_PARAM Invalid or NULL parameter provided. + * @retval NRF_SEMMC_ERROR_HW_FAULT Hardware power-up failed. + * @retval NRF_SEMMC_ERROR_INTERNAL Internal error during power-up. + */ +nrf_semmc_error_t nrf_semmc_enable(nrf_semmc_t const * p_semmc); + +/** + * @brief Explicitly power down the controller. + * + * Optional: Call after a series of operations to save power. + * + * @param[in] p_semmc Pointer to the eMMC driver instance. + * + * @retval NRF_SEMMC_SUCCESS Controller powered down successfully. + * @retval NRF_SEMMC_ERROR_INVALID_PARAM Invalid or NULL parameter provided. + * @retval NRF_SEMMC_ERROR_BUSY Controller is busy with an operation. + * @retval NRF_SEMMC_ERROR_HW_FAULT Hardware power-down failed. + */ +nrf_semmc_error_t nrf_semmc_disable(nrf_semmc_t const * p_semmc); + +/** + * @brief Start an asynchronous command. + * + * May return immediately with error. The user callback will be invoked on completion. + * No other driver calls should be made on this instance until the callback fires. + * + * It is the caller's responsibility to implement a timeout mechanism to detect + * if the device becomes unresponsive. The driver itself does not implement timeouts + * for command completion. + * + * For commands that require a STOP_TRANSMISSION command (CMD12) and cleanup afterwards, + * the caller is responsible for issuing the stop command and + * performing the necessary cleanup. This applies to the following commands: + * - NRF_SEMMC_CMD18_READ_MULTIPLE (CMD18) + * - NRF_SEMMC_CMD25_WRITE_MULTIPLE (CMD25) + * + * The caller is responsible for proper cache management of any memory buffers referenced + * in the p_transfer structure. This includes flushing the cache before writing data to + * the eMMC device (for data being read by the DMA) and invalidating the cache before + * reading data received from the eMMC device (for data written by the DMA). Additionally, + * it is the caller's responsibility to ensure that buffers are properly aligned and padded + * according to cache line boundaries to prevent data corruption when invalidating the cache. + * + * @param p_semmc Pointer to the eMMC driver instance. + * @param p_cmd Pointer to the command descriptor structure. + * @param p_config Pointer to the configuration structure. + * @param p_transfer Pointer to the transfer descriptor structure. + * @param cmd_count Number of transfers in the array pointed by @p p_cmd. + * @param flags Transfer options (0 for default settings). + * + * @retval NRF_SEMMC_SUCCESS Command started successfully; completion will be reported via callback. + * @retval NRF_SEMMC_ERROR_BUSY Driver is busy with another operation. + * @retval NRF_SEMMC_ERROR_INVALID_PARAM Invalid parameter(s) provided. + * @retval NRF_SEMMC_ERROR_UNSUPPORTED Command or operation not supported. + * @retval NRF_SEMMC_ERROR_INTERNAL Internal error occurred. + */ +nrf_semmc_error_t nrf_semmc_cmd(nrf_semmc_t const * p_semmc, + nrf_semmc_cmd_desc_t * p_cmd, + nrf_semmc_config_t const * p_config, + nrf_semmc_transfer_desc_t * p_transfer, + size_t cmd_count, + uint32_t flags); + +/** + * @brief prepare to start an asynchronous command. + * + * This function is an equivalent of @ref nrf_semmc_cmd with @ref + * NRF_SEMMC_FLAG_HOLD_XFER flag set. + * + * The start of the prepared transfer must be triggered outside of this + * function. + * @sa nrf_semmc_start_task_address_get + * + * If the controller mode transfer is in progress, a new transfer can be + * requested. If the driver is capable of queueing the requested transfer, the + * function returns NRF_SEMMC_SUCCESS. If not, it returns NRF_SEMMC_ERROR_BUSY. If the + * target mode transfer is idle waiting for the remote controller, new transfer + * requests abort the idling transfer and the @ref nrf_semmc_event_handler_t is + * called to indicate aborted transfer. If the target mode transfer is activated + * by the remote controller, a new requested transfer can be queued by the + * driver. If the driver is capable of queuing the new transfer, the function + * returns NRF_SEMMC_SUCCESS. Otherwise, it returns NRF_SEMMC_ERROR_BUSY. + * + * @param p_semmc Pointer to the eMMC driver instance. + * @param p_cmd Pointer to the command descriptor structure. + * @param p_config Pointer to the configuration structure. + * @param p_transfer Pointer to the transfer descriptor structure. + * @param cmd_count Number of transfers in the array pointed by @p p_cmd. + * + * @retval NRF_SEMMC_SUCCESS The transfer is prepared + * @retval NRF_SEMMC_ERROR_BUSY There is ongoing transfer + */ + +nrf_semmc_error_t nrf_semmc_cmd_prepare(nrf_semmc_t const * p_semmc, + nrf_semmc_cmd_desc_t * p_cmd, + nrf_semmc_config_t const * p_config, + nrf_semmc_transfer_desc_t * p_transfer, + size_t cmd_count); + +/** + * @brief Get an address of the task register to start the prepared transfer. + * + * The transfer to start must be prepared with @ref nrf_semmc_cmd_prepare. + * + * To trigger a start task write a non-zero value to the returned address or use + * the DPPI subsystem. + * + * If the device is configured in controller mode, the transfer starts + * immediately when the task is triggered. If the device is configured in target + * mode, the task must be triggered first, and then the transfer starts when a + * remote controller initializes it. + * + * @param[in] p_semmc Identifier of the sEMMC instance transferring data. + * + * @returns Address of the task register to start the prepared transfer, or NULL + * if there is no such task. + */ +uint32_t * nrf_semmc_start_task_address_get(nrf_semmc_t const * p_semmc); + +/** + * @brief Abort any ongoing eMMC operation. + * + * This function forcibly terminates any pending eMMC command or data transfer + * operations. It should be used as a recovery mechanism when a command has + * timed out or the driver appears to be in a stuck state. + * + * After calling this function, the driver will attempt to reset internal state + * and hardware, making it ready to accept new commands. + * + * Called by @ref nrf_semmc_disable if there is an ongoing transfer + * + * @param p_semmc Pointer to the eMMC driver instance. + * + * @retval NRF_SEMMC_SUCCESS Operation aborted successfully. + * @retval NRF_SEMMC_ERROR_INVALID_PARAM Invalid or NULL parameter provided. + * @retval NRF_SEMMC_ERROR_HW_FAULT Hardware reset failed. + * @retval NRF_SEMMC_ERROR_INTERNAL Internal error during abort. + */ +nrf_semmc_error_t nrf_semmc_abort(nrf_semmc_t const * p_semmc); + +/** + * @brief Returns true if an operation is still in progress. + */ +bool nrf_semmc_is_busy(nrf_semmc_t const * p_semmc); + +/** + * @brief IRQ handler to be called from the eMMC interrupt vector. + */ +void nrf_semmc_irq_handler(void); + +/** @} */ + +#ifdef __cplusplus +} +#endif + +#endif // NRF_SEMMC_H__ diff --git a/softperipheral/sEMMC/include/nrf_sp_emmc.h b/softperipheral/sEMMC/include/nrf_sp_emmc.h new file mode 100644 index 0000000000..3974204ac3 --- /dev/null +++ b/softperipheral/sEMMC/include/nrf_sp_emmc.h @@ -0,0 +1,476 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef NRF_SP_EMMC_H__ +#define NRF_SP_EMMC_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "nrf.h" // Resolve nrfXX_types.h for the correct target to get definitions for __IO, __IOM etc. +/* =========================================================================================================================== + * ================ SP_EMMC ================ + * ===========================================================================================================================*/ + +#if !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) /*!< Ignore C structs for assembly code. */ + +/* ================================================== Struct SP_EMMC_CONFIG ================================================== */ +/** + * @brief CONFIG [SP_EMMC_CONFIG] SEMMC configuration + */ +typedef struct +{ + __IOM uint32_t READYTOTRANSFER; /*!< (@ 0x00000000) Indicates that SEMMC has parsed a configuration and it + * is ready to transfer*/ + __IOM uint32_t CLKFREQHZ; /*!< (@ 0x00000004) SEMMC Clock Frequency in Hz */ + __IOM uint32_t BUSWIDTH; /*!< (@ 0x00000008) SEMMC Bus width */ + __IOM uint32_t NUMRETRIES; /*!< (@ 0x0000000C) Number of retries for a transaction */ + __IOM uint32_t READDELAY; /*!< (@ 0x00000010) Number of FLPR clock cycles to offset for data sampling + * point*/ +} NRF_SP_EMMC_CONFIG_Type; /*!< Size = 20 (0x014) */ + +/* SP_EMMC_CONFIG_READYTOTRANSFER: Indicates that SEMMC has parsed a configuration and it is ready to transfer */ + #define SP_EMMC_CONFIG_READYTOTRANSFER_ResetValue (0x00000000UL) /*!< Reset value of READYTOTRANSFER register. */ + +/* READYTOTRANSFER @Bit 0 : SEMMC is ready to transfer */ + #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Pos (0UL) /*!< Position of READYTOTRANSFER field. */ + #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Msk \ + (0x1UL << SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Pos) \ + /*!< + * Bit mask of READYTOTRANSFER field.*/ + #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Min (0x0UL) /*!< Min enumerator value of READYTOTRANSFER field. */ + #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Max (0x1UL) /*!< Max enumerator value of READYTOTRANSFER field. */ + #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_NotReady (0x0UL) /*!< SEMMC is not ready */ + #define SP_EMMC_CONFIG_READYTOTRANSFER_READYTOTRANSFER_Ready (0x1UL) /*!< SEMMC is ready */ + +/* SP_EMMC_CONFIG_CLKFREQHZ: SEMMC Clock Frequency in Hz */ + #define SP_EMMC_CONFIG_CLKFREQHZ_ResetValue (0x00000000UL) /*!< Reset value of CLKFREQHZ register. */ + +/* CLKFREQHZ @Bits 0..31 : SEMMC Clock Frequency in Hz */ + #define SP_EMMC_CONFIG_CLKFREQHZ_CLKFREQHZ_Pos (0UL) /*!< Position of CLKFREQHZ field. */ + #define SP_EMMC_CONFIG_CLKFREQHZ_CLKFREQHZ_Msk \ + (0xFFFFFFFFUL << SP_EMMC_CONFIG_CLKFREQHZ_CLKFREQHZ_Pos) \ + /*!< Bit mask of + * CLKFREQHZ field.*/ + +/* SP_EMMC_CONFIG_BUSWIDTH: SEMMC Bus width */ + #define SP_EMMC_CONFIG_BUSWIDTH_ResetValue (0x00000001UL) /*!< Reset value of BUSWIDTH register. */ + +/* BUSWIDTH @Bits 0..3 : Bus width SEMMC will use for data transfers */ + #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Pos (0UL) /*!< Position of BUSWIDTH field. */ + #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Msk \ + (0xFUL << SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Pos) \ + /*!< Bit mask of BUSWIDTH field.*/ + #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Min (0x1UL) /*!< Min enumerator value of BUSWIDTH field. */ + #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_Max (0x8UL) /*!< Max enumerator value of BUSWIDTH field. */ + #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_ONELANE (0x1UL) /*!< Data transfers will use one lane */ + #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_FOURLANES (0x4UL) /*!< Data transfers will use four lanes */ + #define SP_EMMC_CONFIG_BUSWIDTH_BUSWIDTH_EIGHTLANES (0x8UL) /*!< Data transfers will use eigth lanes */ + +/* SP_EMMC_CONFIG_NUMRETRIES: Number of retries for a transaction */ + #define SP_EMMC_CONFIG_NUMRETRIES_ResetValue (0x00000000UL) /*!< Reset value of NUMRETRIES register. */ + +/* NUMRETRIES @Bits 0..31 : Number of retries for a transaction */ + #define SP_EMMC_CONFIG_NUMRETRIES_NUMRETRIES_Pos (0UL) /*!< Position of NUMRETRIES field. */ + #define SP_EMMC_CONFIG_NUMRETRIES_NUMRETRIES_Msk \ + (0xFFFFFFFFUL << SP_EMMC_CONFIG_NUMRETRIES_NUMRETRIES_Pos) \ + /*!< Bit mask of + * NUMRETRIES field.*/ + +/* SP_EMMC_CONFIG_READDELAY: Number of FLPR clock cycles to offset for data sampling point */ + #define SP_EMMC_CONFIG_READDELAY_ResetValue (0x00000000UL) /*!< Reset value of READDELAY register. */ + +/* READDELAY @Bits 0..31 : Number of FLPR clock cycles to offset for data sampling point */ + #define SP_EMMC_CONFIG_READDELAY_READDELAY_Pos (0UL) /*!< Position of READDELAY field. */ + #define SP_EMMC_CONFIG_READDELAY_READDELAY_Msk \ + (0xFFFFFFFFUL << SP_EMMC_CONFIG_READDELAY_READDELAY_Pos) \ + /*!< Bit mask of + * READDELAY field.*/ + +/* ================================================= Struct SP_EMMC_COMMAND ================================================== */ +/** + * @brief COMMAND [SP_EMMC_COMMAND] SEMMC command descriptor + */ +typedef struct +{ + __IOM uint32_t CMD; /*!< (@ 0x00000000) Command */ + __IOM uint32_t ARG; /*!< (@ 0x00000004) Command argument */ + __IOM uint32_t RESPONSEADDR; /*!< (@ 0x00000008) Command response address */ + __IOM uint32_t RESPONSE[4]; /*!< (@ 0x0000000C) Command response */ + __IOM uint32_t SPISADDR; /*!< (@ 0x0000001C) SPI slave instance address */ +} NRF_SP_EMMC_COMMAND_Type; /*!< Size = 32 (0x020) */ + +/* SP_EMMC_COMMAND_CMD: Command */ + #define SP_EMMC_COMMAND_CMD_ResetValue (0x00000000UL) /*!< Reset value of CMD register. */ + +/* IDX @Bits 0..15 : Command index */ + #define SP_EMMC_COMMAND_CMD_IDX_Pos (0UL) /*!< Position of IDX field. */ + #define SP_EMMC_COMMAND_CMD_IDX_Msk (0xFFFFUL << SP_EMMC_COMMAND_CMD_IDX_Pos) /*!< Bit mask of IDX field. */ + +/* RESPTYPE @Bits 16..23 : Response type */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_Pos (16UL) /*!< Position of RESPTYPE field. */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_Msk (0xFFUL << SP_EMMC_COMMAND_CMD_RESPTYPE_Pos) /*!< Bit mask of RESPTYPE field. */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_Min (0x0UL) /*!< Min enumerator value of RESPTYPE field. */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_Max (0x6UL) /*!< Max enumerator value of RESPTYPE field. */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_NONE (0x00UL) /*!< No response */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_R1 (0x01UL) /*!< R1 response */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_R1B (0x02UL) /*!< R1 response with busy signal on DATA0 line */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_R2 (0x03UL) /*!< R2 response */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_R3 (0x04UL) /*!< R3 response */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_R4 (0x05UL) /*!< R4 response */ + #define SP_EMMC_COMMAND_CMD_RESPTYPE_R5 (0x06UL) /*!< R5 response */ + +/* RESPPROC @Bits 24..31 : Response process */ + #define SP_EMMC_COMMAND_CMD_RESPPROC_Pos (24UL) /*!< Position of RESPPROC field. */ + #define SP_EMMC_COMMAND_CMD_RESPPROC_Msk (0xFFUL << SP_EMMC_COMMAND_CMD_RESPPROC_Pos) /*!< Bit mask of RESPPROC field. */ + #define SP_EMMC_COMMAND_CMD_RESPPROC_Min (0x0UL) /*!< Min enumerator value of RESPPROC field. */ + #define SP_EMMC_COMMAND_CMD_RESPPROC_Max (0x2UL) /*!< Max enumerator value of RESPPROC field. */ + #define SP_EMMC_COMMAND_CMD_RESPPROC_PROCESS (0x00UL) /*!< Process the response */ + #define SP_EMMC_COMMAND_CMD_RESPPROC_IGNORE (0x01UL) /*!< Ignore the response */ + +/* SP_EMMC_COMMAND_ARG: Command argument */ + #define SP_EMMC_COMMAND_ARG_ResetValue (0x00000000UL) /*!< Reset value of ARG register. */ + +/* ARG @Bits 0..31 : Argument */ + #define SP_EMMC_COMMAND_ARG_ARG_Pos (0UL) /*!< Position of ARG field. */ + #define SP_EMMC_COMMAND_ARG_ARG_Msk (0xFFFFFFFFUL << SP_EMMC_COMMAND_ARG_ARG_Pos) /*!< Bit mask of ARG field. */ + +/* SP_EMMC_COMMAND_RESPONSEADDR: Command response address */ + #define SP_EMMC_COMMAND_RESPONSEADDR_ResetValue (0x00000000UL) /*!< Reset value of RESPONSEADDR register. */ + +/* RESPONSEADDR @Bits 0..31 : Memory address to which SEMMC will copy the response for a command This address is assumed to be + * the beginning of an array of 4 32 bit words. Meant to be used for a pointer in red code */ + + #define SP_EMMC_COMMAND_RESPONSEADDR_RESPONSEADDR_Pos (0UL) /*!< Position of RESPONSEADDR field. */ + #define SP_EMMC_COMMAND_RESPONSEADDR_RESPONSEADDR_Msk \ + (0xFFFFFFFFUL << SP_EMMC_COMMAND_RESPONSEADDR_RESPONSEADDR_Pos) \ + /*!< Bit + * mask of RESPONSEADDR field.*/ +/* SP_EMMC_COMMAND_RESPONSE: Command response */ + #define SP_EMMC_COMMAND_RESPONSE_MaxCount (4UL) /*!< Max size of RESPONSE[4] array. */ + #define SP_EMMC_COMMAND_RESPONSE_MaxIndex (3UL) /*!< Max index of RESPONSE[4] array. */ + #define SP_EMMC_COMMAND_RESPONSE_MinIndex (0UL) /*!< Min index of RESPONSE[4] array. */ + #define SP_EMMC_COMMAND_RESPONSE_ResetValue (0x00000000UL) /*!< Reset value of RESPONSE[4] register. */ + +/* RESPONSE @Bits 0..31 : (unspecified) */ + #define SP_EMMC_COMMAND_RESPONSE_RESPONSE_Pos (0UL) /*!< Position of RESPONSE field. */ + #define SP_EMMC_COMMAND_RESPONSE_RESPONSE_Msk \ + (0xFFFFFFFFUL << SP_EMMC_COMMAND_RESPONSE_RESPONSE_Pos) \ + /*!< Bit mask of + * RESPONSE field.*/ + +/* SP_EMMC_COMMAND_SPISADDR: SPI slave instance address */ + #define SP_EMMC_COMMAND_SPISADDR_ResetValue (0x00000000UL) /*!< Reset value of SPISADDR register. */ + +/* SPISADDR @Bits 0..31 : Memory address that SEMMC will use to configure a SPI slave to process responses from eMMC This + * address is meant to be used for a pointer in red code */ + + #define SP_EMMC_COMMAND_SPISADDR_SPISADDR_Pos (0UL) /*!< Position of SPISADDR field. */ + #define SP_EMMC_COMMAND_SPISADDR_SPISADDR_Msk \ + (0xFFFFFFFFUL << SP_EMMC_COMMAND_SPISADDR_SPISADDR_Pos) \ + /*!< Bit mask of + * SPISADDR field.*/ + +/* =================================================== Struct SP_EMMC_DATA =================================================== */ +/** + * @brief DATA [SP_EMMC_DATA] SEMMC data transfer descriptor + */ +typedef struct +{ + __IOM uint32_t BUFFERADDR; /*!< (@ 0x00000000) Address of the data buffer */ + __IOM uint32_t BLOCKSIZE; /*!< (@ 0x00000004) Block size */ + __IOM uint32_t BLOCKNUM; /*!< (@ 0x00000008) Number of blocks to transfer */ +} NRF_SP_EMMC_DATA_Type; /*!< Size = 12 (0xC) */ + +/* SP_EMMC_DATA_BUFFERADDR: Address of the data buffer */ + #define SP_EMMC_DATA_BUFFERADDR_ResetValue (0x00000000UL) /*!< Reset value of BUFFERADDR register. */ + +/* BUFFERADDR @Bits 0..31 : Address of the data buffer */ + #define SP_EMMC_DATA_BUFFERADDR_BUFFERADDR_Pos (0UL) /*!< Position of BUFFERADDR field. */ + #define SP_EMMC_DATA_BUFFERADDR_BUFFERADDR_Msk \ + (0xFFFFFFFFUL << SP_EMMC_DATA_BUFFERADDR_BUFFERADDR_Pos) \ + /*!< Bit mask of + * BUFFERADDR field.*/ +/* SP_EMMC_DATA_BLOCKSIZE: Block size */ + #define SP_EMMC_DATA_BLOCKSIZE_ResetValue (0x00000200UL) /*!< Reset value of BLOCKSIZE register. */ + +/* BLOCKSIZE @Bits 0..31 : Block size */ + #define SP_EMMC_DATA_BLOCKSIZE_BLOCKSIZE_Pos (0UL) /*!< Position of BLOCKSIZE field. */ + #define SP_EMMC_DATA_BLOCKSIZE_BLOCKSIZE_Msk \ + (0xFFFFFFFFUL << SP_EMMC_DATA_BLOCKSIZE_BLOCKSIZE_Pos) \ + /*!< Bit mask of BLOCKSIZE + * field.*/ + +/* SP_EMMC_DATA_BLOCKNUM: Number of blocks to transfer */ + #define SP_EMMC_DATA_BLOCKNUM_ResetValue (0x00000001UL) /*!< Reset value of BLOCKNUM register. */ + +/* BLOCKNUM @Bits 0..31 : Number of blocks to transfer */ + #define SP_EMMC_DATA_BLOCKNUM_BLOCKNUM_Pos (0UL) /*!< Position of BLOCKNUM field. */ + #define SP_EMMC_DATA_BLOCKNUM_BLOCKNUM_Msk (0xFFFFFFFFUL << SP_EMMC_DATA_BLOCKNUM_BLOCKNUM_Pos) /*!< Bit mask of BLOCKNUM + * field.*/ + +/* ================================================== Struct SP_EMMC_STATUS ================================================== */ +/** + * @brief STATUS [SP_EMMC_STATUS] SEMMC status + */ +typedef struct +{ + __IOM uint32_t STATUS; /*!< (@ 0x00000000) SEMMC status register */ +} NRF_SP_EMMC_STATUS_Type; /*!< Size = 4 (0x004) */ + +/* SP_EMMC_STATUS_STATUS: SEMMC status register */ + #define SP_EMMC_STATUS_STATUS_ResetValue (0x00000000UL) /*!< Reset value of STATUS register. */ + +/* CMDTIMEOUT @Bit 0 : Command timeout */ + #define SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Pos (0UL) /*!< Position of CMDTIMEOUT field. */ + #define SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Msk (0x1UL << SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Pos) /*!< Bit mask of CMDTIMEOUT + * field.*/ + +/* CMDCRCERROR @Bit 1 : CRC Error in the command response */ + #define SP_EMMC_STATUS_STATUS_CMDCRCERROR_Pos (1UL) /*!< Position of CMDCRCERROR field. */ + #define SP_EMMC_STATUS_STATUS_CMDCRCERROR_Msk (0x1UL << SP_EMMC_STATUS_STATUS_CMDCRCERROR_Pos) /*!< Bit mask of CMDCRCERROR + * field.*/ + +/* DATACRCERROR @Bit 2 : CRC Error during data transfer (read) */ + #define SP_EMMC_STATUS_STATUS_DATACRCERROR_Pos (2UL) /*!< Position of DATACRCERROR field. */ + #define SP_EMMC_STATUS_STATUS_DATACRCERROR_Msk (0x1UL << SP_EMMC_STATUS_STATUS_DATACRCERROR_Pos) /*!< Bit mask of DATACRCERROR + * field.*/ + +/* RETRYEXCEEDED @Bit 3 : Exceeded number in NUMRETRIES */ + #define SP_EMMC_STATUS_STATUS_RETRYEXCEEDED_Pos (3UL) /*!< Position of RETRYEXCEEDED field. */ + #define SP_EMMC_STATUS_STATUS_RETRYEXCEEDED_Msk (0x1UL << SP_EMMC_STATUS_STATUS_RETRYEXCEEDED_Pos) /*!< Bit mask of + * RETRYEXCEEDED field.*/ + +/* PROTOCOLERR @Bit 4 : Protocol error, generic error response */ + #define SP_EMMC_STATUS_STATUS_PROTOCOLERR_Pos (4UL) /*!< Position of PROTOCOLERR field. */ + #define SP_EMMC_STATUS_STATUS_PROTOCOLERR_Msk (0x1UL << SP_EMMC_STATUS_STATUS_PROTOCOLERR_Pos) /*!< Bit mask of PROTOCOLERR + * field.*/ + +/* ================================================== Struct SP_EMMC_SPSYNC ================================================== */ +/** + * @brief SPSYNC [SP_EMMC_SPSYNC] Registers used to acknowledge API function calls + */ +typedef struct +{ + __IOM uint32_t AUX[6]; /*!< (@ 0x00000000) Auxiliary registers for XSB macro call handshaking */ +} NRF_SP_EMMC_SPSYNC_Type; /*!< Size = 24 (0x018) */ + +/* SP_EMMC_SPSYNC_AUX: Auxiliary registers for XSB macro call handshaking */ + #define SP_EMMC_SPSYNC_AUX_MaxCount (6UL) /*!< Max size of AUX[6] array. */ + #define SP_EMMC_SPSYNC_AUX_MaxIndex (5UL) /*!< Max index of AUX[6] array. */ + #define SP_EMMC_SPSYNC_AUX_MinIndex (0UL) /*!< Min index of AUX[6] array. */ + #define SP_EMMC_SPSYNC_AUX_ResetValue (0x00000000UL) /*!< Reset value of AUX[6] register. */ + +/* AUX @Bits 0..31 : Auxiliary register */ + #define SP_EMMC_SPSYNC_AUX_AUX_Pos (0UL) /*!< Position of AUX field. */ + #define SP_EMMC_SPSYNC_AUX_AUX_Msk (0xFFFFFFFFUL << SP_EMMC_SPSYNC_AUX_AUX_Pos) /*!< Bit mask of AUX field. */ + +/* ===================================================== Struct SP_EMMC ====================================================== */ +/** + * @brief Soft peripheral eMMC + */ +typedef struct /*!< SP_EMMC Structure */ +{ + __OM uint32_t TASKS_START; /*!< (@ 0x00000000) Trigger this task to send a command (which starts a + * data transfer, if applicable)*/ + __OM uint32_t TASKS_RESET; /*!< (@ 0x00000004) Trigger this task to reset SEMMC to UNINITIALIZED + * state*/ + __IOM uint32_t SUBSCRIBE_START; /*!< (@ 0x00000008) Subscribe configuration for task START */ + __IOM uint32_t SUBSCRIBE_RESET; /*!< (@ 0x0000000C) Subscribe configuration for task RESET */ + __IOM uint32_t EVENTS_XFERCOMPLETE; /*!< (@ 0x00000010) This event signals that SEMMC has completed a command + * or transfer (if applicable)*/ + __IOM uint32_t EVENTS_ABORTED; /*!< (@ 0x00000014) This event signals that SEMMC has aborted in the middle + * of a command/transfer or has timed out*/ + __IOM uint32_t EVENTS_READYTOTRANSFER; /*!< (@ 0x00000018) This event signals that SEMMC is ready to start a + * transfer*/ + __IOM uint32_t PUBLISH_XFERCOMPLETE; /*!< (@ 0x0000001C) Publish configuration for event XFERCOMPLETE */ + __IOM uint32_t PUBLISH_ABORTED; /*!< (@ 0x00000020) Publish configuration for event ABORTED */ + __IOM uint32_t PUBLISH_READYTOTRANSFER; /*!< (@ 0x00000024) Publish configuration for event READYTOTRANSFER */ + __IOM uint32_t INTEN; /*!< (@ 0x00000028) Enable or disable interrupt */ + __IOM uint32_t ENABLE; /*!< (@ 0x0000002C) Enable the SEMMC peripheral */ + __IOM NRF_SP_EMMC_CONFIG_Type CONFIG; /*!< (@ 0x00000030) SEMMC configuration */ + __IOM NRF_SP_EMMC_COMMAND_Type COMMAND; /*!< (@ 0x00000044) SEMMC command descriptor */ + __IOM NRF_SP_EMMC_DATA_Type DATA; /*!< (@ 0x00000064) SEMMC data transfer descriptor */ + __IOM NRF_SP_EMMC_STATUS_Type STATUS; /*!< (@ 0x00000070) SEMMC status */ + __IOM NRF_SP_EMMC_SPSYNC_Type SPSYNC; /*!< (@ 0x00000074) Registers used to acknowledge API function calls */ +} NRF_SP_EMMC_Type; /*!< Size = 140 (0x08C) */ + +/* SP_EMMC_TASKS_START: Trigger this task to send a command (which starts a data transfer, if applicable) */ + #define SP_EMMC_TASKS_START_ResetValue (0x00000000UL) /*!< Reset value of TASKS_START register. */ + +/* TASKS_START @Bit 0 : Trigger this task to send a command (which starts a data transfer, if applicable) */ + #define SP_EMMC_TASKS_START_TASKS_START_Pos (0UL) /*!< Position of TASKS_START field. */ + #define SP_EMMC_TASKS_START_TASKS_START_Msk (0x1UL << SP_EMMC_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START + * field.*/ + #define SP_EMMC_TASKS_START_TASKS_START_Min (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + #define SP_EMMC_TASKS_START_TASKS_START_Max (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + #define SP_EMMC_TASKS_START_TASKS_START_Trigger (0x1UL) /*!< Trigger task */ + +/* SP_EMMC_TASKS_RESET: Trigger this task to reset SEMMC to UNINITIALIZED state */ + #define SP_EMMC_TASKS_RESET_ResetValue (0x00000000UL) /*!< Reset value of TASKS_RESET register. */ + +/* TASKS_RESET @Bit 0 : Trigger this task to reset SEMMC to UNINITIALIZED state */ + #define SP_EMMC_TASKS_RESET_TASKS_RESET_Pos (0UL) /*!< Position of TASKS_RESET field. */ + #define SP_EMMC_TASKS_RESET_TASKS_RESET_Msk (0x1UL << SP_EMMC_TASKS_RESET_TASKS_RESET_Pos) /*!< Bit mask of TASKS_RESET + * field.*/ + #define SP_EMMC_TASKS_RESET_TASKS_RESET_Min (0x1UL) /*!< Min enumerator value of TASKS_RESET field. */ + #define SP_EMMC_TASKS_RESET_TASKS_RESET_Max (0x1UL) /*!< Max enumerator value of TASKS_RESET field. */ + #define SP_EMMC_TASKS_RESET_TASKS_RESET_Trigger (0x1UL) /*!< Trigger task */ + +/* SP_EMMC_SUBSCRIBE_START: Subscribe configuration for task START */ + #define SP_EMMC_SUBSCRIBE_START_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_START register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task START will subscribe to */ + #define SP_EMMC_SUBSCRIBE_START_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SP_EMMC_SUBSCRIBE_START_CHIDX_Msk (0xFFUL << SP_EMMC_SUBSCRIBE_START_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SP_EMMC_SUBSCRIBE_START_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SP_EMMC_SUBSCRIBE_START_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SP_EMMC_SUBSCRIBE_START_EN_Pos (31UL) /*!< Position of EN field. */ + #define SP_EMMC_SUBSCRIBE_START_EN_Msk (0x1UL << SP_EMMC_SUBSCRIBE_START_EN_Pos) /*!< Bit mask of EN field. */ + #define SP_EMMC_SUBSCRIBE_START_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SP_EMMC_SUBSCRIBE_START_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SP_EMMC_SUBSCRIBE_START_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SP_EMMC_SUBSCRIBE_START_EN_Enabled (0x1UL) /*!< Enable subscription */ + +/* SP_EMMC_SUBSCRIBE_RESET: Subscribe configuration for task RESET */ + #define SP_EMMC_SUBSCRIBE_RESET_ResetValue (0x00000000UL) /*!< Reset value of SUBSCRIBE_RESET register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that task RESET will subscribe to */ + #define SP_EMMC_SUBSCRIBE_RESET_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SP_EMMC_SUBSCRIBE_RESET_CHIDX_Msk (0xFFUL << SP_EMMC_SUBSCRIBE_RESET_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SP_EMMC_SUBSCRIBE_RESET_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SP_EMMC_SUBSCRIBE_RESET_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SP_EMMC_SUBSCRIBE_RESET_EN_Pos (31UL) /*!< Position of EN field. */ + #define SP_EMMC_SUBSCRIBE_RESET_EN_Msk (0x1UL << SP_EMMC_SUBSCRIBE_RESET_EN_Pos) /*!< Bit mask of EN field. */ + #define SP_EMMC_SUBSCRIBE_RESET_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SP_EMMC_SUBSCRIBE_RESET_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SP_EMMC_SUBSCRIBE_RESET_EN_Disabled (0x0UL) /*!< Disable subscription */ + #define SP_EMMC_SUBSCRIBE_RESET_EN_Enabled (0x1UL) /*!< Enable subscription */ + +/* SP_EMMC_EVENTS_XFERCOMPLETE: This event signals that SEMMC has completed a command or transfer (if applicable) */ + #define SP_EMMC_EVENTS_XFERCOMPLETE_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_XFERCOMPLETE register. */ + +/* EVENTS_XFERCOMPLETE @Bit 0 : This event signals that SEMMC has completed a command or transfer (if applicable) */ + #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Pos (0UL) /*!< Position of EVENTS_XFERCOMPLETE field. */ + #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Msk \ + (0x1UL << SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Pos) + /*!< Bit mask of EVENTS_XFERCOMPLETE field.*/ + #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Min (0x0UL) /*!< Min enumerator value of EVENTS_XFERCOMPLETE field. */ + #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Max (0x1UL) /*!< Max enumerator value of EVENTS_XFERCOMPLETE field. */ + #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_NotGenerated (0x0UL) /*!< Event not generated */ + #define SP_EMMC_EVENTS_XFERCOMPLETE_EVENTS_XFERCOMPLETE_Generated (0x1UL) /*!< Event generated */ + +/* SP_EMMC_EVENTS_ABORTED: This event signals that SEMMC has aborted in the middle of a command/transfer or has timed out */ + #define SP_EMMC_EVENTS_ABORTED_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_ABORTED register. */ + +/* EVENTS_ABORTED @Bit 0 : This event signals that SEMMC has aborted in the middle of a command/transfer or has timed out */ + #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Pos (0UL) /*!< Position of EVENTS_ABORTED field. */ + #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Msk \ + (0x1UL << SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Pos) \ + /*!< Bit mask of + * EVENTS_ABORTED field.*/ + #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Min (0x0UL) /*!< Min enumerator value of EVENTS_ABORTED field. */ + #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Max (0x1UL) /*!< Max enumerator value of EVENTS_ABORTED field. */ + #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_NotGenerated (0x0UL) /*!< Event not generated */ + #define SP_EMMC_EVENTS_ABORTED_EVENTS_ABORTED_Generated (0x1UL) /*!< Event generated */ + +/* SP_EMMC_EVENTS_READYTOTRANSFER: This event signals that SEMMC is ready to start a transfer */ + #define SP_EMMC_EVENTS_READYTOTRANSFER_ResetValue (0x00000000UL) /*!< Reset value of EVENTS_READYTOTRANSFER register. */ + +/* EVENTS_READYTOTRANSFER @Bit 0 : This event signals that SEMMC is ready to start a transfer */ + #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Pos (0UL) /*!< Position of EVENTS_READYTOTRANSFER field. */ + #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Msk \ + (0x1UL << SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Pos) + /*!< Bit mask of EVENTS_READYTOTRANSFER field.*/ + #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Min (0x0UL) /*!< Min enumerator value of EVENTS_READYTOTRANSFER + * field.*/ + #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Max (0x1UL) /*!< Max enumerator value of EVENTS_READYTOTRANSFER + * field.*/ + #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_NotGenerated (0x0UL) /*!< Event not generated */ + #define SP_EMMC_EVENTS_READYTOTRANSFER_EVENTS_READYTOTRANSFER_Generated (0x1UL) /*!< Event generated */ + +/* SP_EMMC_PUBLISH_XFERCOMPLETE: Publish configuration for event XFERCOMPLETE */ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_XFERCOMPLETE register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event XFERCOMPLETE will publish to */ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Msk (0xFFUL << SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Pos) /*!< Bit mask of CHIDX + * field.*/ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Pos (31UL) /*!< Position of EN field. */ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Msk (0x1UL << SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Pos) /*!< Bit mask of EN field. */ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SP_EMMC_PUBLISH_XFERCOMPLETE_EN_Enabled (0x1UL) /*!< Enable publishing */ + +/* SP_EMMC_PUBLISH_ABORTED: Publish configuration for event ABORTED */ + #define SP_EMMC_PUBLISH_ABORTED_ResetValue (0x00000000UL) /*!< Reset value of PUBLISH_ABORTED register. */ + +/* CHIDX @Bits 0..7 : DPPI channel that event ABORTED will publish to */ + #define SP_EMMC_PUBLISH_ABORTED_CHIDX_Pos (0UL) /*!< Position of CHIDX field. */ + #define SP_EMMC_PUBLISH_ABORTED_CHIDX_Msk (0xFFUL << SP_EMMC_PUBLISH_ABORTED_CHIDX_Pos) /*!< Bit mask of CHIDX field. */ + #define SP_EMMC_PUBLISH_ABORTED_CHIDX_Min (0x00UL) /*!< Min value of CHIDX field. */ + #define SP_EMMC_PUBLISH_ABORTED_CHIDX_Max (0xFFUL) /*!< Max size of CHIDX field. */ + +/* EN @Bit 31 : (unspecified) */ + #define SP_EMMC_PUBLISH_ABORTED_EN_Pos (31UL) /*!< Position of EN field. */ + #define SP_EMMC_PUBLISH_ABORTED_EN_Msk (0x1UL << SP_EMMC_PUBLISH_ABORTED_EN_Pos) /*!< Bit mask of EN field. */ + #define SP_EMMC_PUBLISH_ABORTED_EN_Min (0x0UL) /*!< Min enumerator value of EN field. */ + #define SP_EMMC_PUBLISH_ABORTED_EN_Max (0x1UL) /*!< Max enumerator value of EN field. */ + #define SP_EMMC_PUBLISH_ABORTED_EN_Disabled (0x0UL) /*!< Disable publishing */ + #define SP_EMMC_PUBLISH_ABORTED_EN_Enabled (0x1UL) /*!< Enable publishing */ + +/* SP_EMMC_INTEN: Enable or disable interrupt */ + #define SP_EMMC_INTEN_ResetValue (0x00000000UL) /*!< Reset value of INTEN register. */ + +/* XFERCOMPLETE @Bit 0 : Enable or disable interrupt for event XFERCOMPLETE */ + #define SP_EMMC_INTEN_XFERCOMPLETE_Pos (0UL) /*!< Position of XFERCOMPLETE field. */ + #define SP_EMMC_INTEN_XFERCOMPLETE_Msk (0x1UL << SP_EMMC_INTEN_XFERCOMPLETE_Pos) /*!< Bit mask of XFERCOMPLETE field. */ + #define SP_EMMC_INTEN_XFERCOMPLETE_Min (0x0UL) /*!< Min enumerator value of XFERCOMPLETE field. */ + #define SP_EMMC_INTEN_XFERCOMPLETE_Max (0x1UL) /*!< Max enumerator value of XFERCOMPLETE field. */ + #define SP_EMMC_INTEN_XFERCOMPLETE_Disabled (0x0UL) /*!< Disable */ + #define SP_EMMC_INTEN_XFERCOMPLETE_Enabled (0x1UL) /*!< Enable */ + +/* ABORTED @Bit 1 : Enable or disable interrupt for event ABORTED */ + #define SP_EMMC_INTEN_ABORTED_Pos (1UL) /*!< Position of ABORTED field. */ + #define SP_EMMC_INTEN_ABORTED_Msk (0x1UL << SP_EMMC_INTEN_ABORTED_Pos) /*!< Bit mask of ABORTED field. */ + #define SP_EMMC_INTEN_ABORTED_Min (0x0UL) /*!< Min enumerator value of ABORTED field. */ + #define SP_EMMC_INTEN_ABORTED_Max (0x1UL) /*!< Max enumerator value of ABORTED field. */ + #define SP_EMMC_INTEN_ABORTED_Disabled (0x0UL) /*!< Disable */ + #define SP_EMMC_INTEN_ABORTED_Enabled (0x1UL) /*!< Enable */ + +/* READYTOTRANSFER @Bit 2 : Enable or disable interrupt for event READYTOTRANSFER */ + #define SP_EMMC_INTEN_READYTOTRANSFER_Pos (2UL) /*!< Position of READYTOTRANSFER field. */ + #define SP_EMMC_INTEN_READYTOTRANSFER_Msk (0x1UL << SP_EMMC_INTEN_READYTOTRANSFER_Pos) /*!< Bit mask of READYTOTRANSFER + * field.*/ + #define SP_EMMC_INTEN_READYTOTRANSFER_Min (0x0UL) /*!< Min enumerator value of READYTOTRANSFER field. */ + #define SP_EMMC_INTEN_READYTOTRANSFER_Max (0x1UL) /*!< Max enumerator value of READYTOTRANSFER field. */ + #define SP_EMMC_INTEN_READYTOTRANSFER_Disabled (0x0UL) /*!< Disable */ + #define SP_EMMC_INTEN_READYTOTRANSFER_Enabled (0x1UL) /*!< Enable */ + +/* SP_EMMC_ENABLE: Enable the SEMMC peripheral */ + #define SP_EMMC_ENABLE_ResetValue (0x00000000UL) /*!< Reset value of ENABLE register. */ + +/* ENABLE @Bit 0 : Enable or disable SEMMC */ + #define SP_EMMC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ + #define SP_EMMC_ENABLE_ENABLE_Msk (0x1UL << SP_EMMC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + #define SP_EMMC_ENABLE_ENABLE_Min (0x0UL) /*!< Min enumerator value of ENABLE field. */ + #define SP_EMMC_ENABLE_ENABLE_Max (0x1UL) /*!< Max enumerator value of ENABLE field. */ + #define SP_EMMC_ENABLE_ENABLE_Disabled (0x0UL) /*!< Disable SEMMC */ + #define SP_EMMC_ENABLE_ENABLE_Enabled (0x1UL) /*!< Enable SEMMC */ + +#endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ + +#endif /* NRF_SP_EMMC_H__ */ diff --git a/softperipheral/sEMMC/src/nrf_semmc.c b/softperipheral/sEMMC/src/nrf_semmc.c new file mode 100644 index 0000000000..5671e7d4f2 --- /dev/null +++ b/softperipheral/sEMMC/src/nrf_semmc.c @@ -0,0 +1,601 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#include +#include + +#if defined(NRF_SEMMC_ENABLED) && (NRF_SEMMC_ENABLED == 1) +#include +#include +#include +#include + +#if defined(NRF54L20_ENGA_XXAA) || defined(NRF54LM20A_ENGA_XXAA) + +#include +#endif + +#ifndef EXCLUDE_SP_FW +#define EXCLUDE_SP_FW 0 +#endif +#if EXCLUDE_SP_FW +static void * nvm_fw_addr = (uint8_t *)SP_VPR_FIRMWARE_ADDRESS; +#else +#include +const void * nvm_fw_addr = (const void *)semmc_firmware_bin; +#endif + +#define NRFX_LOG_MODULE EMMC +#include +#include +#include + +/******************************* NRF_HAL_EMMC_H START ************************/ + +#define SOFTPERIPHERAL_EMMC (1) +#if SOFTPERIPHERAL_EMMC +#define NRF_EMMC_Type NRF_SP_EMMC_Type +#else +#define NRF_EMMC_Type NRF_EMMC_Type +#endif + +static uint32_t m_task_count = 1; + +typedef struct +{ + void * p_hw_instance; + nrf_semmc_event_handler_t handler; + void * p_context; + nrf_semmc_event_t evt; + nrfx_drv_state_t state; + nrf_semmc_error_t xfer_err; + + volatile bool transfer_in_progress; + volatile bool prepared_pending; + + struct + { + nrf_emmc_config_t config; + } conf; +} emmc_control_block_t; + +typedef struct +{ + nrf_semmc_cmd_desc_t * p_cmd; + nrf_semmc_transfer_desc_t * p_transfer; + uint8_t drv_inst_idx; +} nrf_semmc_transaction_data_t; + +#define NRF_SEMMC_ENABLED_COUNT (1) +static emmc_control_block_t m_cb[NRF_SEMMC_ENABLED_COUNT] = +{{.state = NRFX_DRV_STATE_UNINITIALIZED}}; +static volatile nrf_semmc_transaction_data_t m_current_xfer; + +NRF_STATIC_INLINE void sp_handshake_set(void * p_reg, uint32_t val, uint8_t idx) +{ + nrf_emmc_handshake_set((NRF_EMMC_Type *)p_reg, val, idx); +} + +NRF_STATIC_INLINE uint32_t sp_handshake_get(void * p_reg, uint8_t idx) +{ + return nrf_emmc_handshake_get((NRF_EMMC_Type const *)p_reg, idx); +} + +nrf_semmc_error_t nrf_semmc_init(nrf_semmc_t const * p_semmc, + nrf_semmc_event_handler_t handler, + void * p_context) +{ + NRFX_ASSERT(p_semmc); + + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + + if (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED) + { + return NRF_SEMMC_ERROR_BUSY; + } + + p_cb->transfer_in_progress = false; + p_cb->prepared_pending = false; + + const softperipheral_metadata_t * meta = (const softperipheral_metadata_t *)nvm_fw_addr; +#ifndef UNIT_TEST + memset((void *)p_semmc->p_reg, 0, sizeof(NRF_SP_EMMC_Type)); + + // Set ENABLE to 1, expect it to become 0 when ready. + nrf_emmc_enable((NRF_EMMC_Type *)p_semmc->p_reg); +#endif + uint32_t vpr_init_pc = (uint32_t)p_semmc->p_reg - meta->fw_shared_ram_addr_offset - + (meta->fw_code_size << 4); + // Copy firmware and start VPR. + if (meta->self_boot == 0) + { +#ifndef UNIT_TEST + memcpy((void *)vpr_init_pc, nvm_fw_addr, meta->fw_code_size << 4); +#endif + nrf_vpr_initpc_set(NRF_VPR, vpr_init_pc); + } + else + { + nrf_vpr_initpc_set(NRF_VPR, vpr_init_pc); + } + + nrf_vpr_cpurun_set(NRF_VPR, true); +#ifndef UNIT_TEST + while (nrf_emmc_enable_check((NRF_EMMC_Type *)p_semmc->p_reg) != false) + { + // Wait for peripheral to become ready to receive communication. + } +#endif + + // Store hardware instance and configuration + p_cb->p_hw_instance = p_semmc->p_reg; + p_cb->conf.config.ready_to_transfer = false; + + // Store handler and context + p_cb->handler = handler; + p_cb->p_context = p_context; + + NRFX_IRQ_PRIORITY_SET(SP_VPR_IRQn, 1); + + nrf_emmc_int_enable((NRF_EMMC_Type *)p_semmc->p_reg, + (NRF_EMMC_INT_XFERCOMPLETE_MASK | NRF_EMMC_INT_ABORTED_MASK | + NRF_EMMC_INT_READYTOTRANSFER_MASK)); + + p_cb->state = NRFX_DRV_STATE_INITIALIZED; + + return NRF_SEMMC_SUCCESS; +} + +bool nrf_semmc_init_check(const nrf_semmc_t * p_semmc) +{ + NRFX_ASSERT(p_semmc); + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + + return (p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); +} + +void nrf_semmc_uninit(nrf_semmc_t const * p_semmc) +{ + NRFX_ASSERT(p_semmc); + + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + + //Turn off VPR + if (p_cb->state == NRFX_DRV_STATE_POWERED_ON) + { + nrf_semmc_disable(p_semmc); + } + + NRFX_ASSERT(p_cb->state != NRFX_DRV_STATE_UNINITIALIZED); + + // Stop VPR. + nrf_vpr_cpurun_set(NRF_VPR, false); + + // Reset VPR. + nrf_vpr_debugif_dmcontrol_mask_set( + NRF_VPR, (VPR_DEBUGIF_DMCONTROL_NDMRESET_Active << VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos | + VPR_DEBUGIF_DMCONTROL_DMACTIVE_Enabled << VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos)); + nrf_vpr_debugif_dmcontrol_mask_set( + NRF_VPR, (VPR_DEBUGIF_DMCONTROL_NDMRESET_Inactive << VPR_DEBUGIF_DMCONTROL_NDMRESET_Pos | + VPR_DEBUGIF_DMCONTROL_DMACTIVE_Disabled << VPR_DEBUGIF_DMCONTROL_DMACTIVE_Pos)); + + p_cb->state = NRFX_DRV_STATE_UNINITIALIZED; +} + +nrf_semmc_error_t nrf_semmc_enable(nrf_semmc_t const * p_semmc) +{ + NRFX_ASSERT(p_semmc); + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + + if (p_cb->state != NRFX_DRV_STATE_INITIALIZED) + { + return NRF_SEMMC_ERROR_INVALID_STATE; + } + + nrf_emmc_enable((NRF_EMMC_Type *)p_cb->p_hw_instance); + + __ASB(p_cb->p_hw_instance); + + nrf_emmc_event_clear((NRF_EMMC_Type *)p_cb->p_hw_instance, NRF_EMMC_EVENT_XFERCOMPLETE); + nrf_emmc_event_clear((NRF_EMMC_Type *)p_cb->p_hw_instance, NRF_EMMC_EVENT_ABORTED); + nrf_emmc_event_clear((NRF_EMMC_Type *)p_cb->p_hw_instance, NRF_EMMC_EVENT_READYTOTRANSFER); + + NRFX_IRQ_ENABLE(SP_VPR_IRQn); + + p_cb->state = NRFX_DRV_STATE_POWERED_ON; + + return NRF_SEMMC_SUCCESS; +} + +nrf_semmc_error_t nrf_semmc_abort(nrf_semmc_t const * p_semmc) +{ + NRFX_ASSERT(p_semmc); + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + + if (p_cb->state == NRFX_DRV_STATE_UNINITIALIZED) + { + return NRF_SEMMC_ERROR_INVALID_STATE; + } + + p_cb->prepared_pending = false; + if (p_cb->transfer_in_progress) + { + __SSB(p_cb->p_hw_instance); + } + + return NRF_SEMMC_SUCCESS; +} + +nrf_semmc_error_t nrf_semmc_disable(nrf_semmc_t const * p_semmc) +{ + NRFX_ASSERT(p_semmc); + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + + if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) + { + return NRF_SEMMC_ERROR_INVALID_STATE; + } + + nrf_semmc_error_t err = nrf_semmc_abort(p_semmc); + if (err != NRF_SEMMC_SUCCESS) + { + return err; + } + + while (p_cb->transfer_in_progress) + {} + + NRFX_IRQ_DISABLE(SP_VPR_IRQn); + + nrf_emmc_disable((NRF_EMMC_Type *)p_cb->p_hw_instance); + + __ASB(p_cb->p_hw_instance); + + p_cb->state = NRFX_DRV_STATE_INITIALIZED; + + return NRF_SEMMC_SUCCESS; +} + +nrf_semmc_error_t nrf_semmc_cmd_common(emmc_control_block_t * p_cb, + nrf_semmc_t const * p_semmc, + nrf_semmc_cmd_desc_t * p_cmd, + nrf_semmc_config_t const * p_config, + nrf_semmc_transfer_desc_t * p_transfer, + size_t cmd_count + ) +{ + if (cmd_count > NRF_SEMMC_TRANSFERS_PER_REQUEST) + { + return NRF_SEMMC_ERROR_UNSUPPORTED; + } + + if (p_cb->state != NRFX_DRV_STATE_POWERED_ON) + { + return NRF_SEMMC_ERROR_INVALID_STATE; + } + + if (!p_cmd) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + if (!p_transfer) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + + // sEMMC config + uint32_t clkdiv = (uint32_t)SP_VPR_BASE_FREQ_HZ / p_config->clk_freq_hz; + //clkdiv must be an even number + if (clkdiv & 0x1) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + if (clkdiv < 4) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + p_cb->conf.config.clkfreqhz = p_config->clk_freq_hz; + if ((nrf_emmc_bus_width_t)p_config->bus_width > NRF_EMMC_BUS_WIDTH_4_LANES) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + else + { + p_cb->conf.config.bus_width = (nrf_emmc_bus_width_t)p_config->bus_width; + } + if (p_config->read_delay >= clkdiv) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + p_cb->conf.config.read_delay = p_config->read_delay; + if (p_config->spis_instance != NULL) + { + return NRF_SEMMC_ERROR_UNSUPPORTED; + } + nrf_emmc_config_set((NRF_EMMC_Type *)p_cb->p_hw_instance, &(p_cb->conf.config)); + + // Configure EMMC command + nrf_emmc_command_t emmc_cmd = {0}; + emmc_cmd.idx = p_cmd->cmd; + emmc_cmd.arg = p_cmd->arg; + + // Map response types + switch (p_cmd->resp_type) + { + case NRF_SEMMC_RESP_NONE: emmc_cmd.resp_type = NRF_EMMC_RESPONSE_NONE; break; + case NRF_SEMMC_RESP_R1: emmc_cmd.resp_type = NRF_EMMC_RESPONSE_R1; break; + case NRF_SEMMC_RESP_R1B: emmc_cmd.resp_type = NRF_EMMC_RESPONSE_R1B; break; + case NRF_SEMMC_RESP_R2: emmc_cmd.resp_type = NRF_EMMC_RESPONSE_R2; break; + case NRF_SEMMC_RESP_R3: emmc_cmd.resp_type = NRF_EMMC_RESPONSE_R3; break; + default: return NRF_SEMMC_ERROR_INVALID_PARAM; + } + + emmc_cmd.resp_proc = p_config->process_response; + emmc_cmd.resp_addr = (uint32_t)p_cmd->resp_buffer; + // Set command in hardware + nrf_emmc_command_set((NRF_EMMC_Type *)p_cb->p_hw_instance, &emmc_cmd); + + nrf_emmc_data_t emmc_data = {0}; + emmc_data.buffer_addr = (uint32_t)p_transfer->buffer; + emmc_data.block_size = p_transfer->block_size; + emmc_data.block_num = p_transfer->num_blocks; + + // Set data configuration in hardware + nrf_emmc_data_set((NRF_EMMC_Type *)p_cb->p_hw_instance, &emmc_data); + + __CSB(p_cb->p_hw_instance); + + // Store transaction data + m_current_xfer.drv_inst_idx = p_semmc->drv_inst_idx; + m_current_xfer.p_cmd = p_cmd; + m_current_xfer.p_transfer = p_transfer; + + return NRF_SEMMC_SUCCESS; +} + +nrf_semmc_error_t nrf_semmc_cmd(nrf_semmc_t const * p_semmc, + nrf_semmc_cmd_desc_t * p_cmd, + nrf_semmc_config_t const * p_config, + nrf_semmc_transfer_desc_t * p_transfer, + size_t cmd_count, + uint32_t flags) +{ + if (flags == NRF_SEMMC_FLAG_HOLD_XFER) + { + return nrf_semmc_cmd_prepare(p_semmc, p_cmd, p_config, p_transfer, cmd_count); + } + + NRFX_ASSERT(p_semmc); + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + + if (!p_cmd) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + if ((p_cb->transfer_in_progress || p_cb->prepared_pending) && + (p_cmd->cmd != NRF_SEMMC_CMD12_STOP_TRANSMISSION)) + { + return NRF_SEMMC_ERROR_BUSY; + } + + if (!p_config) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + + if (!p_transfer) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + + nrf_semmc_error_t retval; + retval = nrf_semmc_cmd_common(p_cb, p_semmc, p_cmd, p_config, p_transfer, cmd_count); + if (retval == NRF_SEMMC_SUCCESS) + { + p_cb->conf.config.ready_to_transfer = true; + nrf_emmc_config_set_ready_to_transfer(p_cb->p_hw_instance, &(p_cb->conf.config)); + __ASB(p_cb->p_hw_instance); + p_cb->transfer_in_progress = true; + + nrf_vpr_task_trigger(NRF_VPR, + offsetof(NRF_VPR_Type, TASKS_TRIGGER[SP_VPR_TASK_DPPI_0_IDX])); + } + + return retval; +} + +nrf_semmc_error_t nrf_semmc_cmd_prepare(nrf_semmc_t const * p_semmc, + nrf_semmc_cmd_desc_t * p_cmd, + nrf_semmc_config_t const * p_config, + nrf_semmc_transfer_desc_t * p_transfer, + size_t cmd_count) +{ + NRFX_ASSERT(p_semmc); + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + + if (!p_cmd) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + if (p_cb->prepared_pending) + { + return NRF_SEMMC_ERROR_BUSY; + } + + if (!p_config) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + + if (!p_transfer) + { + return NRF_SEMMC_ERROR_INVALID_PARAM; + } + + nrf_semmc_error_t retval; + retval = nrf_semmc_cmd_common(p_cb, p_semmc, p_cmd, p_config, p_transfer, cmd_count); + if (retval == NRF_SEMMC_SUCCESS) + { + p_cb->prepared_pending = true; + p_cb->conf.config.ready_to_transfer = true; + nrf_emmc_config_set_ready_to_transfer(p_cb->p_hw_instance, &(p_cb->conf.config)); + __ASB(p_cb->p_hw_instance); + } + return retval; +} + +bool nrf_semmc_is_busy(nrf_semmc_t const * p_semmc) +{ + NRFX_ASSERT(p_semmc); + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + + return p_cb->transfer_in_progress || p_cb->prepared_pending; +} + +nrf_semmc_error_t nrf_semmc_status_to_err(nrf_semmc_t const * p_semmc) +{ + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + nrf_semmc_error_t err = NRF_SEMMC_ERROR_ILLEGAL_CMD; + uint32_t raw_status = nrf_emmc_status_get(p_cb->p_hw_instance); + + switch (raw_status) + { + case SP_EMMC_STATUS_STATUS_CMDTIMEOUT_Msk: + { + err = NRF_SEMMC_ERROR_CMDTIMEOUT; + } break; + case SP_EMMC_STATUS_STATUS_CMDCRCERROR_Msk: + { + err = NRF_SEMMC_ERROR_CMDCRCERROR; + } break; + case SP_EMMC_STATUS_STATUS_DATACRCERROR_Msk: + { + err = NRF_SEMMC_ERROR_DATACRCERROR; + } break; + case SP_EMMC_STATUS_STATUS_PROTOCOLERR_Msk: + { + err = NRF_SEMMC_ERROR_INTERNAL_OR_PROTOCOL; + } break; + default: + { + err = NRF_SEMMC_SUCCESS; + } break; + } + return err; +} + +void nrf_semmc_get_status_response_after_xfer(nrf_semmc_t const * p_semmc, + nrf_semmc_cmd_desc_t * p_cmd) +{ + NRFX_ASSERT(p_semmc); + emmc_control_block_t * p_cb = &m_cb[p_semmc->drv_inst_idx]; + + p_cb->xfer_err = nrf_semmc_status_to_err(p_semmc); + p_cmd->err = p_cb->xfer_err; + //Get the response if we're expecting one + if (p_cmd->resp_type != NRF_SEMMC_RESP_NONE) + { + nrf_emmc_command_get_response(p_cb->p_hw_instance, p_cmd->response); + } +} + +void nrf_semmc_irq_handler(void) +{ + if (nrf_vpr_event_check(NRF_VPR, offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[SP_VPR_EVENT_IDX]))) + { + nrf_vpr_event_clear(NRF_VPR, offsetof(NRF_VPR_Type, EVENTS_TRIGGERED[SP_VPR_EVENT_IDX])); + + emmc_control_block_t * p_cb = &m_cb[m_current_xfer.drv_inst_idx]; + + if (nrf_emmc_event_check(p_cb->p_hw_instance, NRF_EMMC_EVENT_READYTOTRANSFER)) + { + nrf_emmc_event_clear(p_cb->p_hw_instance, NRF_EMMC_EVENT_READYTOTRANSFER); + p_cb->evt.type = NRF_SEMMC_EVT_XFER_STARTED; + p_cb->evt.data.xfer_done = NRF_SEMMC_RESULT_OK; + if ((p_cb->prepared_pending == true) && (p_cb->transfer_in_progress == false)) + { + // Transition the pending into a transfer_in_progress to allow for a new xfer to be scheduled. + p_cb->transfer_in_progress = true; + p_cb->prepared_pending = false; + } + + // Indicate to the app that the prepared transaction has been triggered. + p_cb->handler(&p_cb->evt, p_cb->p_context); + } + + // Check for completion event + if (nrf_emmc_event_check(p_cb->p_hw_instance, NRF_EMMC_EVENT_XFERCOMPLETE)) + { + nrf_emmc_event_clear(p_cb->p_hw_instance, NRF_EMMC_EVENT_XFERCOMPLETE); + + //End current transaction + p_cb->conf.config.ready_to_transfer = false; + nrf_emmc_config_set_ready_to_transfer(p_cb->p_hw_instance, &(p_cb->conf.config)); + __ASB(p_cb->p_hw_instance); + + if ((p_cb->prepared_pending == true) && (p_cb->transfer_in_progress == true)) // There was an ongoing transfer and we have one on hold. + { + // Trigger the pending transaction. + p_cb->conf.config.ready_to_transfer = true; + nrf_emmc_config_set_ready_to_transfer(p_cb->p_hw_instance, &(p_cb->conf.config)); + __ASB(p_cb->p_hw_instance); + // Continue transfer_in_progress, but clear the pending. + p_cb->prepared_pending = false; + } + else + { + p_cb->transfer_in_progress = false; + } + + p_cb->evt.type = NRF_SEMMC_EVT_XFER_DONE; + p_cb->evt.data.xfer_done = NRF_SEMMC_RESULT_OK; + + nrf_semmc_get_status_response_after_xfer(p_cb->p_hw_instance, m_current_xfer.p_cmd); + nrf_emmc_data_t emmc_data = {0}; + nrf_emmc_get_num_blocks(p_cb->p_hw_instance, &emmc_data); + m_current_xfer.p_transfer->num_blocks = emmc_data.block_num; + + p_cb->handler(&p_cb->evt, p_cb->p_context); + } + + // Check for abort event + if (nrf_emmc_event_check(p_cb->p_hw_instance, NRF_EMMC_EVENT_ABORTED)) + { + nrf_emmc_event_clear(p_cb->p_hw_instance, NRF_EMMC_EVENT_ABORTED); + + p_cb->transfer_in_progress = false; + p_cb->prepared_pending = false; + + p_cb->evt.type = NRF_SEMMC_EVT_XFER_DONE; + p_cb->evt.data.xfer_done = NRF_SEMMC_RESULT_ABORTED; + + p_cb->conf.config.ready_to_transfer = false; + nrf_emmc_config_set_ready_to_transfer(p_cb->p_hw_instance, &(p_cb->conf.config)); + __ASB(p_cb->p_hw_instance); + + p_cb->xfer_err = NRF_SEMMC_ERROR_TIMEOUT; + m_current_xfer.p_cmd->err = p_cb->xfer_err; + nrf_emmc_command_get_response(p_cb->p_hw_instance, m_current_xfer.p_cmd->response); + + nrf_emmc_data_t emmc_data = {0}; + nrf_emmc_get_num_blocks(p_cb->p_hw_instance, &emmc_data); + m_current_xfer.p_transfer->num_blocks = emmc_data.block_num; + + p_cb->handler(&p_cb->evt, p_cb->p_context); + } + } +} + +uint32_t * nrf_semmc_start_task_address_get(nrf_semmc_t const * p_semmc) +{ + (void)p_semmc; + return (uint32_t *)(nrf_vpr_task_address_get(NRF_VPR, + (nrf_vpr_task_t)offsetof(NRF_VPR_Type, + TASKS_TRIGGER[ + SP_VPR_TASK_DPPI_0_IDX]))); +} + +#endif // NRFX_CHECK(NRF_SEMMC_ENABLED) diff --git a/softperipheral/sQSPI/include/hal/nrf_qspi2.h b/softperipheral/sQSPI/include/hal/nrf_qspi2.h index 0be51a724c..f2afc65652 100644 --- a/softperipheral/sQSPI/include/hal/nrf_qspi2.h +++ b/softperipheral/sQSPI/include/hal/nrf_qspi2.h @@ -180,6 +180,10 @@ NRF_STATIC_INLINE void nrf_qspi2_core_ctrlr0_set(NRF_QSPI2_Type * p_reg, NRF_STATIC_INLINE void nrf_qspi2_core_spictrlr0_set(NRF_QSPI2_Type * p_reg, nrf_qspi2_core_spictrlr0_t conf); +NRF_STATIC_INLINE void nrf_qspi2_handshake_set(NRF_QSPI2_Type * p_reg, uint32_t val, uint8_t idx); + +NRF_STATIC_INLINE uint32_t nrf_qspi2_handshake_get(NRF_QSPI2_Type const * p_reg, uint8_t idx); + #ifndef NRF_DECLARE_ONLY NRF_STATIC_INLINE void nrf_qspi2_task_trigger(NRF_QSPI2_Type * p_reg, nrf_qspi2_task_t task) @@ -428,6 +432,16 @@ NRF_STATIC_INLINE void nrf_qspi2_core_spictrlr0_set(NRF_QSPI2_Type * p QSPI_CORE_CORE_SPICTRLR0_RSVDSPICTRLR0_Msk); } +NRF_STATIC_INLINE void nrf_qspi2_handshake_set(NRF_QSPI2_Type * p_reg, uint32_t val, uint8_t idx) +{ + p_reg->SPSYNC.AUX[idx] = val; +} + +NRF_STATIC_INLINE uint32_t nrf_qspi2_handshake_get(NRF_QSPI2_Type const * p_reg, uint8_t idx) +{ + return p_reg->SPSYNC.AUX[idx]; +} + #endif // NRF_DECLARE_ONLY /** @} */ diff --git a/softperipheral/sQSPI/include/nrf54l15/sqspi_firmware.h b/softperipheral/sQSPI/include/nrf54h/sqspi_firmware.h similarity index 86% rename from softperipheral/sQSPI/include/nrf54l15/sqspi_firmware.h rename to softperipheral/sQSPI/include/nrf54h/sqspi_firmware.h index ec7fefa628..eff8d9ad00 100644 --- a/softperipheral/sQSPI/include/nrf54l15/sqspi_firmware.h +++ b/softperipheral/sQSPI/include/nrf54h/sqspi_firmware.h @@ -6,6 +6,6 @@ #ifndef SQSPI_FIRMWARE_H__ #define SQSPI_FIRMWARE_H__ -#include "sqspi_firmware_v1.1.0.h" +#include "sqspi_firmware_v1.2.0.h" #define SOFTPERIPHERAL_META_HEADER_VERSION 2 #endif diff --git a/softperipheral/sQSPI/include/nrf54h/sqspi_firmware_v1.2.0.h b/softperipheral/sQSPI/include/nrf54h/sqspi_firmware_v1.2.0.h new file mode 100644 index 0000000000..c26b2dbb9d --- /dev/null +++ b/softperipheral/sQSPI/include/nrf54h/sqspi_firmware_v1.2.0.h @@ -0,0 +1,1012 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef SP_SQSPI_FIRMWARE_H__ +#define SP_SQSPI_FIRMWARE_H__ + +#include + +const uint8_t sqspi_firmware_bin[] = { + 0x05, 0xa0, 0x12, 0x00, 0xb1, 0x45, 0x10, 0x24, 0x00, 0x00, 0x02, 0x01, + 0x74, 0x03, 0x60, 0x00, 0x7a, 0xda, 0xe5, 0x12, 0x40, 0x37, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x04, 0x7a, 0xda, 0xe5, 0x12, 0x97, 0x02, 0x00, 0x00, + 0x81, 0x12, 0x03, 0xa3, 0xc2, 0x1e, 0x63, 0x02, 0x03, 0x06, 0x23, 0xa6, + 0x02, 0x1e, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xe3, 0x9f, 0x16, 0x93, + 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x03, 0x9c, 0x96, 0x93, 0x81, 0x45, + 0x7d, 0x56, 0x63, 0x0d, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x07, + 0xb5, 0x00, 0x63, 0x05, 0xc5, 0x00, 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, + 0x11, 0x03, 0xe5, 0xb7, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x83, 0x9e, + 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xc3, 0x9d, 0xf1, 0x13, 0x81, 0x45, + 0x63, 0x0b, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x05, 0xb5, 0x00, + 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, 0x11, 0x03, 0xf5, 0xb7, 0x97, 0x11, + 0x00, 0x00, 0x83, 0xa1, 0x21, 0x96, 0x17, 0x11, 0x00, 0x00, 0x03, 0x21, + 0x61, 0x9d, 0x33, 0x04, 0x01, 0x00, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0xe2, 0x9b, 0x73, 0x90, 0x72, 0x30, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0xe2, 0x93, 0x73, 0x90, 0x52, 0x30, 0x73, 0x10, 0x20, 0x34, 0x97, 0x12, + 0x00, 0x00, 0x83, 0xa2, 0x62, 0x9c, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, + 0xa3, 0x97, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xa3, 0x94, 0x89, 0x28, + 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x82, 0x93, 0x17, 0x13, 0x00, 0x00, + 0x03, 0x23, 0x83, 0x98, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xc3, 0x94, + 0x25, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x22, 0x96, 0x17, 0x13, + 0x00, 0x00, 0x03, 0x23, 0xe3, 0x95, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, + 0x63, 0x93, 0x39, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x82, 0x93, + 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xc3, 0x96, 0x97, 0x13, 0x00, 0x00, + 0x83, 0xa3, 0xc3, 0x8e, 0x11, 0x20, 0x21, 0xa8, 0x63, 0x8a, 0x62, 0x00, + 0x03, 0xa5, 0x03, 0x00, 0x23, 0xa0, 0xa2, 0x00, 0x91, 0x02, 0x91, 0x03, + 0xe3, 0x9a, 0x62, 0xfe, 0x82, 0x80, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0x22, 0x91, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x63, 0x8d, 0x25, 0x20, + 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x02, 0x8b, 0x17, 0x13, 0x00, 0x00, + 0x03, 0x23, 0x43, 0x8d, 0x19, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0x22, 0x8c, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x23, 0x91, 0x11, 0x20, + 0x09, 0xa8, 0x63, 0x87, 0x62, 0x00, 0x23, 0xa0, 0x02, 0x00, 0x91, 0x02, + 0xe3, 0x9d, 0x62, 0xfe, 0x82, 0x80, 0xef, 0x20, 0x30, 0x3c, 0xef, 0x00, + 0xd0, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 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0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +const uint32_t sqspi_firmware_bin_len = 11960; +#endif // SP_SQSPI_FIRMWARE_H__ diff --git a/softperipheral/sQSPI/include/nrf54h20/sqspi_firmware_v1.1.0.h b/softperipheral/sQSPI/include/nrf54h20/sqspi_firmware_v1.1.0.h deleted file mode 100644 index f511748fcb..0000000000 --- a/softperipheral/sQSPI/include/nrf54h20/sqspi_firmware_v1.1.0.h +++ /dev/null @@ -1,1007 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause - */ - -#ifndef SP_SQSPI_FIRMWARE_H__ -#define SP_SQSPI_FIRMWARE_H__ - -#include - -const uint8_t sqspi_firmware_bin[] = { - 0x05, 0xa0, 0x12, 0x00, 0xb1, 0x45, 0x10, 0x24, 0x00, 0x00, 0x01, 0x01, - 0x74, 0x03, 0x60, 0x00, 0x7a, 0xda, 0xe5, 0x12, 0x40, 0x37, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x04, 0x7a, 0xda, 0xe5, 0x12, 0x97, 0x02, 0x00, 0x00, - 0x81, 0x12, 0x03, 0xa3, 0xc2, 0x1e, 0x63, 0x02, 0x03, 0x06, 0x23, 0xa6, - 0x02, 0x1e, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xe3, 0x9f, 0x16, 0x93, - 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x03, 0x9c, 0x96, 0x93, 0x81, 0x45, - 0x7d, 0x56, 0x63, 0x0d, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x07, - 0xb5, 0x00, 0x63, 0x05, 0xc5, 0x00, 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, - 0x11, 0x03, 0xe5, 0xb7, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x83, 0x9e, - 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xc3, 0x9d, 0xf1, 0x13, 0x81, 0x45, - 0x63, 0x0b, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x05, 0xb5, 0x00, - 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, 0x11, 0x03, 0xf5, 0xb7, 0x97, 0x11, - 0x00, 0x00, 0x83, 0xa1, 0x21, 0x96, 0x17, 0x11, 0x00, 0x00, 0x03, 0x21, - 0x61, 0x9d, 0x33, 0x04, 0x01, 0x00, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, - 0xe2, 0x9b, 0x73, 0x90, 0x72, 0x30, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, - 0xe2, 0x93, 0x73, 0x90, 0x52, 0x30, 0x73, 0x10, 0x20, 0x34, 0x97, 0x12, - 0x00, 0x00, 0x83, 0xa2, 0x62, 0x9c, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, - 0xa3, 0x97, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xa3, 0x94, 0x89, 0x28, - 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x82, 0x93, 0x17, 0x13, 0x00, 0x00, - 0x03, 0x23, 0x83, 0x98, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xc3, 0x94, - 0x25, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x22, 0x96, 0x17, 0x13, - 0x00, 0x00, 0x03, 0x23, 0xe3, 0x95, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, - 0x63, 0x93, 0x39, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x82, 0x93, - 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xc3, 0x96, 0x97, 0x13, 0x00, 0x00, - 0x83, 0xa3, 0xc3, 0x8e, 0x11, 0x20, 0x21, 0xa8, 0x63, 0x8a, 0x62, 0x00, - 0x03, 0xa5, 0x03, 0x00, 0x23, 0xa0, 0xa2, 0x00, 0x91, 0x02, 0x91, 0x03, - 0xe3, 0x9a, 0x62, 0xfe, 0x82, 0x80, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, - 0x22, 0x91, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x63, 0x8d, 0x25, 0x20, - 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x02, 0x8b, 0x17, 0x13, 0x00, 0x00, - 0x03, 0x23, 0x43, 0x8d, 0x19, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, - 0x22, 0x8c, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x23, 0x91, 0x11, 0x20, - 0x09, 0xa8, 0x63, 0x87, 0x62, 0x00, 0x23, 0xa0, 0x02, 0x00, 0x91, 0x02, - 0xe3, 0x9d, 0x62, 0xfe, 0x82, 0x80, 0xef, 0x20, 0xb0, 0x38, 0xef, 0x00, - 0xd0, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xef, 0xbe, 0xad, 0xde, 0x73, 0x00, 0x20, 0x30, 0x13, 0x00, 0x00, 0x00, - 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xfa, 0x2c, 0x00, 0x00, - 0xfc, 0x2c, 0x00, 0x00, 0xfe, 0x2c, 0x00, 0x00, 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0x30, 0x07, 0x63, 0x03, 0xd6, 0x00, 0x82, 0x80, 0x93, 0x86, - 0x27, 0x00, 0x14, 0xc3, 0x83, 0xd6, 0x27, 0x00, 0x05, 0x67, 0x13, 0x07, - 0x07, 0x05, 0xe3, 0x97, 0xe6, 0xfe, 0x91, 0x07, 0x73, 0x90, 0x17, 0x34, - 0x82, 0x80, 0xb7, 0x07, 0x00, 0x08, 0x73, 0xb0, 0x07, 0x7e, 0x83, 0xa7, - 0x01, 0x8e, 0x91, 0xc3, 0x82, 0x87, 0x82, 0x80, 0x79, 0x71, 0x06, 0xd6, - 0x16, 0xd4, 0x1a, 0xd2, 0x1e, 0xd0, 0x22, 0xce, 0x26, 0xcc, 0x2a, 0xca, - 0x2e, 0xc8, 0x32, 0xc6, 0x36, 0xc4, 0x3a, 0xc2, 0x3e, 0xc0, 0x8a, 0x86, - 0x23, 0xa6, 0xd1, 0x86, 0x93, 0x06, 0xf0, 0x03, 0x73, 0x90, 0x76, 0x34, - 0xef, 0xe0, 0xaf, 0x80, 0x31, 0xa0, 0x83, 0xa6, 0xc1, 0x86, 0x36, 0x81, - 0x1d, 0x45, 0x09, 0xa0, 0xb2, 0x50, 0xa2, 0x52, 0x12, 0x53, 0x82, 0x53, - 0x72, 0x44, 0xe2, 0x44, 0xc2, 0x45, 0x32, 0x46, 0xa2, 0x46, 0x12, 0x47, - 0x82, 0x47, 0x45, 0x61, 0x82, 0x80, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, - 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, - 0x01, 0xa0, 0x01, 0xa0, 0x82, 0x80, 0x00, 0x00, 0x13, 0x03, 0xf0, 0x00, - 0x13, 0x07, 0x05, 0x00, 0x63, 0x7e, 0xc3, 0x02, 0x93, 0x77, 0xf7, 0x00, - 0x63, 0x90, 0x07, 0x0a, 0x63, 0x92, 0x05, 0x08, 0x93, 0x76, 0x06, 0xff, - 0x13, 0x76, 0xf6, 0x00, 0xb3, 0x86, 0xe6, 0x00, 0x23, 0x20, 0xb7, 0x00, - 0x23, 0x22, 0xb7, 0x00, 0x23, 0x24, 0xb7, 0x00, 0x23, 0x26, 0xb7, 0x00, - 0x13, 0x07, 0x07, 0x01, 0xe3, 0x66, 0xd7, 0xfe, 0x63, 0x14, 0x06, 0x00, - 0x67, 0x80, 0x00, 0x00, 0xb3, 0x06, 0xc3, 0x40, 0x93, 0x96, 0x26, 0x00, - 0x97, 0x02, 0x00, 0x00, 0xb3, 0x86, 0x56, 0x00, 0x67, 0x80, 0xc6, 0x00, - 0x23, 0x07, 0xb7, 0x00, 0xa3, 0x06, 0xb7, 0x00, 0x23, 0x06, 0xb7, 0x00, - 0xa3, 0x05, 0xb7, 0x00, 0x23, 0x05, 0xb7, 0x00, 0xa3, 0x04, 0xb7, 0x00, - 0x23, 0x04, 0xb7, 0x00, 0xa3, 0x03, 0xb7, 0x00, 0x23, 0x03, 0xb7, 0x00, - 0xa3, 0x02, 0xb7, 0x00, 0x23, 0x02, 0xb7, 0x00, 0xa3, 0x01, 0xb7, 0x00, - 0x23, 0x01, 0xb7, 0x00, 0xa3, 0x00, 0xb7, 0x00, 0x23, 0x00, 0xb7, 0x00, - 0x67, 0x80, 0x00, 0x00, 0x93, 0xf5, 0xf5, 0x0f, 0x93, 0x96, 0x85, 0x00, - 0xb3, 0xe5, 0xd5, 0x00, 0x93, 0x96, 0x05, 0x01, 0xb3, 0xe5, 0xd5, 0x00, - 0x6f, 0xf0, 0xdf, 0xf6, 0x93, 0x96, 0x27, 0x00, 0x97, 0x02, 0x00, 0x00, - 0xb3, 0x86, 0x56, 0x00, 0x93, 0x82, 0x00, 0x00, 0xe7, 0x80, 0x06, 0xfa, - 0x93, 0x80, 0x02, 0x00, 0x93, 0x87, 0x07, 0xff, 0x33, 0x07, 0xf7, 0x40, - 0x33, 0x06, 0xf6, 0x00, 0xe3, 0x78, 0xc3, 0xf6, 0x6f, 0xf0, 0xdf, 0xf3, - 0x38, 0x2e, 0x00, 0x00, 0x40, 0x37, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, - 0x80, 0x2e, 0x00, 0x00, 0x88, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x2e, 0x00, 0x00, 0x88, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x80, 0x2e, 0x00, 0x00, 0x88, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x88, 0x37, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x2c, 0x38, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x2c, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -const uint32_t sqspi_firmware_bin_len = 11904; -#endif // SP_SQSPI_FIRMWARE_H__ diff --git a/softperipheral/sQSPI/include/nrf54h20/sqspi_firmware.h b/softperipheral/sQSPI/include/nrf54l/sqspi_firmware.h similarity index 86% rename from softperipheral/sQSPI/include/nrf54h20/sqspi_firmware.h rename to softperipheral/sQSPI/include/nrf54l/sqspi_firmware.h index ec7fefa628..eff8d9ad00 100644 --- a/softperipheral/sQSPI/include/nrf54h20/sqspi_firmware.h +++ b/softperipheral/sQSPI/include/nrf54l/sqspi_firmware.h @@ -6,6 +6,6 @@ #ifndef SQSPI_FIRMWARE_H__ #define SQSPI_FIRMWARE_H__ -#include "sqspi_firmware_v1.1.0.h" +#include "sqspi_firmware_v1.2.0.h" #define SOFTPERIPHERAL_META_HEADER_VERSION 2 #endif diff --git a/softperipheral/sQSPI/include/nrf54l/sqspi_firmware_v1.2.0.h b/softperipheral/sQSPI/include/nrf54l/sqspi_firmware_v1.2.0.h new file mode 100644 index 0000000000..45ab756d1e --- /dev/null +++ b/softperipheral/sQSPI/include/nrf54l/sqspi_firmware_v1.2.0.h @@ -0,0 +1,1008 @@ +/* + * Copyright (c) 2025 Nordic Semiconductor ASA + * + * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause + */ + +#ifndef SP_SQSPI_FIRMWARE_H__ +#define SP_SQSPI_FIRMWARE_H__ + +#include + +const uint8_t sqspi_firmware_bin[] = { + 0x05, 0xa0, 0x12, 0x00, 0xb1, 0x45, 0x08, 0x22, 0x00, 0x00, 0x02, 0x01, + 0x74, 0x03, 0x60, 0x00, 0x7a, 0xda, 0xe5, 0x12, 0x40, 0x37, 0x00, 0x00, + 0x20, 0x00, 0x00, 0x04, 0x7a, 0xda, 0xe5, 0x12, 0x97, 0x02, 0x00, 0x00, + 0x81, 0x12, 0x03, 0xa3, 0xc2, 0x1e, 0x63, 0x02, 0x03, 0x06, 0x23, 0xa6, + 0x02, 0x1e, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x23, 0xa0, 0x16, 0x93, + 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x43, 0x9c, 0x96, 0x93, 0x81, 0x45, + 0x7d, 0x56, 0x63, 0x0d, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x07, + 0xb5, 0x00, 0x63, 0x05, 0xc5, 0x00, 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, + 0x11, 0x03, 0xe5, 0xb7, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xc3, 0x9e, + 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x03, 0x9e, 0xf1, 0x13, 0x81, 0x45, + 0x63, 0x0b, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x05, 0xb5, 0x00, + 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, 0x11, 0x03, 0xf5, 0xb7, 0x97, 0x11, + 0x00, 0x00, 0x83, 0xa1, 0x61, 0x96, 0x17, 0x11, 0x00, 0x00, 0x03, 0x21, + 0xa1, 0x9d, 0x33, 0x04, 0x01, 0x00, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0x22, 0x9c, 0x73, 0x90, 0x72, 0x30, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0x22, 0x94, 0x73, 0x90, 0x52, 0x30, 0x73, 0x10, 0x20, 0x34, 0x97, 0x12, + 0x00, 0x00, 0x83, 0xa2, 0xa2, 0x9c, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, + 0xe3, 0x97, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xe3, 0x94, 0x89, 0x28, + 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0xc2, 0x93, 0x17, 0x13, 0x00, 0x00, + 0x03, 0x23, 0xc3, 0x98, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x03, 0x95, + 0x25, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x62, 0x96, 0x17, 0x13, + 0x00, 0x00, 0x03, 0x23, 0x23, 0x96, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, + 0xa3, 0x93, 0x39, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0xc2, 0x93, + 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x03, 0x97, 0x97, 0x13, 0x00, 0x00, + 0x83, 0xa3, 0x03, 0x8f, 0x11, 0x20, 0x21, 0xa8, 0x63, 0x8a, 0x62, 0x00, + 0x03, 0xa5, 0x03, 0x00, 0x23, 0xa0, 0xa2, 0x00, 0x91, 0x02, 0x91, 0x03, + 0xe3, 0x9a, 0x62, 0xfe, 0x82, 0x80, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0x62, 0x91, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xa3, 0x8d, 0x25, 0x20, + 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x42, 0x8b, 0x17, 0x13, 0x00, 0x00, + 0x03, 0x23, 0x83, 0x8d, 0x19, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, + 0x62, 0x8c, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x63, 0x91, 0x11, 0x20, + 0x09, 0xa8, 0x63, 0x87, 0x62, 0x00, 0x23, 0xa0, 0x02, 0x00, 0x91, 0x02, + 0xe3, 0x9d, 0x62, 0xfe, 0x82, 0x80, 0xef, 0x20, 0x10, 0x39, 0xef, 0x00, + 0x10, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 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0x00, 0x93, 0x87, 0x07, 0xff, + 0x33, 0x07, 0xf7, 0x40, 0x33, 0x06, 0xf6, 0x00, 0xe3, 0x78, 0xc3, 0xf6, + 0x6f, 0xf0, 0xdf, 0xf3, 0x3c, 0x2e, 0x00, 0x00, 0x40, 0x37, 0x00, 0x00, + 0x12, 0x00, 0x00, 0x00, 0x84, 0x2e, 0x00, 0x00, 0x88, 0x37, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x84, 0x2e, 0x00, 0x00, 0x88, 0x37, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x84, 0x2e, 0x00, 0x00, 0x88, 0x37, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x88, 0x37, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, + 0x2c, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x2c, 0x38, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x34, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00 +}; +const uint32_t sqspi_firmware_bin_len = 11908; +#endif // SP_SQSPI_FIRMWARE_H__ diff --git a/softperipheral/sQSPI/include/nrf54l15/sqspi_firmware_v1.1.0.h b/softperipheral/sQSPI/include/nrf54l15/sqspi_firmware_v1.1.0.h deleted file mode 100644 index fa0c87b3ef..0000000000 --- a/softperipheral/sQSPI/include/nrf54l15/sqspi_firmware_v1.1.0.h +++ /dev/null @@ -1,1003 +0,0 @@ -/* - * Copyright (c) 2025 Nordic Semiconductor ASA - * - * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause - */ - -#ifndef SP_SQSPI_FIRMWARE_H__ -#define SP_SQSPI_FIRMWARE_H__ - -#include - -const uint8_t sqspi_firmware_bin[] = { - 0x05, 0xa0, 0x12, 0x00, 0xb1, 0x45, 0x08, 0x22, 0x00, 0x00, 0x01, 0x01, - 0x74, 0x03, 0x60, 0x00, 0x7a, 0xda, 0xe5, 0x12, 0x40, 0x37, 0x00, 0x00, - 0x20, 0x00, 0x00, 0x04, 0x7a, 0xda, 0xe5, 0x12, 0x97, 0x02, 0x00, 0x00, - 0x81, 0x12, 0x03, 0xa3, 0xc2, 0x1e, 0x63, 0x02, 0x03, 0x06, 0x23, 0xa6, - 0x02, 0x1e, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x23, 0xa0, 0x16, 0x93, - 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x43, 0x9c, 0x96, 0x93, 0x81, 0x45, - 0x7d, 0x56, 0x63, 0x0d, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x07, - 0xb5, 0x00, 0x63, 0x05, 0xc5, 0x00, 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, - 0x11, 0x03, 0xe5, 0xb7, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xc3, 0x9e, - 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x03, 0x9e, 0xf1, 0x13, 0x81, 0x45, - 0x63, 0x0b, 0x73, 0x00, 0x03, 0x25, 0x03, 0x00, 0x63, 0x05, 0xb5, 0x00, - 0x16, 0x95, 0x23, 0x20, 0xa3, 0x00, 0x11, 0x03, 0xf5, 0xb7, 0x97, 0x11, - 0x00, 0x00, 0x83, 0xa1, 0x61, 0x96, 0x17, 0x11, 0x00, 0x00, 0x03, 0x21, - 0xa1, 0x9d, 0x33, 0x04, 0x01, 0x00, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, - 0x22, 0x9c, 0x73, 0x90, 0x72, 0x30, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, - 0x22, 0x94, 0x73, 0x90, 0x52, 0x30, 0x73, 0x10, 0x20, 0x34, 0x97, 0x12, - 0x00, 0x00, 0x83, 0xa2, 0xa2, 0x9c, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, - 0xe3, 0x97, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0xe3, 0x94, 0x89, 0x28, - 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0xc2, 0x93, 0x17, 0x13, 0x00, 0x00, - 0x03, 0x23, 0xc3, 0x98, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, 0x03, 0x95, - 0x25, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x62, 0x96, 0x17, 0x13, - 0x00, 0x00, 0x03, 0x23, 0x23, 0x96, 0x97, 0x13, 0x00, 0x00, 0x83, 0xa3, - 0xa3, 0x93, 0x39, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0xc2, 0x93, - 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x03, 0x97, 0x97, 0x13, 0x00, 0x00, - 0x83, 0xa3, 0x03, 0x8f, 0x11, 0x20, 0x21, 0xa8, 0x63, 0x8a, 0x62, 0x00, - 0x03, 0xa5, 0x03, 0x00, 0x23, 0xa0, 0xa2, 0x00, 0x91, 0x02, 0x91, 0x03, - 0xe3, 0x9a, 0x62, 0xfe, 0x82, 0x80, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, - 0x62, 0x91, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0xa3, 0x8d, 0x25, 0x20, - 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, 0x42, 0x8b, 0x17, 0x13, 0x00, 0x00, - 0x03, 0x23, 0x83, 0x8d, 0x19, 0x28, 0x97, 0x12, 0x00, 0x00, 0x83, 0xa2, - 0x62, 0x8c, 0x17, 0x13, 0x00, 0x00, 0x03, 0x23, 0x63, 0x91, 0x11, 0x20, - 0x09, 0xa8, 0x63, 0x87, 0x62, 0x00, 0x23, 0xa0, 0x02, 0x00, 0x91, 0x02, - 0xe3, 0x9d, 0x62, 0xfe, 0x82, 0x80, 0xef, 0x20, 0xd0, 0x35, 0xef, 0x00, - 0x10, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xef, 0xbe, 0xad, 0xde, 0x73, 0x00, 0x20, 0x30, 0x13, 0x00, 0x00, 0x00, - 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcc, 0x2c, 0x00, 0x00, - 0xce, 0x2c, 0x00, 0x00, 0xd0, 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xd2, 0x2c, 0x00, 0x00, 0xd4, 0x2c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0xd6, 0x2c, 0x00, 0x00, 0xd8, 0x2c, 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0x07, 0x7e, 0x83, 0xa7, 0x41, 0x8e, - 0xb1, 0xc3, 0x71, 0x11, 0x06, 0xc0, 0x82, 0x97, 0xf3, 0x27, 0x10, 0x34, - 0x17, 0xe7, 0xff, 0xff, 0x03, 0x27, 0x47, 0xdf, 0x1c, 0xc3, 0x03, 0xd6, - 0x07, 0x00, 0x93, 0x06, 0x30, 0x07, 0x63, 0x05, 0xd6, 0x00, 0x82, 0x40, - 0x11, 0x01, 0x82, 0x80, 0x93, 0x86, 0x27, 0x00, 0x14, 0xc3, 0x83, 0xd6, - 0x27, 0x00, 0x05, 0x67, 0x13, 0x07, 0x07, 0x05, 0xe3, 0x95, 0xe6, 0xfe, - 0x91, 0x07, 0x73, 0x90, 0x17, 0x34, 0xc5, 0xb7, 0xf3, 0x27, 0x10, 0x34, - 0x17, 0xe7, 0xff, 0xff, 0x03, 0x27, 0x87, 0xdb, 0x1c, 0xc3, 0x03, 0xd6, - 0x07, 0x00, 0x93, 0x06, 0x30, 0x07, 0x63, 0x03, 0xd6, 0x00, 0x82, 0x80, - 0x93, 0x86, 0x27, 0x00, 0x14, 0xc3, 0x83, 0xd6, 0x27, 0x00, 0x05, 0x67, - 0x13, 0x07, 0x07, 0x05, 0xe3, 0x97, 0xe6, 0xfe, 0x91, 0x07, 0x73, 0x90, - 0x17, 0x34, 0x82, 0x80, 0xb7, 0x07, 0x08, 0x00, 0x73, 0xb0, 0x07, 0x7e, - 0x83, 0xa7, 0x01, 0x8e, 0x91, 0xc3, 0x82, 0x87, 0x82, 0x80, 0x79, 0x71, - 0x06, 0xd6, 0x16, 0xd4, 0x1a, 0xd2, 0x1e, 0xd0, 0x22, 0xce, 0x26, 0xcc, - 0x2a, 0xca, 0x2e, 0xc8, 0x32, 0xc6, 0x36, 0xc4, 0x3a, 0xc2, 0x3e, 0xc0, - 0x8a, 0x86, 0x23, 0xa6, 0xd1, 0x86, 0x93, 0x06, 0xf0, 0x03, 0x73, 0x90, - 0x76, 0x34, 0xef, 0xe0, 0xcf, 0x83, 0x31, 0xa0, 0x83, 0xa6, 0xc1, 0x86, - 0x36, 0x81, 0x1d, 0x45, 0x09, 0xa0, 0xb2, 0x50, 0xa2, 0x52, 0x12, 0x53, - 0x82, 0x53, 0x72, 0x44, 0xe2, 0x44, 0xc2, 0x45, 0x32, 0x46, 0xa2, 0x46, - 0x12, 0x47, 0x82, 0x47, 0x45, 0x61, 0x82, 0x80, 0x01, 0xa0, 0x01, 0xa0, - 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, - 0x01, 0xa0, 0x01, 0xa0, 0x01, 0xa0, 0x82, 0x80, 0x13, 0x03, 0xf0, 0x00, - 0x13, 0x07, 0x05, 0x00, 0x63, 0x7e, 0xc3, 0x02, 0x93, 0x77, 0xf7, 0x00, - 0x63, 0x90, 0x07, 0x0a, 0x63, 0x92, 0x05, 0x08, 0x93, 0x76, 0x06, 0xff, - 0x13, 0x76, 0xf6, 0x00, 0xb3, 0x86, 0xe6, 0x00, 0x23, 0x20, 0xb7, 0x00, - 0x23, 0x22, 0xb7, 0x00, 0x23, 0x24, 0xb7, 0x00, 0x23, 0x26, 0xb7, 0x00, - 0x13, 0x07, 0x07, 0x01, 0xe3, 0x66, 0xd7, 0xfe, 0x63, 0x14, 0x06, 0x00, - 0x67, 0x80, 0x00, 0x00, 0xb3, 0x06, 0xc3, 0x40, 0x93, 0x96, 0x26, 0x00, - 0x97, 0x02, 0x00, 0x00, 0xb3, 0x86, 0x56, 0x00, 0x67, 0x80, 0xc6, 0x00, - 0x23, 0x07, 0xb7, 0x00, 0xa3, 0x06, 0xb7, 0x00, 0x23, 0x06, 0xb7, 0x00, - 0xa3, 0x05, 0xb7, 0x00, 0x23, 0x05, 0xb7, 0x00, 0xa3, 0x04, 0xb7, 0x00, - 0x23, 0x04, 0xb7, 0x00, 0xa3, 0x03, 0xb7, 0x00, 0x23, 0x03, 0xb7, 0x00, - 0xa3, 0x02, 0xb7, 0x00, 0x23, 0x02, 0xb7, 0x00, 0xa3, 0x01, 0xb7, 0x00, - 0x23, 0x01, 0xb7, 0x00, 0xa3, 0x00, 0xb7, 0x00, 0x23, 0x00, 0xb7, 0x00, - 0x67, 0x80, 0x00, 0x00, 0x93, 0xf5, 0xf5, 0x0f, 0x93, 0x96, 0x85, 0x00, - 0xb3, 0xe5, 0xd5, 0x00, 0x93, 0x96, 0x05, 0x01, 0xb3, 0xe5, 0xd5, 0x00, - 0x6f, 0xf0, 0xdf, 0xf6, 0x93, 0x96, 0x27, 0x00, 0x97, 0x02, 0x00, 0x00, - 0xb3, 0x86, 0x56, 0x00, 0x93, 0x82, 0x00, 0x00, 0xe7, 0x80, 0x06, 0xfa, - 0x93, 0x80, 0x02, 0x00, 0x93, 0x87, 0x07, 0xff, 0x33, 0x07, 0xf7, 0x40, - 0x33, 0x06, 0xf6, 0x00, 0xe3, 0x78, 0xc3, 0xf6, 0x6f, 0xf0, 0xdf, 0xf3, - 0x08, 0x2e, 0x00, 0x00, 0x40, 0x37, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, - 0x50, 0x2e, 0x00, 0x00, 0x88, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x50, 0x2e, 0x00, 0x00, 0x88, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x50, 0x2e, 0x00, 0x00, 0x88, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x88, 0x37, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x2c, 0x38, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x2c, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -const uint32_t sqspi_firmware_bin_len = 11856; -#endif // SP_SQSPI_FIRMWARE_H__ diff --git a/softperipheral/sQSPI/include/nrf_config_sqspi.h b/softperipheral/sQSPI/include/nrf_config_sqspi.h index 582dc6ecb9..e35df74def 100644 --- a/softperipheral/sQSPI/include/nrf_config_sqspi.h +++ b/softperipheral/sQSPI/include/nrf_config_sqspi.h @@ -16,15 +16,6 @@ #define NRF_SQSPI_ENABLED 0 #endif -/** - * @brief NRF_SQSPI_SP_INSTANCE - * - * Address value. 32 bits - */ -#ifndef NRF_SQSPI_SP_FIRMWARE_ADDR -#define NRF_SQSPI_SP_FIRMWARE_ADDR 0xDEADBEEF -#endif - /** * @brief NRF_SQSPI_MAX_NUM_DATA_LINES - Maximal number of data lines used by the QSPI peripheral. * diff --git a/softperipheral/sQSPI/include/nrf_sp_qspi.h b/softperipheral/sQSPI/include/nrf_sp_qspi.h index b52e120ee7..f34486afec 100644 --- a/softperipheral/sQSPI/include/nrf_sp_qspi.h +++ b/softperipheral/sQSPI/include/nrf_sp_qspi.h @@ -7,19 +7,7 @@ #ifndef NRF_SP_QSPI_H__ #define NRF_SP_QSPI_H__ -#include "nrf.h" // Resolve nrfXX_types.h for the correct target to get definitions for __IO, __IOM etc. -#if defined (NRF_FLPR) -extern char __soft_periph_com_start__[]; -#define NRF_SP_QSPI_BASE ((uint32_t)&__soft_periph_com_start__) -#elif defined (NRF_APPLICATION) -#include "nrfx_config.h" -#define NRF_SP_QSPI_BASE (NRF_SQSPI_SP_FIRMWARE_ADDR + 0x3b40) -#else - #pragma warning "Processor not defined." -#endif - -#define NRF_SP_QSPI ((NRF_SP_QSPI_Type*)NRF_SP_QSPI_BASE) - +#include "nrf.h" // Resolve nrfXX_types.h for the correct target to get definitions for __IO, __IOM etc. /* =========================================================================================================================== * ================ QSPI ================ * ===========================================================================================================================*/ @@ -2463,870 +2451,890 @@ typedef struct */ typedef struct { - __IOM NRF_QSPI_CORE_CORE_Type CORE; /*!< (unspecified) */ -} NRF_QSPI_CORE_Type; /*!< */ + __IOM NRF_QSPI_CORE_CORE_Type CORE; /*!< (unspecified) */ +} NRF_QSPI_CORE_Type; /*!< */ + +/* ================================================== Struct QSPI_SPSYNC ================================================== */ +/** + * @brief SPSYNC [QSPI_SPSYNC] Registers used to acknowledge API function calls + */ +typedef struct +{ + __IOM uint32_t AUX[4]; /*!< (@ 0x00000000) Auxiliary registers for XSB macro call handshaking */ +} NRF_QSPI_SPSYNC_Type; /*!< Size = 16 (0x010) */ + +/* QSPI_SPSYNC_AUX: Auxiliary registers for XSB macro call handshaking */ + #define QSPI_SPSYNC_AUX_MaxCount (4UL) /*!< Max size of AUX[4] array. */ + #define QSPI_SPSYNC_AUX_MaxIndex (3UL) /*!< Max index of AUX[4] array. */ + #define QSPI_SPSYNC_AUX_MinIndex (0UL) /*!< Min index of AUX[4] array. */ + #define QSPI_SPSYNC_AUX_ResetValue (0x00000000UL) /*!< Reset value of AUX[4] register. */ + +/* AUX @Bits 0..31 : Auxiliary register */ + #define QSPI_SPSYNC_AUX_AUX_Pos (0UL) /*!< Position of AUX field. */ + #define QSPI_SPSYNC_AUX_AUX_Msk (0xFFFFFFFFUL << QSPI_SPSYNC_AUX_AUX_Pos) /*!< Bit mask of AUX field. */ /* ======================================================= Struct QSPI ======================================================= */ /** * @brief Quad serial peripheral interface */ -typedef struct /*!< QSPI Structure */ +typedef struct /*!< QSPI Structure */ { - __OM uint32_t TASKS_START; /*!< Start operation. */ - __OM uint32_t TASKS_RESET; /*!< Reset the QSPI */ - __IOM uint32_t EVENTS_CORE; /*!< Interrupt from the QSPI core */ + __OM uint32_t TASKS_START; /*!< Start operation. */ + __OM uint32_t TASKS_RESET; /*!< Reset the QSPI */ + __IOM uint32_t EVENTS_CORE; /*!< Interrupt from the QSPI core */ __IOM NRF_QSPI_EVENTS_DMA_Type - EVENTS_DMA; /*!< Peripheral events. */ - __IOM uint32_t EVENTS_IDLE; /*!< This event signifies that the QSPI core is no longer - * busy*/ - __IOM uint32_t SHORTS; /*!< Shortcuts between local events and tasks */ - __IOM uint32_t INTEN; /*!< Enable or disable interrupt */ - __IOM uint32_t INTENSET; /*!< Enable interrupt */ - __IOM uint32_t INTENCLR; /*!< Disable interrupt */ - __IM uint32_t INTPEND; /*!< Pending interrupts */ - __IOM uint32_t ENABLE; /*!< Enables the QSPI This requests clock for the IP core */ - __IOM NRF_QSPI_CONFIG_Type CONFIG; /*!< (unspecified) */ - __IOM NRF_QSPI_FORMAT_Type FORMAT; /*!< (unspecified) */ - __IOM NRF_QSPI_DMA_Type DMA; /*!< (unspecified) */ - __IOM NRF_QSPI_CORE_Type CORE; /*!< (unspecified) */ -} NRF_SP_QSPI_Type; /*!< */ + EVENTS_DMA; /*!< Peripheral events. */ + __IOM uint32_t EVENTS_IDLE; /*!< This event signifies that the QSPI core is no longer + * busy*/ + __IOM uint32_t SHORTS; /*!< Shortcuts between local events and tasks */ + __IOM uint32_t INTEN; /*!< Enable or disable interrupt */ + __IOM uint32_t INTENSET; /*!< Enable interrupt */ + __IOM uint32_t INTENCLR; /*!< Disable interrupt */ + __IM uint32_t INTPEND; /*!< Pending interrupts */ + __IOM uint32_t ENABLE; /*!< Enables the QSPI This requests clock for the IP core */ + __IOM NRF_QSPI_CONFIG_Type CONFIG; /*!< (unspecified) */ + __IOM NRF_QSPI_FORMAT_Type FORMAT; /*!< (unspecified) */ + __IOM NRF_QSPI_DMA_Type DMA; /*!< (unspecified) */ + __IOM NRF_QSPI_CORE_Type CORE; /*!< (unspecified) */ + __IOM NRF_QSPI_SPSYNC_Type SPSYNC; /*!< (unspecified) */ +} NRF_SP_QSPI_Type; /*!< */ /* QSPI_TASKS_START: Start operation. */ #define QSPI_TASKS_START_ResetValue \ - (0x00000000UL) /*!< Reset value of TASKS_START register. */ + (0x00000000UL) /*!< Reset value of TASKS_START register. */ /* TASKS_START @Bit 0 : Start operation. */ #define QSPI_TASKS_START_TASKS_START_Pos \ - (0UL) /*!< Position of TASKS_START field. */ + (0UL) /*!< Position of TASKS_START field. */ #define QSPI_TASKS_START_TASKS_START_Msk \ - (0x1UL << QSPI_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ + (0x1UL << QSPI_TASKS_START_TASKS_START_Pos) /*!< Bit mask of TASKS_START field. */ #define QSPI_TASKS_START_TASKS_START_Min \ - (0x1UL) /*!< Min enumerator value of TASKS_START field. */ + (0x1UL) /*!< Min enumerator value of TASKS_START field. */ #define QSPI_TASKS_START_TASKS_START_Max \ - (0x1UL) /*!< Max enumerator value of TASKS_START field. */ + (0x1UL) /*!< Max enumerator value of TASKS_START field. */ #define QSPI_TASKS_START_TASKS_START_Trigger \ - (0x1UL) /*!< Trigger task */ + (0x1UL) /*!< Trigger task */ /* QSPI_TASKS_RESET: Reset the QSPI */ #define QSPI_TASKS_RESET_ResetValue \ - (0x00000000UL) /*!< Reset value of TASKS_RESET register. */ + (0x00000000UL) /*!< Reset value of TASKS_RESET register. */ /* TASKS_RESET @Bit 0 : Reset the QSPI */ #define QSPI_TASKS_RESET_TASKS_RESET_Pos \ - (0UL) /*!< Position of TASKS_RESET field. */ + (0UL) /*!< Position of TASKS_RESET field. */ #define QSPI_TASKS_RESET_TASKS_RESET_Msk \ - (0x1UL << QSPI_TASKS_RESET_TASKS_RESET_Pos) /*!< Bit mask of TASKS_RESET field. */ + (0x1UL << QSPI_TASKS_RESET_TASKS_RESET_Pos) /*!< Bit mask of TASKS_RESET field. */ #define QSPI_TASKS_RESET_TASKS_RESET_Min \ - (0x1UL) /*!< Min enumerator value of TASKS_RESET field. */ + (0x1UL) /*!< Min enumerator value of TASKS_RESET field. */ #define QSPI_TASKS_RESET_TASKS_RESET_Max \ - (0x1UL) /*!< Max enumerator value of TASKS_RESET field. */ + (0x1UL) /*!< Max enumerator value of TASKS_RESET field. */ #define QSPI_TASKS_RESET_TASKS_RESET_Trigger \ - (0x1UL) /*!< Trigger task */ + (0x1UL) /*!< Trigger task */ /* QSPI_EVENTS_CORE: Interrupt from the QSPI core */ #define QSPI_EVENTS_CORE_ResetValue \ - (0x00000000UL) /*!< Reset value of EVENTS_CORE register. */ + (0x00000000UL) /*!< Reset value of EVENTS_CORE register. */ /* EVENTS_CORE @Bit 0 : Interrupt from the QSPI core */ #define QSPI_EVENTS_CORE_EVENTS_CORE_Pos \ - (0UL) /*!< Position of EVENTS_CORE field. */ + (0UL) /*!< Position of EVENTS_CORE field. */ #define QSPI_EVENTS_CORE_EVENTS_CORE_Msk \ - (0x1UL << QSPI_EVENTS_CORE_EVENTS_CORE_Pos) /*!< Bit mask of EVENTS_CORE field. */ + (0x1UL << QSPI_EVENTS_CORE_EVENTS_CORE_Pos) /*!< Bit mask of EVENTS_CORE field. */ #define QSPI_EVENTS_CORE_EVENTS_CORE_Min \ - (0x0UL) /*!< Min enumerator value of EVENTS_CORE field. */ + (0x0UL) /*!< Min enumerator value of EVENTS_CORE field. */ #define QSPI_EVENTS_CORE_EVENTS_CORE_Max \ - (0x1UL) /*!< Max enumerator value of EVENTS_CORE field. */ + (0x1UL) /*!< Max enumerator value of EVENTS_CORE field. */ #define QSPI_EVENTS_CORE_EVENTS_CORE_NotGenerated \ - (0x0UL) /*!< Event not generated */ + (0x0UL) /*!< Event not generated */ #define QSPI_EVENTS_CORE_EVENTS_CORE_Generated \ - (0x1UL) /*!< Event generated */ + (0x1UL) /*!< Event generated */ /* QSPI_EVENTS_IDLE: This event signifies that the QSPI core is no longer busy */ #define QSPI_EVENTS_IDLE_ResetValue \ - (0x00000000UL) /*!< Reset value of EVENTS_IDLE register. */ + (0x00000000UL) /*!< Reset value of EVENTS_IDLE register. */ /* EVENTS_IDLE @Bit 0 : This event signifies that the QSPI core is no longer busy */ #define QSPI_EVENTS_IDLE_EVENTS_IDLE_Pos \ - (0UL) /*!< Position of EVENTS_IDLE field. */ + (0UL) /*!< Position of EVENTS_IDLE field. */ #define QSPI_EVENTS_IDLE_EVENTS_IDLE_Msk \ - (0x1UL << QSPI_EVENTS_IDLE_EVENTS_IDLE_Pos) /*!< Bit mask of EVENTS_IDLE field. */ + (0x1UL << QSPI_EVENTS_IDLE_EVENTS_IDLE_Pos) /*!< Bit mask of EVENTS_IDLE field. */ #define QSPI_EVENTS_IDLE_EVENTS_IDLE_Min \ - (0x0UL) /*!< Min enumerator value of EVENTS_IDLE field. */ + (0x0UL) /*!< Min enumerator value of EVENTS_IDLE field. */ #define QSPI_EVENTS_IDLE_EVENTS_IDLE_Max \ - (0x1UL) /*!< Max enumerator value of EVENTS_IDLE field. */ + (0x1UL) /*!< Max enumerator value of EVENTS_IDLE field. */ #define QSPI_EVENTS_IDLE_EVENTS_IDLE_NotGenerated \ - (0x0UL) /*!< Event not generated */ + (0x0UL) /*!< Event not generated */ #define QSPI_EVENTS_IDLE_EVENTS_IDLE_Generated \ - (0x1UL) /*!< Event generated */ + (0x1UL) /*!< Event generated */ /* QSPI_SHORTS: Shortcuts between local events and tasks */ #define QSPI_SHORTS_ResetValue \ - (0x00000000UL) /*!< Reset value of SHORTS register. */ + (0x00000000UL) /*!< Reset value of SHORTS register. */ /* DMA_DONE_START @Bit 0 : Shortcut between event DMA.DONE and task START */ #define QSPI_SHORTS_DMA_DONE_START_Pos \ - (0UL) /*!< Position of DMA_DONE_START field. */ + (0UL) /*!< Position of DMA_DONE_START field. */ #define QSPI_SHORTS_DMA_DONE_START_Msk \ - (0x1UL << QSPI_SHORTS_DMA_DONE_START_Pos) /*!< Bit mask of DMA_DONE_START field. */ + (0x1UL << QSPI_SHORTS_DMA_DONE_START_Pos) /*!< Bit mask of DMA_DONE_START field. */ #define QSPI_SHORTS_DMA_DONE_START_Min \ - (0x0UL) /*!< Min enumerator value of DMA_DONE_START field. */ + (0x0UL) /*!< Min enumerator value of DMA_DONE_START field. */ #define QSPI_SHORTS_DMA_DONE_START_Max \ - (0x1UL) /*!< Max enumerator value of DMA_DONE_START field. */ + (0x1UL) /*!< Max enumerator value of DMA_DONE_START field. */ #define QSPI_SHORTS_DMA_DONE_START_Disabled \ - (0x0UL) /*!< Disable shortcut */ + (0x0UL) /*!< Disable shortcut */ #define QSPI_SHORTS_DMA_DONE_START_Enabled \ - (0x1UL) /*!< Enable shortcut */ + (0x1UL) /*!< Enable shortcut */ /* QSPI_INTEN: Enable or disable interrupt */ #define QSPI_INTEN_ResetValue \ - (0x00000000UL) /*!< Reset value of INTEN register. */ + (0x00000000UL) /*!< Reset value of INTEN register. */ /* CORE @Bit 0 : Enable or disable interrupt for event CORE */ -#define QSPI_INTEN_CORE_Pos (0UL) /*!< Position of CORE field. */ +#define QSPI_INTEN_CORE_Pos (0UL) /*!< Position of CORE field. */ #define QSPI_INTEN_CORE_Msk \ - (0x1UL << QSPI_INTEN_CORE_Pos) /*!< Bit mask of CORE field. */ -#define QSPI_INTEN_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ -#define QSPI_INTEN_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ -#define QSPI_INTEN_CORE_Disabled (0x0UL) /*!< Disable */ -#define QSPI_INTEN_CORE_Enabled (0x1UL) /*!< Enable */ + (0x1UL << QSPI_INTEN_CORE_Pos) /*!< Bit mask of CORE field. */ +#define QSPI_INTEN_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ +#define QSPI_INTEN_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ +#define QSPI_INTEN_CORE_Disabled (0x0UL) /*!< Disable */ +#define QSPI_INTEN_CORE_Enabled (0x1UL) /*!< Enable */ /* DMADONELIST @Bit 1 : Enable or disable interrupt for event DMADONELIST */ -#define QSPI_INTEN_DMADONELIST_Pos (1UL) /*!< Position of DMADONELIST field. */ +#define QSPI_INTEN_DMADONELIST_Pos (1UL) /*!< Position of DMADONELIST field. */ #define QSPI_INTEN_DMADONELIST_Msk \ - (0x1UL << QSPI_INTEN_DMADONELIST_Pos) /*!< Bit mask of DMADONELIST field. */ -#define QSPI_INTEN_DMADONELIST_Min (0x0UL) /*!< Min enumerator value of DMADONELIST field. */ -#define QSPI_INTEN_DMADONELIST_Max (0x1UL) /*!< Max enumerator value of DMADONELIST field. */ + (0x1UL << QSPI_INTEN_DMADONELIST_Pos) /*!< Bit mask of DMADONELIST field. */ +#define QSPI_INTEN_DMADONELIST_Min (0x0UL) /*!< Min enumerator value of DMADONELIST field. */ +#define QSPI_INTEN_DMADONELIST_Max (0x1UL) /*!< Max enumerator value of DMADONELIST field. */ #define QSPI_INTEN_DMADONELIST_Disabled \ - (0x0UL) /*!< Disable */ + (0x0UL) /*!< Disable */ #define QSPI_INTEN_DMADONELIST_Enabled \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ /* DMADONELISTPART @Bit 2 : Enable or disable interrupt for event DMADONELISTPART */ #define QSPI_INTEN_DMADONELISTPART_Pos \ - (2UL) /*!< Position of DMADONELISTPART field. */ + (2UL) /*!< Position of DMADONELISTPART field. */ #define QSPI_INTEN_DMADONELISTPART_Msk \ - (0x1UL << QSPI_INTEN_DMADONELISTPART_Pos) /*!< Bit mask of DMADONELISTPART field. */ + (0x1UL << QSPI_INTEN_DMADONELISTPART_Pos) /*!< Bit mask of DMADONELISTPART field. */ #define QSPI_INTEN_DMADONELISTPART_Min \ - (0x0UL) /*!< Min enumerator value of DMADONELISTPART field. */ + (0x0UL) /*!< Min enumerator value of DMADONELISTPART field. */ #define QSPI_INTEN_DMADONELISTPART_Max \ - (0x1UL) /*!< Max enumerator value of DMADONELISTPART field. */ + (0x1UL) /*!< Max enumerator value of DMADONELISTPART field. */ #define QSPI_INTEN_DMADONELISTPART_Disabled \ - (0x0UL) /*!< Disable */ + (0x0UL) /*!< Disable */ #define QSPI_INTEN_DMADONELISTPART_Enabled \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ /* DMADONESELECTJOB @Bit 3 : Enable or disable interrupt for event DMADONESELECTJOB */ #define QSPI_INTEN_DMADONESELECTJOB_Pos \ - (3UL) /*!< Position of DMADONESELECTJOB field. */ + (3UL) /*!< Position of DMADONESELECTJOB field. */ #define QSPI_INTEN_DMADONESELECTJOB_Msk \ - (0x1UL << QSPI_INTEN_DMADONESELECTJOB_Pos) /*!< Bit mask of DMADONESELECTJOB field. */ + (0x1UL << QSPI_INTEN_DMADONESELECTJOB_Pos) /*!< Bit mask of DMADONESELECTJOB field. */ #define QSPI_INTEN_DMADONESELECTJOB_Min \ - (0x0UL) /*!< Min enumerator value of DMADONESELECTJOB field. */ + (0x0UL) /*!< Min enumerator value of DMADONESELECTJOB field. */ #define QSPI_INTEN_DMADONESELECTJOB_Max \ - (0x1UL) /*!< Max enumerator value of DMADONESELECTJOB field. */ + (0x1UL) /*!< Max enumerator value of DMADONESELECTJOB field. */ #define QSPI_INTEN_DMADONESELECTJOB_Disabled \ - (0x0UL) /*!< Disable */ + (0x0UL) /*!< Disable */ #define QSPI_INTEN_DMADONESELECTJOB_Enabled \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ /* DMADONEDATA @Bit 4 : Enable or disable interrupt for event DMADONEDATA */ -#define QSPI_INTEN_DMADONEDATA_Pos (4UL) /*!< Position of DMADONEDATA field. */ +#define QSPI_INTEN_DMADONEDATA_Pos (4UL) /*!< Position of DMADONEDATA field. */ #define QSPI_INTEN_DMADONEDATA_Msk \ - (0x1UL << QSPI_INTEN_DMADONEDATA_Pos) /*!< Bit mask of DMADONEDATA field. */ -#define QSPI_INTEN_DMADONEDATA_Min (0x0UL) /*!< Min enumerator value of DMADONEDATA field. */ -#define QSPI_INTEN_DMADONEDATA_Max (0x1UL) /*!< Max enumerator value of DMADONEDATA field. */ + (0x1UL << QSPI_INTEN_DMADONEDATA_Pos) /*!< Bit mask of DMADONEDATA field. */ +#define QSPI_INTEN_DMADONEDATA_Min (0x0UL) /*!< Min enumerator value of DMADONEDATA field. */ +#define QSPI_INTEN_DMADONEDATA_Max (0x1UL) /*!< Max enumerator value of DMADONEDATA field. */ #define QSPI_INTEN_DMADONEDATA_Disabled \ - (0x0UL) /*!< Disable */ + (0x0UL) /*!< Disable */ #define QSPI_INTEN_DMADONEDATA_Enabled \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ /* DMADONEJOB @Bit 5 : Enable or disable interrupt for event DMADONEJOB */ -#define QSPI_INTEN_DMADONEJOB_Pos (5UL) /*!< Position of DMADONEJOB field. */ +#define QSPI_INTEN_DMADONEJOB_Pos (5UL) /*!< Position of DMADONEJOB field. */ #define QSPI_INTEN_DMADONEJOB_Msk \ - (0x1UL << QSPI_INTEN_DMADONEJOB_Pos) /*!< Bit mask of DMADONEJOB field. */ -#define QSPI_INTEN_DMADONEJOB_Min (0x0UL) /*!< Min enumerator value of DMADONEJOB field. */ -#define QSPI_INTEN_DMADONEJOB_Max (0x1UL) /*!< Max enumerator value of DMADONEJOB field. */ + (0x1UL << QSPI_INTEN_DMADONEJOB_Pos) /*!< Bit mask of DMADONEJOB field. */ +#define QSPI_INTEN_DMADONEJOB_Min (0x0UL) /*!< Min enumerator value of DMADONEJOB field. */ +#define QSPI_INTEN_DMADONEJOB_Max (0x1UL) /*!< Max enumerator value of DMADONEJOB field. */ #define QSPI_INTEN_DMADONEJOB_Disabled \ - (0x0UL) /*!< Disable */ + (0x0UL) /*!< Disable */ #define QSPI_INTEN_DMADONEJOB_Enabled \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ /* DMAERROR @Bit 6 : Enable or disable interrupt for event DMAERROR */ -#define QSPI_INTEN_DMAERROR_Pos (6UL) /*!< Position of DMAERROR field. */ +#define QSPI_INTEN_DMAERROR_Pos (6UL) /*!< Position of DMAERROR field. */ #define QSPI_INTEN_DMAERROR_Msk \ - (0x1UL << QSPI_INTEN_DMAERROR_Pos) /*!< Bit mask of DMAERROR field. */ -#define QSPI_INTEN_DMAERROR_Min (0x0UL) /*!< Min enumerator value of DMAERROR field. */ -#define QSPI_INTEN_DMAERROR_Max (0x1UL) /*!< Max enumerator value of DMAERROR field. */ + (0x1UL << QSPI_INTEN_DMAERROR_Pos) /*!< Bit mask of DMAERROR field. */ +#define QSPI_INTEN_DMAERROR_Min (0x0UL) /*!< Min enumerator value of DMAERROR field. */ +#define QSPI_INTEN_DMAERROR_Max (0x1UL) /*!< Max enumerator value of DMAERROR field. */ #define QSPI_INTEN_DMAERROR_Disabled \ - (0x0UL) /*!< Disable */ -#define QSPI_INTEN_DMAERROR_Enabled (0x1UL) /*!< Enable */ + (0x0UL) /*!< Disable */ +#define QSPI_INTEN_DMAERROR_Enabled (0x1UL) /*!< Enable */ /* DMAPAUSED @Bit 7 : Enable or disable interrupt for event DMAPAUSED */ -#define QSPI_INTEN_DMAPAUSED_Pos (7UL) /*!< Position of DMAPAUSED field. */ +#define QSPI_INTEN_DMAPAUSED_Pos (7UL) /*!< Position of DMAPAUSED field. */ #define QSPI_INTEN_DMAPAUSED_Msk \ - (0x1UL << QSPI_INTEN_DMAPAUSED_Pos) /*!< Bit mask of DMAPAUSED field. */ -#define QSPI_INTEN_DMAPAUSED_Min (0x0UL) /*!< Min enumerator value of DMAPAUSED field. */ -#define QSPI_INTEN_DMAPAUSED_Max (0x1UL) /*!< Max enumerator value of DMAPAUSED field. */ + (0x1UL << QSPI_INTEN_DMAPAUSED_Pos) /*!< Bit mask of DMAPAUSED field. */ +#define QSPI_INTEN_DMAPAUSED_Min (0x0UL) /*!< Min enumerator value of DMAPAUSED field. */ +#define QSPI_INTEN_DMAPAUSED_Max (0x1UL) /*!< Max enumerator value of DMAPAUSED field. */ #define QSPI_INTEN_DMAPAUSED_Disabled \ - (0x0UL) /*!< Disable */ + (0x0UL) /*!< Disable */ #define QSPI_INTEN_DMAPAUSED_Enabled \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ /* DMARESET @Bit 8 : Enable or disable interrupt for event DMARESET */ -#define QSPI_INTEN_DMARESET_Pos (8UL) /*!< Position of DMARESET field. */ +#define QSPI_INTEN_DMARESET_Pos (8UL) /*!< Position of DMARESET field. */ #define QSPI_INTEN_DMARESET_Msk \ - (0x1UL << QSPI_INTEN_DMARESET_Pos) /*!< Bit mask of DMARESET field. */ -#define QSPI_INTEN_DMARESET_Min (0x0UL) /*!< Min enumerator value of DMARESET field. */ -#define QSPI_INTEN_DMARESET_Max (0x1UL) /*!< Max enumerator value of DMARESET field. */ + (0x1UL << QSPI_INTEN_DMARESET_Pos) /*!< Bit mask of DMARESET field. */ +#define QSPI_INTEN_DMARESET_Min (0x0UL) /*!< Min enumerator value of DMARESET field. */ +#define QSPI_INTEN_DMARESET_Max (0x1UL) /*!< Max enumerator value of DMARESET field. */ #define QSPI_INTEN_DMARESET_Disabled \ - (0x0UL) /*!< Disable */ -#define QSPI_INTEN_DMARESET_Enabled (0x1UL) /*!< Enable */ + (0x0UL) /*!< Disable */ +#define QSPI_INTEN_DMARESET_Enabled (0x1UL) /*!< Enable */ /* DMADONE @Bit 9 : Enable or disable interrupt for event DMADONE */ -#define QSPI_INTEN_DMADONE_Pos (9UL) /*!< Position of DMADONE field. */ +#define QSPI_INTEN_DMADONE_Pos (9UL) /*!< Position of DMADONE field. */ #define QSPI_INTEN_DMADONE_Msk \ - (0x1UL << QSPI_INTEN_DMADONE_Pos) /*!< Bit mask of DMADONE field. */ -#define QSPI_INTEN_DMADONE_Min (0x0UL) /*!< Min enumerator value of DMADONE field. */ -#define QSPI_INTEN_DMADONE_Max (0x1UL) /*!< Max enumerator value of DMADONE field. */ -#define QSPI_INTEN_DMADONE_Disabled (0x0UL) /*!< Disable */ -#define QSPI_INTEN_DMADONE_Enabled (0x1UL) /*!< Enable */ + (0x1UL << QSPI_INTEN_DMADONE_Pos) /*!< Bit mask of DMADONE field. */ +#define QSPI_INTEN_DMADONE_Min (0x0UL) /*!< Min enumerator value of DMADONE field. */ +#define QSPI_INTEN_DMADONE_Max (0x1UL) /*!< Max enumerator value of DMADONE field. */ +#define QSPI_INTEN_DMADONE_Disabled (0x0UL) /*!< Disable */ +#define QSPI_INTEN_DMADONE_Enabled (0x1UL) /*!< Enable */ /* DMATXUNEXPECTEDIDLE @Bit 10 : Enable or disable interrupt for event DMATXUNEXPECTEDIDLE */ #define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Pos \ - (10UL) /*!< Position of DMATXUNEXPECTEDIDLE field. */ + (10UL) /*!< Position of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Msk \ - (0x1UL << QSPI_INTEN_DMATXUNEXPECTEDIDLE_Pos) /*!< Bit mask of DMATXUNEXPECTEDIDLE - * field.*/ + (0x1UL << QSPI_INTEN_DMATXUNEXPECTEDIDLE_Pos) /*!< Bit mask of DMATXUNEXPECTEDIDLE + * field.*/ #define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Min \ - (0x0UL) /*!< Min enumerator value of DMATXUNEXPECTEDIDLE field. */ + (0x0UL) /*!< Min enumerator value of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Max \ - (0x1UL) /*!< Max enumerator value of DMATXUNEXPECTEDIDLE field. */ + (0x1UL) /*!< Max enumerator value of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Disabled \ - (0x0UL) /*!< Disable */ + (0x0UL) /*!< Disable */ #define QSPI_INTEN_DMATXUNEXPECTEDIDLE_Enabled \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ /* DMAINTERNALBUSERROR @Bit 11 : Enable or disable interrupt for event DMAINTERNALBUSERROR */ #define QSPI_INTEN_DMAINTERNALBUSERROR_Pos \ - (11UL) /*!< Position of DMAINTERNALBUSERROR field. */ + (11UL) /*!< Position of DMAINTERNALBUSERROR field. */ #define QSPI_INTEN_DMAINTERNALBUSERROR_Msk \ - (0x1UL << QSPI_INTEN_DMAINTERNALBUSERROR_Pos) /*!< Bit mask of DMAINTERNALBUSERROR - * field.*/ + (0x1UL << QSPI_INTEN_DMAINTERNALBUSERROR_Pos) /*!< Bit mask of DMAINTERNALBUSERROR + * field.*/ #define QSPI_INTEN_DMAINTERNALBUSERROR_Min \ - (0x0UL) /*!< Min enumerator value of DMAINTERNALBUSERROR field. */ + (0x0UL) /*!< Min enumerator value of DMAINTERNALBUSERROR field. */ #define QSPI_INTEN_DMAINTERNALBUSERROR_Max \ - (0x1UL) /*!< Max enumerator value of DMAINTERNALBUSERROR field. */ + (0x1UL) /*!< Max enumerator value of DMAINTERNALBUSERROR field. */ #define QSPI_INTEN_DMAINTERNALBUSERROR_Disabled \ - (0x0UL) /*!< Disable */ + (0x0UL) /*!< Disable */ #define QSPI_INTEN_DMAINTERNALBUSERROR_Enabled \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ /* DMAABORTED @Bit 12 : Enable or disable interrupt for event DMAABORTED */ -#define QSPI_INTEN_DMAABORTED_Pos (12UL) /*!< Position of DMAABORTED field. */ +#define QSPI_INTEN_DMAABORTED_Pos (12UL) /*!< Position of DMAABORTED field. */ #define QSPI_INTEN_DMAABORTED_Msk \ - (0x1UL << QSPI_INTEN_DMAABORTED_Pos) /*!< Bit mask of DMAABORTED field. */ -#define QSPI_INTEN_DMAABORTED_Min (0x0UL) /*!< Min enumerator value of DMAABORTED field. */ -#define QSPI_INTEN_DMAABORTED_Max (0x1UL) /*!< Max enumerator value of DMAABORTED field. */ + (0x1UL << QSPI_INTEN_DMAABORTED_Pos) /*!< Bit mask of DMAABORTED field. */ +#define QSPI_INTEN_DMAABORTED_Min (0x0UL) /*!< Min enumerator value of DMAABORTED field. */ +#define QSPI_INTEN_DMAABORTED_Max (0x1UL) /*!< Max enumerator value of DMAABORTED field. */ #define QSPI_INTEN_DMAABORTED_Disabled \ - (0x0UL) /*!< Disable */ + (0x0UL) /*!< Disable */ #define QSPI_INTEN_DMAABORTED_Enabled \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ /* IDLE @Bit 13 : Enable or disable interrupt for event IDLE */ -#define QSPI_INTEN_IDLE_Pos (13UL) /*!< Position of IDLE field. */ +#define QSPI_INTEN_IDLE_Pos (13UL) /*!< Position of IDLE field. */ #define QSPI_INTEN_IDLE_Msk \ - (0x1UL << QSPI_INTEN_IDLE_Pos) /*!< Bit mask of IDLE field. */ -#define QSPI_INTEN_IDLE_Min (0x0UL) /*!< Min enumerator value of IDLE field. */ -#define QSPI_INTEN_IDLE_Max (0x1UL) /*!< Max enumerator value of IDLE field. */ -#define QSPI_INTEN_IDLE_Disabled (0x0UL) /*!< Disable */ -#define QSPI_INTEN_IDLE_Enabled (0x1UL) /*!< Enable */ + (0x1UL << QSPI_INTEN_IDLE_Pos) /*!< Bit mask of IDLE field. */ +#define QSPI_INTEN_IDLE_Min (0x0UL) /*!< Min enumerator value of IDLE field. */ +#define QSPI_INTEN_IDLE_Max (0x1UL) /*!< Max enumerator value of IDLE field. */ +#define QSPI_INTEN_IDLE_Disabled (0x0UL) /*!< Disable */ +#define QSPI_INTEN_IDLE_Enabled (0x1UL) /*!< Enable */ /* QSPI_INTENSET: Enable interrupt */ #define QSPI_INTENSET_ResetValue \ - (0x00000000UL) /*!< Reset value of INTENSET register. */ + (0x00000000UL) /*!< Reset value of INTENSET register. */ /* CORE @Bit 0 : Write '1' to enable interrupt for event CORE */ -#define QSPI_INTENSET_CORE_Pos (0UL) /*!< Position of CORE field. */ +#define QSPI_INTENSET_CORE_Pos (0UL) /*!< Position of CORE field. */ #define QSPI_INTENSET_CORE_Msk \ - (0x1UL << QSPI_INTENSET_CORE_Pos) /*!< Bit mask of CORE field. */ -#define QSPI_INTENSET_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ -#define QSPI_INTENSET_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ -#define QSPI_INTENSET_CORE_Set (0x1UL) /*!< Enable */ -#define QSPI_INTENSET_CORE_Disabled (0x0UL) /*!< Read: Disabled */ -#define QSPI_INTENSET_CORE_Enabled (0x1UL) /*!< Read: Enabled */ + (0x1UL << QSPI_INTENSET_CORE_Pos) /*!< Bit mask of CORE field. */ +#define QSPI_INTENSET_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ +#define QSPI_INTENSET_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ +#define QSPI_INTENSET_CORE_Set (0x1UL) /*!< Enable */ +#define QSPI_INTENSET_CORE_Disabled (0x0UL) /*!< Read: Disabled */ +#define QSPI_INTENSET_CORE_Enabled (0x1UL) /*!< Read: Enabled */ /* DMADONELIST @Bit 1 : Write '1' to enable interrupt for event DMADONELIST */ -#define QSPI_INTENSET_DMADONELIST_Pos (1UL) /*!< Position of DMADONELIST field. */ +#define QSPI_INTENSET_DMADONELIST_Pos (1UL) /*!< Position of DMADONELIST field. */ #define QSPI_INTENSET_DMADONELIST_Msk \ - (0x1UL << QSPI_INTENSET_DMADONELIST_Pos) /*!< Bit mask of DMADONELIST field. */ + (0x1UL << QSPI_INTENSET_DMADONELIST_Pos) /*!< Bit mask of DMADONELIST field. */ #define QSPI_INTENSET_DMADONELIST_Min \ - (0x0UL) /*!< Min enumerator value of DMADONELIST field. */ + (0x0UL) /*!< Min enumerator value of DMADONELIST field. */ #define QSPI_INTENSET_DMADONELIST_Max \ - (0x1UL) /*!< Max enumerator value of DMADONELIST field. */ + (0x1UL) /*!< Max enumerator value of DMADONELIST field. */ #define QSPI_INTENSET_DMADONELIST_Set \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMADONELIST_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMADONELIST_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMADONELISTPART @Bit 2 : Write '1' to enable interrupt for event DMADONELISTPART */ #define QSPI_INTENSET_DMADONELISTPART_Pos \ - (2UL) /*!< Position of DMADONELISTPART field. */ + (2UL) /*!< Position of DMADONELISTPART field. */ #define QSPI_INTENSET_DMADONELISTPART_Msk \ - (0x1UL << QSPI_INTENSET_DMADONELISTPART_Pos) /*!< Bit mask of DMADONELISTPART - * field.*/ + (0x1UL << QSPI_INTENSET_DMADONELISTPART_Pos) /*!< Bit mask of DMADONELISTPART + * field.*/ #define QSPI_INTENSET_DMADONELISTPART_Min \ - (0x0UL) /*!< Min enumerator value of DMADONELISTPART field. */ + (0x0UL) /*!< Min enumerator value of DMADONELISTPART field. */ #define QSPI_INTENSET_DMADONELISTPART_Max \ - (0x1UL) /*!< Max enumerator value of DMADONELISTPART field. */ + (0x1UL) /*!< Max enumerator value of DMADONELISTPART field. */ #define QSPI_INTENSET_DMADONELISTPART_Set \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMADONELISTPART_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMADONELISTPART_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMADONESELECTJOB @Bit 3 : Write '1' to enable interrupt for event DMADONESELECTJOB */ #define QSPI_INTENSET_DMADONESELECTJOB_Pos \ - (3UL) /*!< Position of DMADONESELECTJOB field. */ + (3UL) /*!< Position of DMADONESELECTJOB field. */ #define QSPI_INTENSET_DMADONESELECTJOB_Msk \ - (0x1UL << QSPI_INTENSET_DMADONESELECTJOB_Pos) /*!< Bit mask of DMADONESELECTJOB - * field.*/ + (0x1UL << QSPI_INTENSET_DMADONESELECTJOB_Pos) /*!< Bit mask of DMADONESELECTJOB + * field.*/ #define QSPI_INTENSET_DMADONESELECTJOB_Min \ - (0x0UL) /*!< Min enumerator value of DMADONESELECTJOB field. */ + (0x0UL) /*!< Min enumerator value of DMADONESELECTJOB field. */ #define QSPI_INTENSET_DMADONESELECTJOB_Max \ - (0x1UL) /*!< Max enumerator value of DMADONESELECTJOB field. */ + (0x1UL) /*!< Max enumerator value of DMADONESELECTJOB field. */ #define QSPI_INTENSET_DMADONESELECTJOB_Set \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMADONESELECTJOB_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMADONESELECTJOB_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMADONEDATA @Bit 4 : Write '1' to enable interrupt for event DMADONEDATA */ -#define QSPI_INTENSET_DMADONEDATA_Pos (4UL) /*!< Position of DMADONEDATA field. */ +#define QSPI_INTENSET_DMADONEDATA_Pos (4UL) /*!< Position of DMADONEDATA field. */ #define QSPI_INTENSET_DMADONEDATA_Msk \ - (0x1UL << QSPI_INTENSET_DMADONEDATA_Pos) /*!< Bit mask of DMADONEDATA field. */ + (0x1UL << QSPI_INTENSET_DMADONEDATA_Pos) /*!< Bit mask of DMADONEDATA field. */ #define QSPI_INTENSET_DMADONEDATA_Min \ - (0x0UL) /*!< Min enumerator value of DMADONEDATA field. */ + (0x0UL) /*!< Min enumerator value of DMADONEDATA field. */ #define QSPI_INTENSET_DMADONEDATA_Max \ - (0x1UL) /*!< Max enumerator value of DMADONEDATA field. */ + (0x1UL) /*!< Max enumerator value of DMADONEDATA field. */ #define QSPI_INTENSET_DMADONEDATA_Set \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMADONEDATA_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMADONEDATA_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMADONEJOB @Bit 5 : Write '1' to enable interrupt for event DMADONEJOB */ -#define QSPI_INTENSET_DMADONEJOB_Pos (5UL) /*!< Position of DMADONEJOB field. */ +#define QSPI_INTENSET_DMADONEJOB_Pos (5UL) /*!< Position of DMADONEJOB field. */ #define QSPI_INTENSET_DMADONEJOB_Msk \ - (0x1UL << QSPI_INTENSET_DMADONEJOB_Pos) /*!< Bit mask of DMADONEJOB field. */ + (0x1UL << QSPI_INTENSET_DMADONEJOB_Pos) /*!< Bit mask of DMADONEJOB field. */ #define QSPI_INTENSET_DMADONEJOB_Min \ - (0x0UL) /*!< Min enumerator value of DMADONEJOB field. */ + (0x0UL) /*!< Min enumerator value of DMADONEJOB field. */ #define QSPI_INTENSET_DMADONEJOB_Max \ - (0x1UL) /*!< Max enumerator value of DMADONEJOB field. */ + (0x1UL) /*!< Max enumerator value of DMADONEJOB field. */ #define QSPI_INTENSET_DMADONEJOB_Set \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMADONEJOB_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMADONEJOB_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMAERROR @Bit 6 : Write '1' to enable interrupt for event DMAERROR */ -#define QSPI_INTENSET_DMAERROR_Pos (6UL) /*!< Position of DMAERROR field. */ +#define QSPI_INTENSET_DMAERROR_Pos (6UL) /*!< Position of DMAERROR field. */ #define QSPI_INTENSET_DMAERROR_Msk \ - (0x1UL << QSPI_INTENSET_DMAERROR_Pos) /*!< Bit mask of DMAERROR field. */ -#define QSPI_INTENSET_DMAERROR_Min (0x0UL) /*!< Min enumerator value of DMAERROR field. */ -#define QSPI_INTENSET_DMAERROR_Max (0x1UL) /*!< Max enumerator value of DMAERROR field. */ -#define QSPI_INTENSET_DMAERROR_Set (0x1UL) /*!< Enable */ + (0x1UL << QSPI_INTENSET_DMAERROR_Pos) /*!< Bit mask of DMAERROR field. */ +#define QSPI_INTENSET_DMAERROR_Min (0x0UL) /*!< Min enumerator value of DMAERROR field. */ +#define QSPI_INTENSET_DMAERROR_Max (0x1UL) /*!< Max enumerator value of DMAERROR field. */ +#define QSPI_INTENSET_DMAERROR_Set (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMAERROR_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMAERROR_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMAPAUSED @Bit 7 : Write '1' to enable interrupt for event DMAPAUSED */ -#define QSPI_INTENSET_DMAPAUSED_Pos (7UL) /*!< Position of DMAPAUSED field. */ +#define QSPI_INTENSET_DMAPAUSED_Pos (7UL) /*!< Position of DMAPAUSED field. */ #define QSPI_INTENSET_DMAPAUSED_Msk \ - (0x1UL << QSPI_INTENSET_DMAPAUSED_Pos) /*!< Bit mask of DMAPAUSED field. */ -#define QSPI_INTENSET_DMAPAUSED_Min (0x0UL) /*!< Min enumerator value of DMAPAUSED field. */ -#define QSPI_INTENSET_DMAPAUSED_Max (0x1UL) /*!< Max enumerator value of DMAPAUSED field. */ -#define QSPI_INTENSET_DMAPAUSED_Set (0x1UL) /*!< Enable */ + (0x1UL << QSPI_INTENSET_DMAPAUSED_Pos) /*!< Bit mask of DMAPAUSED field. */ +#define QSPI_INTENSET_DMAPAUSED_Min (0x0UL) /*!< Min enumerator value of DMAPAUSED field. */ +#define QSPI_INTENSET_DMAPAUSED_Max (0x1UL) /*!< Max enumerator value of DMAPAUSED field. */ +#define QSPI_INTENSET_DMAPAUSED_Set (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMAPAUSED_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMAPAUSED_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMARESET @Bit 8 : Write '1' to enable interrupt for event DMARESET */ -#define QSPI_INTENSET_DMARESET_Pos (8UL) /*!< Position of DMARESET field. */ +#define QSPI_INTENSET_DMARESET_Pos (8UL) /*!< Position of DMARESET field. */ #define QSPI_INTENSET_DMARESET_Msk \ - (0x1UL << QSPI_INTENSET_DMARESET_Pos) /*!< Bit mask of DMARESET field. */ -#define QSPI_INTENSET_DMARESET_Min (0x0UL) /*!< Min enumerator value of DMARESET field. */ -#define QSPI_INTENSET_DMARESET_Max (0x1UL) /*!< Max enumerator value of DMARESET field. */ -#define QSPI_INTENSET_DMARESET_Set (0x1UL) /*!< Enable */ + (0x1UL << QSPI_INTENSET_DMARESET_Pos) /*!< Bit mask of DMARESET field. */ +#define QSPI_INTENSET_DMARESET_Min (0x0UL) /*!< Min enumerator value of DMARESET field. */ +#define QSPI_INTENSET_DMARESET_Max (0x1UL) /*!< Max enumerator value of DMARESET field. */ +#define QSPI_INTENSET_DMARESET_Set (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMARESET_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMARESET_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMADONE @Bit 9 : Write '1' to enable interrupt for event DMADONE */ -#define QSPI_INTENSET_DMADONE_Pos (9UL) /*!< Position of DMADONE field. */ +#define QSPI_INTENSET_DMADONE_Pos (9UL) /*!< Position of DMADONE field. */ #define QSPI_INTENSET_DMADONE_Msk \ - (0x1UL << QSPI_INTENSET_DMADONE_Pos) /*!< Bit mask of DMADONE field. */ -#define QSPI_INTENSET_DMADONE_Min (0x0UL) /*!< Min enumerator value of DMADONE field. */ -#define QSPI_INTENSET_DMADONE_Max (0x1UL) /*!< Max enumerator value of DMADONE field. */ -#define QSPI_INTENSET_DMADONE_Set (0x1UL) /*!< Enable */ + (0x1UL << QSPI_INTENSET_DMADONE_Pos) /*!< Bit mask of DMADONE field. */ +#define QSPI_INTENSET_DMADONE_Min (0x0UL) /*!< Min enumerator value of DMADONE field. */ +#define QSPI_INTENSET_DMADONE_Max (0x1UL) /*!< Max enumerator value of DMADONE field. */ +#define QSPI_INTENSET_DMADONE_Set (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMADONE_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMADONE_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMATXUNEXPECTEDIDLE @Bit 10 : Write '1' to enable interrupt for event DMATXUNEXPECTEDIDLE */ #define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Pos \ - (10UL) /*!< Position of DMATXUNEXPECTEDIDLE field. */ + (10UL) /*!< Position of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Msk \ - (0x1UL << QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Pos) /*!< Bit mask of - * DMATXUNEXPECTEDIDLE field.*/ + (0x1UL << QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Pos) /*!< Bit mask of + * DMATXUNEXPECTEDIDLE field.*/ #define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Min \ - (0x0UL) /*!< Min enumerator value of DMATXUNEXPECTEDIDLE field. */ + (0x0UL) /*!< Min enumerator value of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Max \ - (0x1UL) /*!< Max enumerator value of DMATXUNEXPECTEDIDLE field. */ + (0x1UL) /*!< Max enumerator value of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Set \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMATXUNEXPECTEDIDLE_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMAINTERNALBUSERROR @Bit 11 : Write '1' to enable interrupt for event DMAINTERNALBUSERROR */ #define QSPI_INTENSET_DMAINTERNALBUSERROR_Pos \ - (11UL) /*!< Position of DMAINTERNALBUSERROR field. */ + (11UL) /*!< Position of DMAINTERNALBUSERROR field. */ #define QSPI_INTENSET_DMAINTERNALBUSERROR_Msk \ - (0x1UL << QSPI_INTENSET_DMAINTERNALBUSERROR_Pos) /*!< Bit mask of - * DMAINTERNALBUSERROR field.*/ + (0x1UL << QSPI_INTENSET_DMAINTERNALBUSERROR_Pos) /*!< Bit mask of + * DMAINTERNALBUSERROR field.*/ #define QSPI_INTENSET_DMAINTERNALBUSERROR_Min \ - (0x0UL) /*!< Min enumerator value of DMAINTERNALBUSERROR field. */ + (0x0UL) /*!< Min enumerator value of DMAINTERNALBUSERROR field. */ #define QSPI_INTENSET_DMAINTERNALBUSERROR_Max \ - (0x1UL) /*!< Max enumerator value of DMAINTERNALBUSERROR field. */ + (0x1UL) /*!< Max enumerator value of DMAINTERNALBUSERROR field. */ #define QSPI_INTENSET_DMAINTERNALBUSERROR_Set \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMAINTERNALBUSERROR_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMAINTERNALBUSERROR_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMAABORTED @Bit 12 : Write '1' to enable interrupt for event DMAABORTED */ -#define QSPI_INTENSET_DMAABORTED_Pos (12UL) /*!< Position of DMAABORTED field. */ +#define QSPI_INTENSET_DMAABORTED_Pos (12UL) /*!< Position of DMAABORTED field. */ #define QSPI_INTENSET_DMAABORTED_Msk \ - (0x1UL << QSPI_INTENSET_DMAABORTED_Pos) /*!< Bit mask of DMAABORTED field. */ + (0x1UL << QSPI_INTENSET_DMAABORTED_Pos) /*!< Bit mask of DMAABORTED field. */ #define QSPI_INTENSET_DMAABORTED_Min \ - (0x0UL) /*!< Min enumerator value of DMAABORTED field. */ + (0x0UL) /*!< Min enumerator value of DMAABORTED field. */ #define QSPI_INTENSET_DMAABORTED_Max \ - (0x1UL) /*!< Max enumerator value of DMAABORTED field. */ + (0x1UL) /*!< Max enumerator value of DMAABORTED field. */ #define QSPI_INTENSET_DMAABORTED_Set \ - (0x1UL) /*!< Enable */ + (0x1UL) /*!< Enable */ #define QSPI_INTENSET_DMAABORTED_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENSET_DMAABORTED_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* IDLE @Bit 13 : Write '1' to enable interrupt for event IDLE */ -#define QSPI_INTENSET_IDLE_Pos (13UL) /*!< Position of IDLE field. */ +#define QSPI_INTENSET_IDLE_Pos (13UL) /*!< Position of IDLE field. */ #define QSPI_INTENSET_IDLE_Msk \ - (0x1UL << QSPI_INTENSET_IDLE_Pos) /*!< Bit mask of IDLE field. */ -#define QSPI_INTENSET_IDLE_Min (0x0UL) /*!< Min enumerator value of IDLE field. */ -#define QSPI_INTENSET_IDLE_Max (0x1UL) /*!< Max enumerator value of IDLE field. */ -#define QSPI_INTENSET_IDLE_Set (0x1UL) /*!< Enable */ -#define QSPI_INTENSET_IDLE_Disabled (0x0UL) /*!< Read: Disabled */ -#define QSPI_INTENSET_IDLE_Enabled (0x1UL) /*!< Read: Enabled */ + (0x1UL << QSPI_INTENSET_IDLE_Pos) /*!< Bit mask of IDLE field. */ +#define QSPI_INTENSET_IDLE_Min (0x0UL) /*!< Min enumerator value of IDLE field. */ +#define QSPI_INTENSET_IDLE_Max (0x1UL) /*!< Max enumerator value of IDLE field. */ +#define QSPI_INTENSET_IDLE_Set (0x1UL) /*!< Enable */ +#define QSPI_INTENSET_IDLE_Disabled (0x0UL) /*!< Read: Disabled */ +#define QSPI_INTENSET_IDLE_Enabled (0x1UL) /*!< Read: Enabled */ /* QSPI_INTENCLR: Disable interrupt */ #define QSPI_INTENCLR_ResetValue \ - (0x00000000UL) /*!< Reset value of INTENCLR register. */ + (0x00000000UL) /*!< Reset value of INTENCLR register. */ /* CORE @Bit 0 : Write '1' to disable interrupt for event CORE */ -#define QSPI_INTENCLR_CORE_Pos (0UL) /*!< Position of CORE field. */ +#define QSPI_INTENCLR_CORE_Pos (0UL) /*!< Position of CORE field. */ #define QSPI_INTENCLR_CORE_Msk \ - (0x1UL << QSPI_INTENCLR_CORE_Pos) /*!< Bit mask of CORE field. */ -#define QSPI_INTENCLR_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ -#define QSPI_INTENCLR_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ -#define QSPI_INTENCLR_CORE_Clear (0x1UL) /*!< Disable */ -#define QSPI_INTENCLR_CORE_Disabled (0x0UL) /*!< Read: Disabled */ -#define QSPI_INTENCLR_CORE_Enabled (0x1UL) /*!< Read: Enabled */ + (0x1UL << QSPI_INTENCLR_CORE_Pos) /*!< Bit mask of CORE field. */ +#define QSPI_INTENCLR_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ +#define QSPI_INTENCLR_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ +#define QSPI_INTENCLR_CORE_Clear (0x1UL) /*!< Disable */ +#define QSPI_INTENCLR_CORE_Disabled (0x0UL) /*!< Read: Disabled */ +#define QSPI_INTENCLR_CORE_Enabled (0x1UL) /*!< Read: Enabled */ /* DMADONELIST @Bit 1 : Write '1' to disable interrupt for event DMADONELIST */ -#define QSPI_INTENCLR_DMADONELIST_Pos (1UL) /*!< Position of DMADONELIST field. */ +#define QSPI_INTENCLR_DMADONELIST_Pos (1UL) /*!< Position of DMADONELIST field. */ #define QSPI_INTENCLR_DMADONELIST_Msk \ - (0x1UL << QSPI_INTENCLR_DMADONELIST_Pos) /*!< Bit mask of DMADONELIST field. */ + (0x1UL << QSPI_INTENCLR_DMADONELIST_Pos) /*!< Bit mask of DMADONELIST field. */ #define QSPI_INTENCLR_DMADONELIST_Min \ - (0x0UL) /*!< Min enumerator value of DMADONELIST field. */ + (0x0UL) /*!< Min enumerator value of DMADONELIST field. */ #define QSPI_INTENCLR_DMADONELIST_Max \ - (0x1UL) /*!< Max enumerator value of DMADONELIST field. */ + (0x1UL) /*!< Max enumerator value of DMADONELIST field. */ #define QSPI_INTENCLR_DMADONELIST_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMADONELIST_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMADONELIST_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMADONELISTPART @Bit 2 : Write '1' to disable interrupt for event DMADONELISTPART */ #define QSPI_INTENCLR_DMADONELISTPART_Pos \ - (2UL) /*!< Position of DMADONELISTPART field. */ + (2UL) /*!< Position of DMADONELISTPART field. */ #define QSPI_INTENCLR_DMADONELISTPART_Msk \ - (0x1UL << QSPI_INTENCLR_DMADONELISTPART_Pos) /*!< Bit mask of DMADONELISTPART - * field.*/ + (0x1UL << QSPI_INTENCLR_DMADONELISTPART_Pos) /*!< Bit mask of DMADONELISTPART + * field.*/ #define QSPI_INTENCLR_DMADONELISTPART_Min \ - (0x0UL) /*!< Min enumerator value of DMADONELISTPART field. */ + (0x0UL) /*!< Min enumerator value of DMADONELISTPART field. */ #define QSPI_INTENCLR_DMADONELISTPART_Max \ - (0x1UL) /*!< Max enumerator value of DMADONELISTPART field. */ + (0x1UL) /*!< Max enumerator value of DMADONELISTPART field. */ #define QSPI_INTENCLR_DMADONELISTPART_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMADONELISTPART_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMADONELISTPART_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMADONESELECTJOB @Bit 3 : Write '1' to disable interrupt for event DMADONESELECTJOB */ #define QSPI_INTENCLR_DMADONESELECTJOB_Pos \ - (3UL) /*!< Position of DMADONESELECTJOB field. */ + (3UL) /*!< Position of DMADONESELECTJOB field. */ #define QSPI_INTENCLR_DMADONESELECTJOB_Msk \ - (0x1UL << QSPI_INTENCLR_DMADONESELECTJOB_Pos) /*!< Bit mask of DMADONESELECTJOB - * field.*/ + (0x1UL << QSPI_INTENCLR_DMADONESELECTJOB_Pos) /*!< Bit mask of DMADONESELECTJOB + * field.*/ #define QSPI_INTENCLR_DMADONESELECTJOB_Min \ - (0x0UL) /*!< Min enumerator value of DMADONESELECTJOB field. */ + (0x0UL) /*!< Min enumerator value of DMADONESELECTJOB field. */ #define QSPI_INTENCLR_DMADONESELECTJOB_Max \ - (0x1UL) /*!< Max enumerator value of DMADONESELECTJOB field. */ + (0x1UL) /*!< Max enumerator value of DMADONESELECTJOB field. */ #define QSPI_INTENCLR_DMADONESELECTJOB_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMADONESELECTJOB_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMADONESELECTJOB_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMADONEDATA @Bit 4 : Write '1' to disable interrupt for event DMADONEDATA */ -#define QSPI_INTENCLR_DMADONEDATA_Pos (4UL) /*!< Position of DMADONEDATA field. */ +#define QSPI_INTENCLR_DMADONEDATA_Pos (4UL) /*!< Position of DMADONEDATA field. */ #define QSPI_INTENCLR_DMADONEDATA_Msk \ - (0x1UL << QSPI_INTENCLR_DMADONEDATA_Pos) /*!< Bit mask of DMADONEDATA field. */ + (0x1UL << QSPI_INTENCLR_DMADONEDATA_Pos) /*!< Bit mask of DMADONEDATA field. */ #define QSPI_INTENCLR_DMADONEDATA_Min \ - (0x0UL) /*!< Min enumerator value of DMADONEDATA field. */ + (0x0UL) /*!< Min enumerator value of DMADONEDATA field. */ #define QSPI_INTENCLR_DMADONEDATA_Max \ - (0x1UL) /*!< Max enumerator value of DMADONEDATA field. */ + (0x1UL) /*!< Max enumerator value of DMADONEDATA field. */ #define QSPI_INTENCLR_DMADONEDATA_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMADONEDATA_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMADONEDATA_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMADONEJOB @Bit 5 : Write '1' to disable interrupt for event DMADONEJOB */ -#define QSPI_INTENCLR_DMADONEJOB_Pos (5UL) /*!< Position of DMADONEJOB field. */ +#define QSPI_INTENCLR_DMADONEJOB_Pos (5UL) /*!< Position of DMADONEJOB field. */ #define QSPI_INTENCLR_DMADONEJOB_Msk \ - (0x1UL << QSPI_INTENCLR_DMADONEJOB_Pos) /*!< Bit mask of DMADONEJOB field. */ + (0x1UL << QSPI_INTENCLR_DMADONEJOB_Pos) /*!< Bit mask of DMADONEJOB field. */ #define QSPI_INTENCLR_DMADONEJOB_Min \ - (0x0UL) /*!< Min enumerator value of DMADONEJOB field. */ + (0x0UL) /*!< Min enumerator value of DMADONEJOB field. */ #define QSPI_INTENCLR_DMADONEJOB_Max \ - (0x1UL) /*!< Max enumerator value of DMADONEJOB field. */ + (0x1UL) /*!< Max enumerator value of DMADONEJOB field. */ #define QSPI_INTENCLR_DMADONEJOB_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMADONEJOB_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMADONEJOB_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMAERROR @Bit 6 : Write '1' to disable interrupt for event DMAERROR */ -#define QSPI_INTENCLR_DMAERROR_Pos (6UL) /*!< Position of DMAERROR field. */ +#define QSPI_INTENCLR_DMAERROR_Pos (6UL) /*!< Position of DMAERROR field. */ #define QSPI_INTENCLR_DMAERROR_Msk \ - (0x1UL << QSPI_INTENCLR_DMAERROR_Pos) /*!< Bit mask of DMAERROR field. */ -#define QSPI_INTENCLR_DMAERROR_Min (0x0UL) /*!< Min enumerator value of DMAERROR field. */ -#define QSPI_INTENCLR_DMAERROR_Max (0x1UL) /*!< Max enumerator value of DMAERROR field. */ + (0x1UL << QSPI_INTENCLR_DMAERROR_Pos) /*!< Bit mask of DMAERROR field. */ +#define QSPI_INTENCLR_DMAERROR_Min (0x0UL) /*!< Min enumerator value of DMAERROR field. */ +#define QSPI_INTENCLR_DMAERROR_Max (0x1UL) /*!< Max enumerator value of DMAERROR field. */ #define QSPI_INTENCLR_DMAERROR_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMAERROR_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMAERROR_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMAPAUSED @Bit 7 : Write '1' to disable interrupt for event DMAPAUSED */ -#define QSPI_INTENCLR_DMAPAUSED_Pos (7UL) /*!< Position of DMAPAUSED field. */ +#define QSPI_INTENCLR_DMAPAUSED_Pos (7UL) /*!< Position of DMAPAUSED field. */ #define QSPI_INTENCLR_DMAPAUSED_Msk \ - (0x1UL << QSPI_INTENCLR_DMAPAUSED_Pos) /*!< Bit mask of DMAPAUSED field. */ -#define QSPI_INTENCLR_DMAPAUSED_Min (0x0UL) /*!< Min enumerator value of DMAPAUSED field. */ -#define QSPI_INTENCLR_DMAPAUSED_Max (0x1UL) /*!< Max enumerator value of DMAPAUSED field. */ + (0x1UL << QSPI_INTENCLR_DMAPAUSED_Pos) /*!< Bit mask of DMAPAUSED field. */ +#define QSPI_INTENCLR_DMAPAUSED_Min (0x0UL) /*!< Min enumerator value of DMAPAUSED field. */ +#define QSPI_INTENCLR_DMAPAUSED_Max (0x1UL) /*!< Max enumerator value of DMAPAUSED field. */ #define QSPI_INTENCLR_DMAPAUSED_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMAPAUSED_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMAPAUSED_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMARESET @Bit 8 : Write '1' to disable interrupt for event DMARESET */ -#define QSPI_INTENCLR_DMARESET_Pos (8UL) /*!< Position of DMARESET field. */ +#define QSPI_INTENCLR_DMARESET_Pos (8UL) /*!< Position of DMARESET field. */ #define QSPI_INTENCLR_DMARESET_Msk \ - (0x1UL << QSPI_INTENCLR_DMARESET_Pos) /*!< Bit mask of DMARESET field. */ -#define QSPI_INTENCLR_DMARESET_Min (0x0UL) /*!< Min enumerator value of DMARESET field. */ -#define QSPI_INTENCLR_DMARESET_Max (0x1UL) /*!< Max enumerator value of DMARESET field. */ + (0x1UL << QSPI_INTENCLR_DMARESET_Pos) /*!< Bit mask of DMARESET field. */ +#define QSPI_INTENCLR_DMARESET_Min (0x0UL) /*!< Min enumerator value of DMARESET field. */ +#define QSPI_INTENCLR_DMARESET_Max (0x1UL) /*!< Max enumerator value of DMARESET field. */ #define QSPI_INTENCLR_DMARESET_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMARESET_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMARESET_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMADONE @Bit 9 : Write '1' to disable interrupt for event DMADONE */ -#define QSPI_INTENCLR_DMADONE_Pos (9UL) /*!< Position of DMADONE field. */ +#define QSPI_INTENCLR_DMADONE_Pos (9UL) /*!< Position of DMADONE field. */ #define QSPI_INTENCLR_DMADONE_Msk \ - (0x1UL << QSPI_INTENCLR_DMADONE_Pos) /*!< Bit mask of DMADONE field. */ -#define QSPI_INTENCLR_DMADONE_Min (0x0UL) /*!< Min enumerator value of DMADONE field. */ -#define QSPI_INTENCLR_DMADONE_Max (0x1UL) /*!< Max enumerator value of DMADONE field. */ -#define QSPI_INTENCLR_DMADONE_Clear (0x1UL) /*!< Disable */ + (0x1UL << QSPI_INTENCLR_DMADONE_Pos) /*!< Bit mask of DMADONE field. */ +#define QSPI_INTENCLR_DMADONE_Min (0x0UL) /*!< Min enumerator value of DMADONE field. */ +#define QSPI_INTENCLR_DMADONE_Max (0x1UL) /*!< Max enumerator value of DMADONE field. */ +#define QSPI_INTENCLR_DMADONE_Clear (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMADONE_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMADONE_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMATXUNEXPECTEDIDLE @Bit 10 : Write '1' to disable interrupt for event DMATXUNEXPECTEDIDLE */ #define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Pos \ - (10UL) /*!< Position of DMATXUNEXPECTEDIDLE field. */ + (10UL) /*!< Position of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Msk \ - (0x1UL << QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Pos) /*!< Bit mask of - * DMATXUNEXPECTEDIDLE field.*/ + (0x1UL << QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Pos) /*!< Bit mask of + * DMATXUNEXPECTEDIDLE field.*/ #define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Min \ - (0x0UL) /*!< Min enumerator value of DMATXUNEXPECTEDIDLE field. */ + (0x0UL) /*!< Min enumerator value of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Max \ - (0x1UL) /*!< Max enumerator value of DMATXUNEXPECTEDIDLE field. */ + (0x1UL) /*!< Max enumerator value of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMATXUNEXPECTEDIDLE_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMAINTERNALBUSERROR @Bit 11 : Write '1' to disable interrupt for event DMAINTERNALBUSERROR */ #define QSPI_INTENCLR_DMAINTERNALBUSERROR_Pos \ - (11UL) /*!< Position of DMAINTERNALBUSERROR field. */ + (11UL) /*!< Position of DMAINTERNALBUSERROR field. */ #define QSPI_INTENCLR_DMAINTERNALBUSERROR_Msk \ - (0x1UL << QSPI_INTENCLR_DMAINTERNALBUSERROR_Pos) /*!< Bit mask of - * DMAINTERNALBUSERROR field.*/ + (0x1UL << QSPI_INTENCLR_DMAINTERNALBUSERROR_Pos) /*!< Bit mask of + * DMAINTERNALBUSERROR field.*/ #define QSPI_INTENCLR_DMAINTERNALBUSERROR_Min \ - (0x0UL) /*!< Min enumerator value of DMAINTERNALBUSERROR field. */ + (0x0UL) /*!< Min enumerator value of DMAINTERNALBUSERROR field. */ #define QSPI_INTENCLR_DMAINTERNALBUSERROR_Max \ - (0x1UL) /*!< Max enumerator value of DMAINTERNALBUSERROR field. */ + (0x1UL) /*!< Max enumerator value of DMAINTERNALBUSERROR field. */ #define QSPI_INTENCLR_DMAINTERNALBUSERROR_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMAINTERNALBUSERROR_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMAINTERNALBUSERROR_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* DMAABORTED @Bit 12 : Write '1' to disable interrupt for event DMAABORTED */ -#define QSPI_INTENCLR_DMAABORTED_Pos (12UL) /*!< Position of DMAABORTED field. */ +#define QSPI_INTENCLR_DMAABORTED_Pos (12UL) /*!< Position of DMAABORTED field. */ #define QSPI_INTENCLR_DMAABORTED_Msk \ - (0x1UL << QSPI_INTENCLR_DMAABORTED_Pos) /*!< Bit mask of DMAABORTED field. */ + (0x1UL << QSPI_INTENCLR_DMAABORTED_Pos) /*!< Bit mask of DMAABORTED field. */ #define QSPI_INTENCLR_DMAABORTED_Min \ - (0x0UL) /*!< Min enumerator value of DMAABORTED field. */ + (0x0UL) /*!< Min enumerator value of DMAABORTED field. */ #define QSPI_INTENCLR_DMAABORTED_Max \ - (0x1UL) /*!< Max enumerator value of DMAABORTED field. */ + (0x1UL) /*!< Max enumerator value of DMAABORTED field. */ #define QSPI_INTENCLR_DMAABORTED_Clear \ - (0x1UL) /*!< Disable */ + (0x1UL) /*!< Disable */ #define QSPI_INTENCLR_DMAABORTED_Disabled \ - (0x0UL) /*!< Read: Disabled */ + (0x0UL) /*!< Read: Disabled */ #define QSPI_INTENCLR_DMAABORTED_Enabled \ - (0x1UL) /*!< Read: Enabled */ + (0x1UL) /*!< Read: Enabled */ /* IDLE @Bit 13 : Write '1' to disable interrupt for event IDLE */ -#define QSPI_INTENCLR_IDLE_Pos (13UL) /*!< Position of IDLE field. */ +#define QSPI_INTENCLR_IDLE_Pos (13UL) /*!< Position of IDLE field. */ #define QSPI_INTENCLR_IDLE_Msk \ - (0x1UL << QSPI_INTENCLR_IDLE_Pos) /*!< Bit mask of IDLE field. */ -#define QSPI_INTENCLR_IDLE_Min (0x0UL) /*!< Min enumerator value of IDLE field. */ -#define QSPI_INTENCLR_IDLE_Max (0x1UL) /*!< Max enumerator value of IDLE field. */ -#define QSPI_INTENCLR_IDLE_Clear (0x1UL) /*!< Disable */ -#define QSPI_INTENCLR_IDLE_Disabled (0x0UL) /*!< Read: Disabled */ -#define QSPI_INTENCLR_IDLE_Enabled (0x1UL) /*!< Read: Enabled */ + (0x1UL << QSPI_INTENCLR_IDLE_Pos) /*!< Bit mask of IDLE field. */ +#define QSPI_INTENCLR_IDLE_Min (0x0UL) /*!< Min enumerator value of IDLE field. */ +#define QSPI_INTENCLR_IDLE_Max (0x1UL) /*!< Max enumerator value of IDLE field. */ +#define QSPI_INTENCLR_IDLE_Clear (0x1UL) /*!< Disable */ +#define QSPI_INTENCLR_IDLE_Disabled (0x0UL) /*!< Read: Disabled */ +#define QSPI_INTENCLR_IDLE_Enabled (0x1UL) /*!< Read: Enabled */ /* QSPI_INTPEND: Pending interrupts */ #define QSPI_INTPEND_ResetValue \ - (0x00000000UL) /*!< Reset value of INTPEND register. */ + (0x00000000UL) /*!< Reset value of INTPEND register. */ /* CORE @Bit 0 : Read pending status of interrupt for event CORE */ -#define QSPI_INTPEND_CORE_Pos (0UL) /*!< Position of CORE field. */ +#define QSPI_INTPEND_CORE_Pos (0UL) /*!< Position of CORE field. */ #define QSPI_INTPEND_CORE_Msk \ - (0x1UL << QSPI_INTPEND_CORE_Pos) /*!< Bit mask of CORE field. */ -#define QSPI_INTPEND_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ -#define QSPI_INTPEND_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ + (0x1UL << QSPI_INTPEND_CORE_Pos) /*!< Bit mask of CORE field. */ +#define QSPI_INTPEND_CORE_Min (0x0UL) /*!< Min enumerator value of CORE field. */ +#define QSPI_INTPEND_CORE_Max (0x1UL) /*!< Max enumerator value of CORE field. */ #define QSPI_INTPEND_CORE_NotPending \ - (0x0UL) /*!< Read: Not pending */ -#define QSPI_INTPEND_CORE_Pending (0x1UL) /*!< Read: Pending */ + (0x0UL) /*!< Read: Not pending */ +#define QSPI_INTPEND_CORE_Pending (0x1UL) /*!< Read: Pending */ /* DMADONELIST @Bit 1 : Read pending status of interrupt for event DMADONELIST */ -#define QSPI_INTPEND_DMADONELIST_Pos (1UL) /*!< Position of DMADONELIST field. */ +#define QSPI_INTPEND_DMADONELIST_Pos (1UL) /*!< Position of DMADONELIST field. */ #define QSPI_INTPEND_DMADONELIST_Msk \ - (0x1UL << QSPI_INTPEND_DMADONELIST_Pos) /*!< Bit mask of DMADONELIST field. */ + (0x1UL << QSPI_INTPEND_DMADONELIST_Pos) /*!< Bit mask of DMADONELIST field. */ #define QSPI_INTPEND_DMADONELIST_Min \ - (0x0UL) /*!< Min enumerator value of DMADONELIST field. */ + (0x0UL) /*!< Min enumerator value of DMADONELIST field. */ #define QSPI_INTPEND_DMADONELIST_Max \ - (0x1UL) /*!< Max enumerator value of DMADONELIST field. */ + (0x1UL) /*!< Max enumerator value of DMADONELIST field. */ #define QSPI_INTPEND_DMADONELIST_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMADONELIST_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMADONELISTPART @Bit 2 : Read pending status of interrupt for event DMADONELISTPART */ #define QSPI_INTPEND_DMADONELISTPART_Pos \ - (2UL) /*!< Position of DMADONELISTPART field. */ + (2UL) /*!< Position of DMADONELISTPART field. */ #define QSPI_INTPEND_DMADONELISTPART_Msk \ - (0x1UL << QSPI_INTPEND_DMADONELISTPART_Pos) /*!< Bit mask of DMADONELISTPART field. */ + (0x1UL << QSPI_INTPEND_DMADONELISTPART_Pos) /*!< Bit mask of DMADONELISTPART field. */ #define QSPI_INTPEND_DMADONELISTPART_Min \ - (0x0UL) /*!< Min enumerator value of DMADONELISTPART field. */ + (0x0UL) /*!< Min enumerator value of DMADONELISTPART field. */ #define QSPI_INTPEND_DMADONELISTPART_Max \ - (0x1UL) /*!< Max enumerator value of DMADONELISTPART field. */ + (0x1UL) /*!< Max enumerator value of DMADONELISTPART field. */ #define QSPI_INTPEND_DMADONELISTPART_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMADONELISTPART_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMADONESELECTJOB @Bit 3 : Read pending status of interrupt for event DMADONESELECTJOB */ #define QSPI_INTPEND_DMADONESELECTJOB_Pos \ - (3UL) /*!< Position of DMADONESELECTJOB field. */ + (3UL) /*!< Position of DMADONESELECTJOB field. */ #define QSPI_INTPEND_DMADONESELECTJOB_Msk \ - (0x1UL << QSPI_INTPEND_DMADONESELECTJOB_Pos) /*!< Bit mask of DMADONESELECTJOB - * field.*/ + (0x1UL << QSPI_INTPEND_DMADONESELECTJOB_Pos) /*!< Bit mask of DMADONESELECTJOB + * field.*/ #define QSPI_INTPEND_DMADONESELECTJOB_Min \ - (0x0UL) /*!< Min enumerator value of DMADONESELECTJOB field. */ + (0x0UL) /*!< Min enumerator value of DMADONESELECTJOB field. */ #define QSPI_INTPEND_DMADONESELECTJOB_Max \ - (0x1UL) /*!< Max enumerator value of DMADONESELECTJOB field. */ + (0x1UL) /*!< Max enumerator value of DMADONESELECTJOB field. */ #define QSPI_INTPEND_DMADONESELECTJOB_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMADONESELECTJOB_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMADONEDATA @Bit 4 : Read pending status of interrupt for event DMADONEDATA */ -#define QSPI_INTPEND_DMADONEDATA_Pos (4UL) /*!< Position of DMADONEDATA field. */ +#define QSPI_INTPEND_DMADONEDATA_Pos (4UL) /*!< Position of DMADONEDATA field. */ #define QSPI_INTPEND_DMADONEDATA_Msk \ - (0x1UL << QSPI_INTPEND_DMADONEDATA_Pos) /*!< Bit mask of DMADONEDATA field. */ + (0x1UL << QSPI_INTPEND_DMADONEDATA_Pos) /*!< Bit mask of DMADONEDATA field. */ #define QSPI_INTPEND_DMADONEDATA_Min \ - (0x0UL) /*!< Min enumerator value of DMADONEDATA field. */ + (0x0UL) /*!< Min enumerator value of DMADONEDATA field. */ #define QSPI_INTPEND_DMADONEDATA_Max \ - (0x1UL) /*!< Max enumerator value of DMADONEDATA field. */ + (0x1UL) /*!< Max enumerator value of DMADONEDATA field. */ #define QSPI_INTPEND_DMADONEDATA_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMADONEDATA_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMADONEJOB @Bit 5 : Read pending status of interrupt for event DMADONEJOB */ -#define QSPI_INTPEND_DMADONEJOB_Pos (5UL) /*!< Position of DMADONEJOB field. */ +#define QSPI_INTPEND_DMADONEJOB_Pos (5UL) /*!< Position of DMADONEJOB field. */ #define QSPI_INTPEND_DMADONEJOB_Msk \ - (0x1UL << QSPI_INTPEND_DMADONEJOB_Pos) /*!< Bit mask of DMADONEJOB field. */ -#define QSPI_INTPEND_DMADONEJOB_Min (0x0UL) /*!< Min enumerator value of DMADONEJOB field. */ -#define QSPI_INTPEND_DMADONEJOB_Max (0x1UL) /*!< Max enumerator value of DMADONEJOB field. */ + (0x1UL << QSPI_INTPEND_DMADONEJOB_Pos) /*!< Bit mask of DMADONEJOB field. */ +#define QSPI_INTPEND_DMADONEJOB_Min (0x0UL) /*!< Min enumerator value of DMADONEJOB field. */ +#define QSPI_INTPEND_DMADONEJOB_Max (0x1UL) /*!< Max enumerator value of DMADONEJOB field. */ #define QSPI_INTPEND_DMADONEJOB_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMADONEJOB_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMAERROR @Bit 6 : Read pending status of interrupt for event DMAERROR */ -#define QSPI_INTPEND_DMAERROR_Pos (6UL) /*!< Position of DMAERROR field. */ +#define QSPI_INTPEND_DMAERROR_Pos (6UL) /*!< Position of DMAERROR field. */ #define QSPI_INTPEND_DMAERROR_Msk \ - (0x1UL << QSPI_INTPEND_DMAERROR_Pos) /*!< Bit mask of DMAERROR field. */ -#define QSPI_INTPEND_DMAERROR_Min (0x0UL) /*!< Min enumerator value of DMAERROR field. */ -#define QSPI_INTPEND_DMAERROR_Max (0x1UL) /*!< Max enumerator value of DMAERROR field. */ + (0x1UL << QSPI_INTPEND_DMAERROR_Pos) /*!< Bit mask of DMAERROR field. */ +#define QSPI_INTPEND_DMAERROR_Min (0x0UL) /*!< Min enumerator value of DMAERROR field. */ +#define QSPI_INTPEND_DMAERROR_Max (0x1UL) /*!< Max enumerator value of DMAERROR field. */ #define QSPI_INTPEND_DMAERROR_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMAERROR_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMAPAUSED @Bit 7 : Read pending status of interrupt for event DMAPAUSED */ -#define QSPI_INTPEND_DMAPAUSED_Pos (7UL) /*!< Position of DMAPAUSED field. */ +#define QSPI_INTPEND_DMAPAUSED_Pos (7UL) /*!< Position of DMAPAUSED field. */ #define QSPI_INTPEND_DMAPAUSED_Msk \ - (0x1UL << QSPI_INTPEND_DMAPAUSED_Pos) /*!< Bit mask of DMAPAUSED field. */ -#define QSPI_INTPEND_DMAPAUSED_Min (0x0UL) /*!< Min enumerator value of DMAPAUSED field. */ -#define QSPI_INTPEND_DMAPAUSED_Max (0x1UL) /*!< Max enumerator value of DMAPAUSED field. */ + (0x1UL << QSPI_INTPEND_DMAPAUSED_Pos) /*!< Bit mask of DMAPAUSED field. */ +#define QSPI_INTPEND_DMAPAUSED_Min (0x0UL) /*!< Min enumerator value of DMAPAUSED field. */ +#define QSPI_INTPEND_DMAPAUSED_Max (0x1UL) /*!< Max enumerator value of DMAPAUSED field. */ #define QSPI_INTPEND_DMAPAUSED_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMAPAUSED_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMARESET @Bit 8 : Read pending status of interrupt for event DMARESET */ -#define QSPI_INTPEND_DMARESET_Pos (8UL) /*!< Position of DMARESET field. */ +#define QSPI_INTPEND_DMARESET_Pos (8UL) /*!< Position of DMARESET field. */ #define QSPI_INTPEND_DMARESET_Msk \ - (0x1UL << QSPI_INTPEND_DMARESET_Pos) /*!< Bit mask of DMARESET field. */ -#define QSPI_INTPEND_DMARESET_Min (0x0UL) /*!< Min enumerator value of DMARESET field. */ -#define QSPI_INTPEND_DMARESET_Max (0x1UL) /*!< Max enumerator value of DMARESET field. */ + (0x1UL << QSPI_INTPEND_DMARESET_Pos) /*!< Bit mask of DMARESET field. */ +#define QSPI_INTPEND_DMARESET_Min (0x0UL) /*!< Min enumerator value of DMARESET field. */ +#define QSPI_INTPEND_DMARESET_Max (0x1UL) /*!< Max enumerator value of DMARESET field. */ #define QSPI_INTPEND_DMARESET_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMARESET_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMADONE @Bit 9 : Read pending status of interrupt for event DMADONE */ -#define QSPI_INTPEND_DMADONE_Pos (9UL) /*!< Position of DMADONE field. */ +#define QSPI_INTPEND_DMADONE_Pos (9UL) /*!< Position of DMADONE field. */ #define QSPI_INTPEND_DMADONE_Msk \ - (0x1UL << QSPI_INTPEND_DMADONE_Pos) /*!< Bit mask of DMADONE field. */ -#define QSPI_INTPEND_DMADONE_Min (0x0UL) /*!< Min enumerator value of DMADONE field. */ -#define QSPI_INTPEND_DMADONE_Max (0x1UL) /*!< Max enumerator value of DMADONE field. */ + (0x1UL << QSPI_INTPEND_DMADONE_Pos) /*!< Bit mask of DMADONE field. */ +#define QSPI_INTPEND_DMADONE_Min (0x0UL) /*!< Min enumerator value of DMADONE field. */ +#define QSPI_INTPEND_DMADONE_Max (0x1UL) /*!< Max enumerator value of DMADONE field. */ #define QSPI_INTPEND_DMADONE_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMADONE_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMATXUNEXPECTEDIDLE @Bit 10 : Read pending status of interrupt for event DMATXUNEXPECTEDIDLE */ #define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Pos \ - (10UL) /*!< Position of DMATXUNEXPECTEDIDLE field. */ + (10UL) /*!< Position of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Msk \ - (0x1UL << QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Pos) /*!< Bit mask of - * DMATXUNEXPECTEDIDLE field.*/ + (0x1UL << QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Pos) /*!< Bit mask of + * DMATXUNEXPECTEDIDLE field.*/ #define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Min \ - (0x0UL) /*!< Min enumerator value of DMATXUNEXPECTEDIDLE field. */ + (0x0UL) /*!< Min enumerator value of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Max \ - (0x1UL) /*!< Max enumerator value of DMATXUNEXPECTEDIDLE field. */ + (0x1UL) /*!< Max enumerator value of DMATXUNEXPECTEDIDLE field. */ #define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMATXUNEXPECTEDIDLE_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMAINTERNALBUSERROR @Bit 11 : Read pending status of interrupt for event DMAINTERNALBUSERROR */ #define QSPI_INTPEND_DMAINTERNALBUSERROR_Pos \ - (11UL) /*!< Position of DMAINTERNALBUSERROR field. */ + (11UL) /*!< Position of DMAINTERNALBUSERROR field. */ #define QSPI_INTPEND_DMAINTERNALBUSERROR_Msk \ - (0x1UL << QSPI_INTPEND_DMAINTERNALBUSERROR_Pos) /*!< Bit mask of - * DMAINTERNALBUSERROR field.*/ + (0x1UL << QSPI_INTPEND_DMAINTERNALBUSERROR_Pos) /*!< Bit mask of + * DMAINTERNALBUSERROR field.*/ #define QSPI_INTPEND_DMAINTERNALBUSERROR_Min \ - (0x0UL) /*!< Min enumerator value of DMAINTERNALBUSERROR field. */ + (0x0UL) /*!< Min enumerator value of DMAINTERNALBUSERROR field. */ #define QSPI_INTPEND_DMAINTERNALBUSERROR_Max \ - (0x1UL) /*!< Max enumerator value of DMAINTERNALBUSERROR field. */ + (0x1UL) /*!< Max enumerator value of DMAINTERNALBUSERROR field. */ #define QSPI_INTPEND_DMAINTERNALBUSERROR_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMAINTERNALBUSERROR_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* DMAABORTED @Bit 12 : Read pending status of interrupt for event DMAABORTED */ -#define QSPI_INTPEND_DMAABORTED_Pos (12UL) /*!< Position of DMAABORTED field. */ +#define QSPI_INTPEND_DMAABORTED_Pos (12UL) /*!< Position of DMAABORTED field. */ #define QSPI_INTPEND_DMAABORTED_Msk \ - (0x1UL << QSPI_INTPEND_DMAABORTED_Pos) /*!< Bit mask of DMAABORTED field. */ -#define QSPI_INTPEND_DMAABORTED_Min (0x0UL) /*!< Min enumerator value of DMAABORTED field. */ -#define QSPI_INTPEND_DMAABORTED_Max (0x1UL) /*!< Max enumerator value of DMAABORTED field. */ + (0x1UL << QSPI_INTPEND_DMAABORTED_Pos) /*!< Bit mask of DMAABORTED field. */ +#define QSPI_INTPEND_DMAABORTED_Min (0x0UL) /*!< Min enumerator value of DMAABORTED field. */ +#define QSPI_INTPEND_DMAABORTED_Max (0x1UL) /*!< Max enumerator value of DMAABORTED field. */ #define QSPI_INTPEND_DMAABORTED_NotPending \ - (0x0UL) /*!< Read: Not pending */ + (0x0UL) /*!< Read: Not pending */ #define QSPI_INTPEND_DMAABORTED_Pending \ - (0x1UL) /*!< Read: Pending */ + (0x1UL) /*!< Read: Pending */ /* IDLE @Bit 13 : Read pending status of interrupt for event IDLE */ -#define QSPI_INTPEND_IDLE_Pos (13UL) /*!< Position of IDLE field. */ +#define QSPI_INTPEND_IDLE_Pos (13UL) /*!< Position of IDLE field. */ #define QSPI_INTPEND_IDLE_Msk \ - (0x1UL << QSPI_INTPEND_IDLE_Pos) /*!< Bit mask of IDLE field. */ -#define QSPI_INTPEND_IDLE_Min (0x0UL) /*!< Min enumerator value of IDLE field. */ -#define QSPI_INTPEND_IDLE_Max (0x1UL) /*!< Max enumerator value of IDLE field. */ + (0x1UL << QSPI_INTPEND_IDLE_Pos) /*!< Bit mask of IDLE field. */ +#define QSPI_INTPEND_IDLE_Min (0x0UL) /*!< Min enumerator value of IDLE field. */ +#define QSPI_INTPEND_IDLE_Max (0x1UL) /*!< Max enumerator value of IDLE field. */ #define QSPI_INTPEND_IDLE_NotPending \ - (0x0UL) /*!< Read: Not pending */ -#define QSPI_INTPEND_IDLE_Pending (0x1UL) /*!< Read: Pending */ + (0x0UL) /*!< Read: Not pending */ +#define QSPI_INTPEND_IDLE_Pending (0x1UL) /*!< Read: Pending */ /* QSPI_ENABLE: Enables the QSPI This requests clock for the IP core */ #define QSPI_ENABLE_ResetValue \ - (0x00000000UL) /*!< Reset value of ENABLE register. */ + (0x00000000UL) /*!< Reset value of ENABLE register. */ /* ENABLE @Bit 0 : Enable the QSPI */ -#define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ +#define QSPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ #define QSPI_ENABLE_ENABLE_Msk \ - (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ + (0x1UL << QSPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ #endif /*!< !defined(__ASSEMBLER__) && !defined(__ASSEMBLY__) */ diff --git a/softperipheral/sQSPI/include/nrf_sqspi.h b/softperipheral/sQSPI/include/nrf_sqspi.h index b4f0873dc4..1461f714d9 100644 --- a/softperipheral/sQSPI/include/nrf_sqspi.h +++ b/softperipheral/sQSPI/include/nrf_sqspi.h @@ -618,10 +618,8 @@ nrfx_err_t nrf_sqspi_dev_cfg(nrf_sqspi_t const * p_qspi, * @param[in] p_data_fmt Data format to set. * * @retval NRFX_SUCCESS Data format configured successfully - * @retval NRFX_ERROR_BUSY The device is during a transfer. Can't - * reconfigure - * @retval NRFX_ERROR_NOT_SUPPORTED The data format is not supported by this - * driver + * @retval NRFX_ERROR_INVALID_PARAM At least one configuration option has + * invalid value */ nrfx_err_t nrf_sqspi_dev_data_fmt_set(nrf_sqspi_t const * p_qspi, nrf_sqspi_data_fmt_t * p_data_fmt); @@ -649,7 +647,7 @@ nrfx_err_t nrf_sqspi_activate(nrf_sqspi_t const * p_qspi); * deactivated. * * @note If a transfer is ongoing when the function is called, the transfer is - * aborted. + * aborted. Any prepared transfer is discarded on deactivation. * * @param[in] p_qspi Identifier of the QSPI instance to deactivate. * diff --git a/softperipheral/sQSPI/src/nrf_sqspi.c b/softperipheral/sQSPI/src/nrf_sqspi.c index d8d635a0aa..6c26914724 100644 --- a/softperipheral/sQSPI/src/nrf_sqspi.c +++ b/softperipheral/sQSPI/src/nrf_sqspi.c @@ -113,6 +113,16 @@ static qspi2_control_block_t m_cb[NRF_SQSPI_ENABLED_COUNT] = {{.state = NRFX_DRV_STATE_UNINITIALIZED}}; static volatile nrf_sqspi_transaction_data_t m_current_xfer; +NRF_STATIC_INLINE void sp_handshake_set(void * p_reg, uint32_t val, uint8_t idx) +{ + nrf_qspi2_handshake_set((NRF_QSPI2_Type *)p_reg, val, idx); +} + +NRF_STATIC_INLINE uint32_t sp_handshake_get(void * p_reg, uint8_t idx) +{ + return nrf_qspi2_handshake_get((NRF_QSPI2_Type const *)p_reg, idx); +} + nrfx_err_t nrf_sqspi_init(const nrf_sqspi_t * p_qspi, const nrf_sqspi_cfg_t * p_config) { NRFX_ASSERT(p_qspi); @@ -403,6 +413,21 @@ nrfx_err_t nrf_sqspi_dev_cfg(const nrf_sqspi_t * p_qspi, p_cb->conf.ctrlr0.scph = QSPI_CORE_CORE_CTRLR0_SCPH_MIDDLEBIT; p_cb->conf.ctrlr0.scpol = QSPI_CORE_CORE_CTRLR0_SCPOL_INACTIVEHIGH; } + else if (p_config->spi_cpolpha == NRF_SQSPI_SPI_CPOLPHA_1) + { + p_cb->conf.ctrlr0.scph = QSPI_CORE_CORE_CTRLR0_SCPH_STARTBIT; + p_cb->conf.ctrlr0.scpol = QSPI_CORE_CORE_CTRLR0_SCPOL_INACTIVEHIGH; + } + else if (p_config->spi_cpolpha == NRF_SQSPI_SPI_CPOLPHA_2) + { + p_cb->conf.ctrlr0.scph = QSPI_CORE_CORE_CTRLR0_SCPH_MIDDLEBIT; + p_cb->conf.ctrlr0.scpol = QSPI_CORE_CORE_CTRLR0_SCPOL_INACTIVELOW; + } + else if (p_config->spi_cpolpha == NRF_SQSPI_SPI_CPOLPHA_3) + { + p_cb->conf.ctrlr0.scph = QSPI_CORE_CORE_CTRLR0_SCPH_STARTBIT; + p_cb->conf.ctrlr0.scpol = QSPI_CORE_CORE_CTRLR0_SCPOL_INACTIVELOW; + } if (p_config->mspi_lines == NRF_SQSPI_SPI_LINES_SINGLE) {