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lines changed Original file line number Diff line number Diff line change @@ -25,7 +25,7 @@ config DFU_MULTI_IMAGE_PACKAGE_APP
2525 default y
2626
2727config PM_EXTERNAL_FLASH_MCUBOOT_SECONDARY
28- default y if BOARD_NRF52840DK_NRF52840 || BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP
28+ default y if !BOARD_NRF54L15DK_NRF54L15_CPUAPP || !BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS
2929
3030if (BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP)
3131
@@ -50,7 +50,7 @@ config DFU_MULTI_IMAGE_PACKAGE_NET
5050
5151endif # (BOARD_NRF5340DK_NRF5340_CPUAPP || BOARD_THINGY53_NRF5340_CPUAPP)
5252
53- if (BOARD_NRF54L15DK_NRF54L15_CPUAPP || BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS)
53+ if (BOARD_NRF54L15DK_NRF54L15_CPUAPP || BOARD_NRF54L15DK_NRF54L15_CPUAPP_NS || BOARD_NRF54L15DK_NRF54L10_CPUAPP )
5454
5555# TODO: NCSDK-28931: Cannot use fprotect twice, so disable it in MCUboot to
5656# test protecting factory data. It can be enabled while there is a support
Original file line number Diff line number Diff line change 55#
66
77CONFIG_POWEROFF=y
8+
9+ # nRF54L15DK uses SPI NOR external flash for DFU
10+ CONFIG_SPI=y
11+ CONFIG_SPI_NOR=y
12+ CONFIG_MULTITHREADING=y
13+ CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y
14+ CONFIG_MCUMGR_GRP_IMG_ALLOW_ERASE_PENDING=y
Original file line number Diff line number Diff line change 3131 label = "semtech_sx1262 DIO1";
3232 };
3333 };
34+
35+ chosen {
36+ nordic,pm-ext-flash = &mx25r64;
37+ };
3438};
3539
3640sid_semtech: &spi30 {
@@ -89,6 +93,9 @@ sid_semtech: &spi30 {
8993&spi22 {
9094 status = "disabled";
9195};
96+ &mx25r64 {
97+ status = "okay";
98+ };
9299
93100// TODO: re-enable HWFC once it's fixed
94101&uart20 {
Original file line number Diff line number Diff line change 11app :
22 address : 0xc800
3- end_address : 0x84800
3+ end_address : 0xfd000
44 region : flash_primary
5- size : 0x78000
5+ size : 0xf0800
66mcuboot :
77 address : 0x0
88 end_address : 0xc000
@@ -21,46 +21,43 @@ mcuboot_pad:
2121 size : 0x800
2222mcuboot_primary :
2323 address : 0xc000
24- end_address : 0x84800
24+ end_address : 0xfd000
2525 orig_span : &id001
2626 - mcuboot_pad
2727 - app
2828 region : flash_primary
29- sharers : 0x1
30- size : 0x78800
29+ size : 0xf1000
3130 span : *id001
3231mcuboot_primary_app :
3332 address : 0xc800
34- end_address : 0x84800
33+ end_address : 0xfd000
3534 orig_span : &id002
3635 - app
3736 region : flash_primary
38- size : 0x78000
37+ size : 0xf0800
3938 span : *id002
40- mcuboot_secondary :
41- address : 0x84800
42- end_address : 0xfd000
39+ settings_storage :
40+ address : 0xfd000
41+ end_address : 0xff000
4342 placement :
44- after :
45- - mcuboot_primary
4643 align :
4744 start : 0x1000
45+ before :
46+ - end
4847 region : flash_primary
49- share_size :
50- - mcuboot_primary
51- size : 0x78800
48+ size : 0x2000
5249mfg_storage :
5350 address : 0xff000
5451 end_address : 0x100000
5552 region : flash_primary
5653 size : 0x1000
57- settings_storage :
58- address : 0xfd000
59- end_address : 0xff000
54+ mcuboot_secondary :
55+ address : 0x0
56+ end_address : 0xf1000
6057 placement :
6158 align :
62- start : 0x1000
63- before :
64- - end
65- region : flash_primary
66- size : 0x2000
59+ start : 0x4
60+ region : external_flash
61+ share_size :
62+ - mcuboot_primary
63+ size : 0xf1000
Original file line number Diff line number Diff line change @@ -23,7 +23,12 @@ CONFIG_BOOT_WATCHDOG_FEED=n
2323
2424CONFIG_PM_OVERRIDE_EXTERNAL_DRIVER_CHECK=y
2525
26- # Ensure that the qspi driver is disabled by default
27- CONFIG_SPI=n
28- CONFIG_SPI_NOR=n
29- CONFIG_NORDIC_QSPI_NOR=n
26+ # nRF54L15DK uses SPI NOR external flash
27+ CONFIG_GPIO=y
28+ CONFIG_SPI=y
29+ CONFIG_SPI_NOR=y
30+ CONFIG_SPI_NOR_SFDP_DEVICETREE=y
31+ CONFIG_SPI_NOR_FLASH_LAYOUT_PAGE_SIZE=4096
32+
33+ # required by SPI driver
34+ CONFIG_MULTITHREADING=y
Original file line number Diff line number Diff line change 44 * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
55 */
66
7+ / {
8+ chosen {
9+ nordic,pm-ext-flash = &mx25r64;
10+ };
11+ };
712
813/* Application does not use cpuflpr core. Assign whole RRAM and RAM to cpuapp. */
914&cpuapp_rram {
1520 ranges = <0x0 0x20000000 DT_SIZE_K(192)>;
1621};
1722
18- &adc {
19- status = "disabled";
20- };
21- &uart21 {
22- status = "disabled";
23- };
24- &pwm20 {
25- status = "disabled";
26- };
27- &i2c20 {
28- status = "disabled";
29- };
30- &spi00 {
31- status = "disabled";
32- };
33- &spi20 {
34- status = "disabled";
35- };
36- &spi21 {
37- status = "disabled";
38- };
39- &spi22 {
40- status = "disabled";
41- };
42-
43- /* Disable the external flash, as it's not needed
44- for the configuration with secondary slot residing
45- in the internal MRAM. */
4623&mx25r64 {
47- status = "disabled ";
24+ status = "okay ";
4825};
Original file line number Diff line number Diff line change @@ -25,7 +25,7 @@ config SIDEWALK_DFU_BOOTLOADER
2525 imply EXTRA_EXCEPTION_INFO
2626
2727config SIDEWALK_DFU_SERVICE_BLE
28- bool "DFU sericve over BLE"
28+ bool "DFU service over BLE"
2929 default SIDEWALK_DFU
3030 imply MCUMGR
3131 imply MCUMGR_GRP_IMG
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