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ananglcarlescufi
anangl
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carlescufi
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[nrf fromtree] drivers: pinctrl_nrf: Use S0D1 drive by default for TWI/TWIM pins
The default S0S1 drive setting is not suitable for TWI/TWIM pins. Override it with S0D1 as for some SoCs (e.g. nRF52833) without this the peripheral will not work properly. Signed-off-by: Andrzej Głąbek <[email protected]> (cherry picked from commit fd07675)
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-37
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2 files changed

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-37
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‎drivers/pinctrl/pinctrl_nrf.c‎

Lines changed: 51 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -86,7 +86,8 @@ BUILD_ASSERT(((NRF_DRIVE_S0S1 == NRF_GPIO_PIN_S0S1) &&
8686
*/
8787
__unused static void nrf_pin_configure(pinctrl_soc_pin_t pin,
8888
nrf_gpio_pin_dir_t dir,
89-
nrf_gpio_pin_input_t input)
89+
nrf_gpio_pin_input_t input,
90+
nrf_gpio_pin_drive_t drive)
9091
{
9192
/* force input direction and disconnected buffer for low power */
9293
if (NRF_GET_LP(pin) == NRF_LP_ENABLE) {
@@ -102,136 +103,150 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
102103
uintptr_t reg)
103104
{
104105
for (uint8_t i = 0U; i < pin_cnt; i++) {
106+
__unused nrf_gpio_pin_drive_t drive = NRF_GET_DRIVE(pins[i]);
107+
105108
switch (NRF_GET_FUN(pins[i])) {
106109
#if defined(NRF_PSEL_UART)
107110
case NRF_FUN_UART_TX:
108111
NRF_PSEL_UART(reg, TXD) = NRF_GET_PIN(pins[i]);
109112
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 1);
110113
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
111-
NRF_GPIO_PIN_INPUT_DISCONNECT);
114+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
112115
break;
113116
case NRF_FUN_UART_RX:
114117
NRF_PSEL_UART(reg, RXD) = NRF_GET_PIN(pins[i]);
115118
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
116-
NRF_GPIO_PIN_INPUT_CONNECT);
119+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
117120
break;
118121
case NRF_FUN_UART_RTS:
119122
NRF_PSEL_UART(reg, RTS) = NRF_GET_PIN(pins[i]);
120123
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 1);
121124
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
122-
NRF_GPIO_PIN_INPUT_DISCONNECT);
125+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
123126
break;
124127
case NRF_FUN_UART_CTS:
125128
NRF_PSEL_UART(reg, CTS) = NRF_GET_PIN(pins[i]);
126129
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
127-
NRF_GPIO_PIN_INPUT_CONNECT);
130+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
128131
break;
129132
#endif /* defined(NRF_PSEL_UART) */
130133
#if defined(NRF_PSEL_SPIM)
131134
case NRF_FUN_SPIM_SCK:
132135
NRF_PSEL_SPIM(reg, SCK) = NRF_GET_PIN(pins[i]);
133136
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 0);
134137
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
135-
NRF_GPIO_PIN_INPUT_CONNECT);
138+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
136139
break;
137140
case NRF_FUN_SPIM_MOSI:
138141
NRF_PSEL_SPIM(reg, MOSI) = NRF_GET_PIN(pins[i]);
139142
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 0);
140143
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
141-
NRF_GPIO_PIN_INPUT_DISCONNECT);
144+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
142145
break;
143146
case NRF_FUN_SPIM_MISO:
144147
NRF_PSEL_SPIM(reg, MISO) = NRF_GET_PIN(pins[i]);
145148
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
146-
NRF_GPIO_PIN_INPUT_CONNECT);
149+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
147150
break;
148151
#endif /* defined(NRF_PSEL_SPIM) */
149152
#if defined(NRF_PSEL_SPIS)
150153
case NRF_FUN_SPIS_SCK:
151154
NRF_PSEL_SPIS(reg, SCK) = NRF_GET_PIN(pins[i]);
152155
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
153-
NRF_GPIO_PIN_INPUT_CONNECT);
156+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
154157
break;
155158
case NRF_FUN_SPIS_MOSI:
156159
NRF_PSEL_SPIS(reg, MOSI) = NRF_GET_PIN(pins[i]);
157160
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
158-
NRF_GPIO_PIN_INPUT_CONNECT);
161+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
159162
break;
160163
case NRF_FUN_SPIS_MISO:
161164
NRF_PSEL_SPIS(reg, MISO) = NRF_GET_PIN(pins[i]);
162165
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
163-
NRF_GPIO_PIN_INPUT_DISCONNECT);
166+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
164167
break;
165168
case NRF_FUN_SPIS_CSN:
166169
NRF_PSEL_SPIS(reg, CSN) = NRF_GET_PIN(pins[i]);
167170
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
168-
NRF_GPIO_PIN_INPUT_CONNECT);
171+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
169172
break;
170173
#endif /* defined(NRF_PSEL_SPIS) */
171174
#if defined(NRF_PSEL_TWIM)
172175
case NRF_FUN_TWIM_SCL:
173176
NRF_PSEL_TWIM(reg, SCL) = NRF_GET_PIN(pins[i]);
177+
if (drive == NRF_DRIVE_S0S1) {
178+
/* Override the default drive setting with one
179+
* suitable for TWI/TWIM peripherals (S0D1).
180+
* This drive cannot be used always so that
181+
* users are able to select e.g. H0D1 or E0E1
182+
* in devicetree.
183+
*/
184+
drive = NRF_DRIVE_S0D1;
185+
}
174186
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
175-
NRF_GPIO_PIN_INPUT_CONNECT);
187+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
176188
break;
177189
case NRF_FUN_TWIM_SDA:
178190
NRF_PSEL_TWIM(reg, SDA) = NRF_GET_PIN(pins[i]);
191+
if (drive == NRF_DRIVE_S0S1) {
192+
drive = NRF_DRIVE_S0D1;
193+
}
179194
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
180-
NRF_GPIO_PIN_INPUT_CONNECT);
195+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
181196
break;
182197
#endif /* defined(NRF_PSEL_TWIM) */
183198
#if defined(NRF_PSEL_I2S)
184199
case NRF_FUN_I2S_SCK_M:
185200
NRF_PSEL_I2S(reg, SCK) = NRF_GET_PIN(pins[i]);
186201
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 0);
187202
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
188-
NRF_GPIO_PIN_INPUT_DISCONNECT);
203+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
189204
break;
190205
case NRF_FUN_I2S_SCK_S:
191206
NRF_PSEL_I2S(reg, SCK) = NRF_GET_PIN(pins[i]);
192207
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
193-
NRF_GPIO_PIN_INPUT_CONNECT);
208+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
194209
break;
195210
case NRF_FUN_I2S_LRCK_M:
196211
NRF_PSEL_I2S(reg, LRCK) = NRF_GET_PIN(pins[i]);
197212
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 0);
198213
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
199-
NRF_GPIO_PIN_INPUT_DISCONNECT);
214+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
200215
break;
201216
case NRF_FUN_I2S_LRCK_S:
202217
NRF_PSEL_I2S(reg, LRCK) = NRF_GET_PIN(pins[i]);
203218
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
204-
NRF_GPIO_PIN_INPUT_CONNECT);
219+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
205220
break;
206221
case NRF_FUN_I2S_SDIN:
207222
NRF_PSEL_I2S(reg, SDIN) = NRF_GET_PIN(pins[i]);
208223
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
209-
NRF_GPIO_PIN_INPUT_CONNECT);
224+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
210225
break;
211226
case NRF_FUN_I2S_SDOUT:
212227
NRF_PSEL_I2S(reg, SDOUT) = NRF_GET_PIN(pins[i]);
213228
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 0);
214229
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
215-
NRF_GPIO_PIN_INPUT_DISCONNECT);
230+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
216231
break;
217232
case NRF_FUN_I2S_MCK:
218233
NRF_PSEL_I2S(reg, MCK) = NRF_GET_PIN(pins[i]);
219234
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 0);
220235
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
221-
NRF_GPIO_PIN_INPUT_DISCONNECT);
236+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
222237
break;
223238
#endif /* defined(NRF_PSEL_I2S) */
224239
#if defined(NRF_PSEL_PDM)
225240
case NRF_FUN_PDM_CLK:
226241
NRF_PSEL_PDM(reg, CLK) = NRF_GET_PIN(pins[i]);
227242
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]), 0);
228243
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
229-
NRF_GPIO_PIN_INPUT_DISCONNECT);
244+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
230245
break;
231246
case NRF_FUN_PDM_DIN:
232247
NRF_PSEL_PDM(reg, DIN) = NRF_GET_PIN(pins[i]);
233248
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
234-
NRF_GPIO_PIN_INPUT_CONNECT);
249+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
235250
break;
236251
#endif /* defined(NRF_PSEL_PDM) */
237252
#if defined(NRF_PSEL_PWM)
@@ -240,77 +255,77 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
240255
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
241256
NRF_GET_INVERT(pins[i]));
242257
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
243-
NRF_GPIO_PIN_INPUT_DISCONNECT);
258+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
244259
break;
245260
case NRF_FUN_PWM_OUT1:
246261
NRF_PSEL_PWM(reg, OUT[1]) = NRF_GET_PIN(pins[i]);
247262
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
248263
NRF_GET_INVERT(pins[i]));
249264
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
250-
NRF_GPIO_PIN_INPUT_DISCONNECT);
265+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
251266
break;
252267
case NRF_FUN_PWM_OUT2:
253268
NRF_PSEL_PWM(reg, OUT[2]) = NRF_GET_PIN(pins[i]);
254269
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
255270
NRF_GET_INVERT(pins[i]));
256271
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
257-
NRF_GPIO_PIN_INPUT_DISCONNECT);
272+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
258273
break;
259274
case NRF_FUN_PWM_OUT3:
260275
NRF_PSEL_PWM(reg, OUT[3]) = NRF_GET_PIN(pins[i]);
261276
nrf_gpio_pin_write(NRF_GET_PIN(pins[i]),
262277
NRF_GET_INVERT(pins[i]));
263278
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_OUTPUT,
264-
NRF_GPIO_PIN_INPUT_DISCONNECT);
279+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
265280
break;
266281
#endif /* defined(NRF_PSEL_PWM) */
267282
#if defined(NRF_PSEL_QDEC)
268283
case NRF_FUN_QDEC_A:
269284
NRF_PSEL_QDEC(reg, A) = NRF_GET_PIN(pins[i]);
270285
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
271-
NRF_GPIO_PIN_INPUT_CONNECT);
286+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
272287
break;
273288
case NRF_FUN_QDEC_B:
274289
NRF_PSEL_QDEC(reg, B) = NRF_GET_PIN(pins[i]);
275290
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
276-
NRF_GPIO_PIN_INPUT_CONNECT);
291+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
277292
break;
278293
case NRF_FUN_QDEC_LED:
279294
NRF_PSEL_QDEC(reg, LED) = NRF_GET_PIN(pins[i]);
280295
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
281-
NRF_GPIO_PIN_INPUT_CONNECT);
296+
NRF_GPIO_PIN_INPUT_CONNECT, drive);
282297
break;
283298
#endif /* defined(NRF_PSEL_QDEC) */
284299
#if defined(NRF_PSEL_QSPI)
285300
case NRF_FUN_QSPI_SCK:
286301
NRF_PSEL_QSPI(reg, SCK) = NRF_GET_PIN(pins[i]);
287302
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
288-
NRF_GPIO_PIN_INPUT_DISCONNECT);
303+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
289304
break;
290305
case NRF_FUN_QSPI_CSN:
291306
NRF_PSEL_QSPI(reg, CSN) = NRF_GET_PIN(pins[i]);
292307
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
293-
NRF_GPIO_PIN_INPUT_DISCONNECT);
308+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
294309
break;
295310
case NRF_FUN_QSPI_IO0:
296311
NRF_PSEL_QSPI(reg, IO0) = NRF_GET_PIN(pins[i]);
297312
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
298-
NRF_GPIO_PIN_INPUT_DISCONNECT);
313+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
299314
break;
300315
case NRF_FUN_QSPI_IO1:
301316
NRF_PSEL_QSPI(reg, IO1) = NRF_GET_PIN(pins[i]);
302317
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
303-
NRF_GPIO_PIN_INPUT_DISCONNECT);
318+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
304319
break;
305320
case NRF_FUN_QSPI_IO2:
306321
NRF_PSEL_QSPI(reg, IO2) = NRF_GET_PIN(pins[i]);
307322
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
308-
NRF_GPIO_PIN_INPUT_DISCONNECT);
323+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
309324
break;
310325
case NRF_FUN_QSPI_IO3:
311326
NRF_PSEL_QSPI(reg, IO3) = NRF_GET_PIN(pins[i]);
312327
nrf_pin_configure(pins[i], NRF_GPIO_PIN_DIR_INPUT,
313-
NRF_GPIO_PIN_INPUT_DISCONNECT);
328+
NRF_GPIO_PIN_INPUT_DISCONNECT, drive);
314329
break;
315330
#endif /* defined(NRF_PSEL_QSPI) */
316331
default:

‎dts/bindings/pinctrl/nordic,nrf-pinctrl.yaml‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,9 @@ child-binding:
107107
Pin output drive mode. Available drive modes are pre-defined in
108108
nrf-pinctrl.h. Note that extra modes may not be available on certain
109109
devices. Defaults to standard mode for 0 and 1 (NRF_DRIVE_S0S1), the
110-
SoC default.
110+
SoC default, except for the "nordic,nrf-twi" and "nordic,nrf-twim"
111+
nodes where NRF_DRIVE_S0S1 is always overridden with NRF_DRIVE_S0D1
112+
(standard '0', disconnect '1').
111113
112114
nordic,invert:
113115
type: boolean

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