[nrf fromlist] soc: nordic: ironside: Add TDD

Upstream PR #: 92340

Added support for the IronSide TDD service which allows configuring and
powering the trace and debug domain of the nrf54h20.
Also provide option to start the trace and debug domain in the soc start
sequence.

Signed-off-by: Karsten Koenig <[email protected]>

Author: karstenkoenig

soc/nordic/ironside/CMakeLists.txt

@@ -6,5 +6,6 @@ zephyr_library()
 zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_CALL call.c)
 zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_BOOT_REPORT boot_report.c)
 zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_CPUCONF_SERVICE cpuconf.c)
+zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_TDD_SERVICE tdd.c)
 zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_UPDATE_SERVICE update.c)
 zephyr_library_sources_ifdef(CONFIG_NRF_IRONSIDE_DVFS_SERVICE dvfs.c)

soc/nordic/ironside/Kconfig

@@ -37,6 +37,12 @@ config NRF_IRONSIDE_CPUCONF_SERVICE
 	help
 	  Service used to boot local domain cores.
 
+config NRF_IRONSIDE_TDD_SERVICE
+	bool "IronSide TDD service"
+	select NRF_IRONSIDE_CALL
+	help
+	  Service used to control the trace and debug domain.
+
 config NRF_IRONSIDE_UPDATE_SERVICE
 	bool "IronSide update service"
 	select NRF_IRONSIDE_CALL

soc/nordic/ironside/include/nrf_ironside/tdd.h

@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#ifndef ZEPHYR_SOC_NORDIC_IRONSIDE_INCLUDE_NRF_IRONSIDE_TDD_H_
+#define ZEPHYR_SOC_NORDIC_IRONSIDE_INCLUDE_NRF_IRONSIDE_TDD_H_
+
+#include <nrf_ironside/call.h>
+
+#include <nrfx.h>
+
+#define IRONSIDE_SE_TDD_SERVICE_ERROR_INVALID_CONFIG (1)
+
+#define IRONSIDE_SE_CALL_ID_TDD_V0 4
+
+#define IRONSIDE_SE_TDD_SERVICE_REQ_CONFIG_IDX  0
+#define IRONSIDE_SE_TDD_SERVICE_RSP_RETCODE_IDX 0
+
+enum ironside_se_tdd_config {
+	RESERVED0 = 0, /* Reserved */
+	/** Turn off the TDD */
+	IRONSIDE_SE_TDD_CONFIG_OFF = 1,
+	/** Turn on the TDD with default configuration */
+	IRONSIDE_SE_TDD_CONFIG_ON_DEFAULT = 2,
+};
+
+/**
+ * @brief Control the Trace and Debug Domain (TDD).
+ *
+ * @param config The configuration to be applied.
+ *
+ * @retval 0 on success.
+ * @retval -IRONSIDE_SE_TDD_ERROR_EINVAL on invalid argument.
+ */
+int ironside_se_tdd_configure(const enum ironside_se_tdd_config config);
+
+#endif /* ZEPHYR_SOC_NORDIC_IRONSIDE_INCLUDE_NRF_IRONSIDE_TDD_H_ */

soc/nordic/ironside/tdd.c

@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <nrf_ironside/tdd.h>
+#include <nrf_ironside/call.h>
+
+int ironside_se_tdd_configure(const enum ironside_se_tdd_config config)
+{
+	int err;
+	struct ironside_call_buf *const buf = ironside_call_alloc();
+
+	buf->id = IRONSIDE_SE_CALL_ID_TDD_V0;
+	buf->args[IRONSIDE_SE_TDD_SERVICE_REQ_CONFIG_IDX] = (uint32_t)config;
+
+	ironside_call_dispatch(buf);
+
+	if (buf->status == IRONSIDE_CALL_STATUS_RSP_SUCCESS) {
+		err = buf->args[IRONSIDE_SE_TDD_SERVICE_RSP_RETCODE_IDX];
+	} else {
+		err = buf->status;
+	}
+
+	ironside_call_release(buf);
+
+	return err;
+}

soc/nordic/nrf54h/Kconfig

@@ -8,7 +8,6 @@ config SOC_SERIES_NRF54HX
 	select HAS_NRFX
 	select HAS_NORDIC_DRIVERS
 	select SOC_EARLY_INIT_HOOK if ARM
-	select SOC_LATE_INIT_HOOK if SOC_NRF54H20_CPURAD_ENABLE
 	select NRF_PLATFORM_HALTIUM
 	select EXPERIMENTAL if MCUBOOT
 
@@ -68,11 +67,23 @@ config SOC_NRF54H20_CPURAD_COMMON
 	select HAS_PM
 	select HAS_POWEROFF
 
+config SOC_NRF54H20_TDD_ENABLE
+	bool "Power and configure the trace and debug domain (TDD)"
+	depends on SOC_NRF54H20_CPUAPP
+	select NRF_IRONSIDE_TDD_SERVICE
+	select SOC_LATE_INIT_HOOK
+	help
+	  This will at application boot time request that the trace and
+	  debug domain (TDD) is powered up and configured.
+	  This allows configuring the coresight peripherals from
+	  the application domain.
+
 config SOC_NRF54H20_CPURAD_ENABLE
 	bool "Boot the nRF54H20 Radio core"
 	default y if NRF_802154_SER_HOST || BT_HCI_HOST
 	depends on SOC_NRF54H20_CPUAPP
 	select NRF_IRONSIDE_CPUCONF_SERVICE
+	select SOC_LATE_INIT_HOOK
 	help
 	  This will at application boot time enable clock to the
 	  Radiocore, and also power will be requested to the Radiocore

soc/nordic/nrf54h/soc.c

@@ -26,6 +26,9 @@
 #if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE)
 #include <nrf_ironside/cpuconf.h>
 #endif
+#if defined(CONFIG_SOC_NRF54H20_TDD_ENABLE)
+#include <nrf_ironside/tdd.h>
+#endif
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
@@ -171,10 +174,19 @@ void soc_early_init_hook(void)
 	}
 }
 
-#if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE)
+#if defined(CONFIG_SOC_LATE_INIT_HOOK)
+
 void soc_late_init_hook(void)
 {
-	int err;
+#if defined(CONFIG_SOC_NRF54H20_TDD_ENABLE)
+	int err_tdd;
+
+	err_tdd = ironside_se_tdd_configure(IRONSIDE_SE_TDD_CONFIG_ON_DEFAULT);
+	__ASSERT(err_tdd == 0, "err_tdd was %d", err_tdd);
+#endif
+
+#if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE)
+	int err_cpuconf;
 
 	/* The msg will be used for communication prior to IPC
 	 * communication being set up. But at this moment no such
@@ -213,8 +225,10 @@ void soc_late_init_hook(void)
 	/* Don't wait as this is not yet supported. */
 	bool cpu_wait = false;
 
-	err = ironside_cpuconf(NRF_PROCESSOR_RADIOCORE, radiocore_address, cpu_wait, msg, msg_size);
-	__ASSERT(err == 0, "err was %d", err);
+	err_cpuconf = ironside_cpuconf(NRF_PROCESSOR_RADIOCORE, radiocore_address, cpu_wait, msg,
+				       msg_size);
+	__ASSERT(err_cpuconf == 0, "err_cpuconf was %d", err_cpuconf);
+#endif
 }
 #endif