[nrf fromlist] boards: nordic: replace custom JLink reset scheme

Upstream PR #: 82976

The secure domain firmware ADAC interface has again been changed
for SDFW v9.0 with ADAC v3, which no longer supports non-essential
domain resets which the custom JLink reset scheme for
nrf54h20dk/nrf54h20/cpuapp, nrf54h20dk/nrf54h20/cpurad,
nrf9280pdk/nrf9280/cpuapp and nrf9280pdk/nrf9280/cpurad relied on.
All resets done through the ADAC interface now do a global reset
instead, which as of now "kills" the JLink session.

This commit updates the JLink scripts for these boards to provide
at least some way to debug the app/radio cores from the start of
execution. It is likely no longer possible to implement a clean reset
through the JLink scripts, and support for handling the global reset will
need to be added to the tools instead. However, it is still possible to
debug from the start of execution by resetting the device over ADAC first
and then running "west attach".

Signed-off-by: Jonathan Nilsen <[email protected]>

Author: jonathannilsen

boards/nordic/nrf54h20dk/support/nrf54h20_cpuapp.JLinkScript

@@ -11,11 +11,6 @@ __constant U32 _DHCSR_DBGKEY = (0xA05F << 16);
 __constant U32 _DHCSR_C_DEBUGEN = (1 << 0);
 __constant U32 _DHCSR_C_HALT = (1 << 1);
 
-// Debug Exception and Monitor Control Register
-__constant U32 _DEMCR_ADDR = 0xE000EDFC;
-__constant U32 _DEMCR_VC_CORERESET = (1 << 0);
-__constant U32 _DEMCR_TRCENA = (1 << 24);
-
 // CPU wait enable register
 __constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C;
 
@@ -154,7 +149,7 @@ int _DoAdacTransaction(int checkReplyStatus)
 	return 0;
 }
 
-int ResetTarget(void)
+int SetupTarget(void)
 {
 	int err;
 	U32 adacMajorVersion;
@@ -192,33 +187,6 @@ int ResetTarget(void)
 	JLINK_SYS_Report1("ADAC major version: ", adacMajorVersion);
 
 	if (adacMajorVersion >= 2) {
-		// There is a very small chance that this command fails if the domain reset itself
-		// at the exact same time the command was issued. Therefore we retry a few times.
-		i = 0;
-		while (i < 3) {
-			// Reset non-essential domains
-			_adacTx[0] = 0xA30A0000; // Command RESET
-			_adacTx[1] = 0x00000004; // Data length 4 bytes
-			_adacTx[2] = 0x00000000; // (reserved)
-			err = _DoAdacTransaction(1);
-			if (err >= 0) {
-				break;
-			} else if (err != _ERR_REPLY) {
-				return -1;
-			}
-
-			i = i + 1;
-		}
-
-		// Start the core in halted mode
-		_adacTx[0] = 0xA3090000;                         // Command START
-		_adacTx[1] = 0x00000004;                         // Data length 4 bytes
-		_adacTx[2] = 0x01000000 | (_PROCESSOR_ID << 16); // Own processor, Flags HALT
-		err = _DoAdacTransaction(1);
-		if (err < 0) {
-			return -1;
-		}
-
 		// Start other cores normally (will fail silently if no firmware is present)
 		i = 0;
 		while (i < _NUM_OTHER_PROCESSORS) {
@@ -233,28 +201,13 @@ int ResetTarget(void)
 
 			i = i + 1;
 		}
-	} else {
-		// Reset single domain via legacy implementation
-		_adacTx[0] = 0xA3030000;                      // Command RESET
-		_adacTx[1] = 0x00000004;                      // Data length 4 bytes
-		_adacTx[2] = 0x01000000 | (_DOMAIN_ID << 16); // Own domain, Mode HALT
-		err = _DoAdacTransaction(1);
-		if (err < 0) {
-			return -1;
-		}
 	}
 
 	// Halt the CPU
 	JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN));
 
-	// Set vector catch on reset (to halt the CPU immediately after reset)
-	JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA));
-
 	// Disable CPU wait
 	JLINK_MEM_WriteU32(_CPUCONF_ADDR + _CPUCONF_CPUWAIT_OFFSET, 0);
 
-	// Clear vector catch stuff
-	JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA);
-
 	return 0;
 }

boards/nordic/nrf54h20dk/support/nrf54h20_cpurad.JLinkScript

@@ -11,11 +11,6 @@ __constant U32 _DHCSR_DBGKEY = (0xA05F << 16);
 __constant U32 _DHCSR_C_DEBUGEN = (1 << 0);
 __constant U32 _DHCSR_C_HALT = (1 << 1);
 
-// Debug Exception and Monitor Control Register
-__constant U32 _DEMCR_ADDR = 0xE000EDFC;
-__constant U32 _DEMCR_VC_CORERESET = (1 << 0);
-__constant U32 _DEMCR_TRCENA = (1 << 24);
-
 // CPU wait enable register
 __constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C;
 
@@ -162,7 +157,7 @@ int ConfigTargetSettings(void)
 	return 0;
 }
 
-int ResetTarget(void)
+int SetupTarget(void)
 {
 	int err;
 	U32 adacMajorVersion;
@@ -200,33 +195,6 @@ int ResetTarget(void)
 	JLINK_SYS_Report1("ADAC major version: ", adacMajorVersion);
 
 	if (adacMajorVersion >= 2) {
-		// There is a very small chance that this command fails if the domain reset itself
-		// at the exact same time the command was issued. Therefore we retry a few times.
-		i = 0;
-		while (i < 3) {
-			// Reset non-essential domains
-			_adacTx[0] = 0xA30A0000; // Command RESET
-			_adacTx[1] = 0x00000004; // Data length 4 bytes
-			_adacTx[2] = 0x00000000; // (reserved)
-			err = _DoAdacTransaction(1);
-			if (err >= 0) {
-				break;
-			} else if (err != _ERR_REPLY) {
-				return -1;
-			}
-
-			i = i + 1;
-		}
-
-		// Start the core in halted mode
-		_adacTx[0] = 0xA3090000;                         // Command START
-		_adacTx[1] = 0x00000004;                         // Data length 4 bytes
-		_adacTx[2] = 0x01000000 | (_PROCESSOR_ID << 16); // Own processor, Flags HALT
-		err = _DoAdacTransaction(1);
-		if (err < 0) {
-			return -1;
-		}
-
 		// Start other cores normally (will fail silently if no firmware is present)
 		i = 0;
 		while (i < _NUM_OTHER_PROCESSORS) {
@@ -241,28 +209,13 @@ int ResetTarget(void)
 
 			i = i + 1;
 		}
-	} else {
-		// Reset single domain via legacy implementation
-		_adacTx[0] = 0xA3030000;                      // Command RESET
-		_adacTx[1] = 0x00000004;                      // Data length 4 bytes
-		_adacTx[2] = 0x01000000 | (_DOMAIN_ID << 16); // Own domain, Mode HALT
-		err = _DoAdacTransaction(1);
-		if (err < 0) {
-			return -1;
-		}
 	}
 
 	// Halt the CPU
 	JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN));
 
-	// Set vector catch on reset (to halt the CPU immediately after reset)
-	JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA));
-
 	// Disable CPU wait
 	JLINK_MEM_WriteU32(_CPUCONF_ADDR + _CPUCONF_CPUWAIT_OFFSET, 0);
 
-	// Clear vector catch stuff
-	JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA);
-
 	return 0;
 }

boards/nordic/nrf9280pdk/support/nrf9280_cpuapp.JLinkScript

@@ -11,11 +11,6 @@ __constant U32 _DHCSR_DBGKEY = (0xA05F << 16);
 __constant U32 _DHCSR_C_DEBUGEN = (1 << 0);
 __constant U32 _DHCSR_C_HALT = (1 << 1);
 
-// Debug Exception and Monitor Control Register
-__constant U32 _DEMCR_ADDR = 0xE000EDFC;
-__constant U32 _DEMCR_VC_CORERESET = (1 << 0);
-__constant U32 _DEMCR_TRCENA = (1 << 24);
-
 // CPU wait enable register
 __constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C;
 
@@ -154,7 +149,7 @@ int _DoAdacTransaction(int checkReplyStatus)
 	return 0;
 }
 
-int ResetTarget(void)
+int SetupTarget(void)
 {
 	int err;
 	U32 adacMajorVersion;
@@ -192,33 +187,6 @@ int ResetTarget(void)
 	JLINK_SYS_Report1("ADAC major version: ", adacMajorVersion);
 
 	if (adacMajorVersion >= 2) {
-		// There is a very small chance that this command fails if the domain reset itself
-		// at the exact same time the command was issued. Therefore we retry a few times.
-		i = 0;
-		while (i < 3) {
-			// Reset non-essential domains
-			_adacTx[0] = 0xA30A0000; // Command RESET
-			_adacTx[1] = 0x00000004; // Data length 4 bytes
-			_adacTx[2] = 0x00000000; // (reserved)
-			err = _DoAdacTransaction(1);
-			if (err >= 0) {
-				break;
-			} else if (err != _ERR_REPLY) {
-				return -1;
-			}
-
-			i = i + 1;
-		}
-
-		// Start the core in halted mode
-		_adacTx[0] = 0xA3090000;                         // Command START
-		_adacTx[1] = 0x00000004;                         // Data length 4 bytes
-		_adacTx[2] = 0x01000000 | (_PROCESSOR_ID << 16); // Own processor, Flags HALT
-		err = _DoAdacTransaction(1);
-		if (err < 0) {
-			return -1;
-		}
-
 		// Start other cores normally (will fail silently if no firmware is present)
 		i = 0;
 		while (i < _NUM_OTHER_PROCESSORS) {
@@ -233,28 +201,13 @@ int ResetTarget(void)
 
 			i = i + 1;
 		}
-	} else {
-		// Reset single domain via legacy implementation
-		_adacTx[0] = 0xA3030000;                      // Command RESET
-		_adacTx[1] = 0x00000004;                      // Data length 4 bytes
-		_adacTx[2] = 0x01000000 | (_DOMAIN_ID << 16); // Own domain, Mode HALT
-		err = _DoAdacTransaction(1);
-		if (err < 0) {
-			return -1;
-		}
 	}
 
 	// Halt the CPU
 	JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN));
 
-	// Set vector catch on reset (to halt the CPU immediately after reset)
-	JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA));
-
 	// Disable CPU wait
 	JLINK_MEM_WriteU32(_CPUCONF_ADDR + _CPUCONF_CPUWAIT_OFFSET, 0);
 
-	// Clear vector catch stuff
-	JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA);
-
 	return 0;
 }

boards/nordic/nrf9280pdk/support/nrf9280_cpurad.JLinkScript

@@ -11,11 +11,6 @@ __constant U32 _DHCSR_DBGKEY = (0xA05F << 16);
 __constant U32 _DHCSR_C_DEBUGEN = (1 << 0);
 __constant U32 _DHCSR_C_HALT = (1 << 1);
 
-// Debug Exception and Monitor Control Register
-__constant U32 _DEMCR_ADDR = 0xE000EDFC;
-__constant U32 _DEMCR_VC_CORERESET = (1 << 0);
-__constant U32 _DEMCR_TRCENA = (1 << 24);
-
 // CPU wait enable register
 __constant U32 _CPUCONF_CPUWAIT_OFFSET = 0x50C;
 
@@ -162,7 +157,7 @@ int ConfigTargetSettings(void)
 	return 0;
 }
 
-int ResetTarget(void)
+int SetupTarget(void)
 {
 	int err;
 	U32 adacMajorVersion;
@@ -200,33 +195,6 @@ int ResetTarget(void)
 	JLINK_SYS_Report1("ADAC major version: ", adacMajorVersion);
 
 	if (adacMajorVersion >= 2) {
-		// There is a very small chance that this command fails if the domain reset itself
-		// at the exact same time the command was issued. Therefore we retry a few times.
-		i = 0;
-		while (i < 3) {
-			// Reset non-essential domains
-			_adacTx[0] = 0xA30A0000; // Command RESET
-			_adacTx[1] = 0x00000004; // Data length 4 bytes
-			_adacTx[2] = 0x00000000; // (reserved)
-			err = _DoAdacTransaction(1);
-			if (err >= 0) {
-				break;
-			} else if (err != _ERR_REPLY) {
-				return -1;
-			}
-
-			i = i + 1;
-		}
-
-		// Start the core in halted mode
-		_adacTx[0] = 0xA3090000;                         // Command START
-		_adacTx[1] = 0x00000004;                         // Data length 4 bytes
-		_adacTx[2] = 0x01000000 | (_PROCESSOR_ID << 16); // Own processor, Flags HALT
-		err = _DoAdacTransaction(1);
-		if (err < 0) {
-			return -1;
-		}
-
 		// Start other cores normally (will fail silently if no firmware is present)
 		i = 0;
 		while (i < _NUM_OTHER_PROCESSORS) {
@@ -241,28 +209,13 @@ int ResetTarget(void)
 
 			i = i + 1;
 		}
-	} else {
-		// Reset single domain via legacy implementation
-		_adacTx[0] = 0xA3030000;                      // Command RESET
-		_adacTx[1] = 0x00000004;                      // Data length 4 bytes
-		_adacTx[2] = 0x01000000 | (_DOMAIN_ID << 16); // Own domain, Mode HALT
-		err = _DoAdacTransaction(1);
-		if (err < 0) {
-			return -1;
-		}
 	}
 
 	// Halt the CPU
 	JLINK_MEM_WriteU32(_DHCSR_ADDR, (_DHCSR_DBGKEY | _DHCSR_C_HALT | _DHCSR_C_DEBUGEN));
 
-	// Set vector catch on reset (to halt the CPU immediately after reset)
-	JLINK_MEM_WriteU32(_DEMCR_ADDR, (_DEMCR_VC_CORERESET | _DEMCR_TRCENA));
-
 	// Disable CPU wait
 	JLINK_MEM_WriteU32(_CPUCONF_ADDR + _CPUCONF_CPUWAIT_OFFSET, 0);
 
-	// Clear vector catch stuff
-	JLINK_MEM_WriteU32(_DEMCR_ADDR, _DEMCR_TRCENA);
-
 	return 0;
 }