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nordic-baminordic-bami
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[nrf fromlist] tests: drivers: flash: Test newly introduced MSPI driver features
These features are: - soft reset - 4B addressing (SPI mode) - supply gpios - erase size greater than 4kB Signed-off-by: Bartosz Miller <[email protected]> (cherry picked from commit 7875a4daa6c328dd0a9cb49598df16c2082a319b)
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‎tests/drivers/flash/common/boards/mx25uw63_low_freq.overlay‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
&mx25uw63 {
8+
status = "okay";
9+
mspi-max-frequency = <DT_FREQ_K(256)>;
10+
};

‎tests/drivers/flash/common/boards/mx25uw63_single_io_4B_addr_sreset.overlay‎

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/*
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* Copyright (c) 2025 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
&pinctrl {
8+
9+
/delete-node/ exmif_default;
10+
/delete-node/ exmif_sleep;
11+
12+
exmif_default: exmif_default {
13+
group1 {
14+
psels = <NRF_PSEL(EXMIF_CK, 6, 0)>,
15+
<NRF_PSEL(EXMIF_RWDS, 6, 2)>,
16+
<NRF_PSEL(EXMIF_DQ0, 6, 7)>,
17+
<NRF_PSEL(EXMIF_DQ1, 6, 5)>,
18+
<NRF_PSEL(EXMIF_DQ2, 6, 10)>,
19+
<NRF_PSEL(EXMIF_DQ3, 6, 9)>,
20+
<NRF_PSEL(EXMIF_DQ4, 6, 11)>,
21+
<NRF_PSEL(EXMIF_DQ5, 6, 8)>,
22+
<NRF_PSEL(EXMIF_DQ6, 6, 6)>,
23+
<NRF_PSEL(EXMIF_DQ7, 6, 4)>;
24+
nordic,drive-mode = <NRF_DRIVE_H0H1>;
25+
};
26+
};
27+
28+
exmif_sleep: exmif_sleep {
29+
group1 {
30+
low-power-enable;
31+
psels = <NRF_PSEL(EXMIF_CK, 6, 0)>,
32+
<NRF_PSEL(EXMIF_RWDS, 6, 2)>,
33+
<NRF_PSEL(EXMIF_DQ0, 6, 7)>,
34+
<NRF_PSEL(EXMIF_DQ1, 6, 5)>,
35+
<NRF_PSEL(EXMIF_DQ2, 6, 10)>,
36+
<NRF_PSEL(EXMIF_DQ3, 6, 9)>,
37+
<NRF_PSEL(EXMIF_DQ4, 6, 11)>,
38+
<NRF_PSEL(EXMIF_DQ5, 6, 8)>,
39+
<NRF_PSEL(EXMIF_DQ6, 6, 6)>,
40+
<NRF_PSEL(EXMIF_DQ7, 6, 4)>;
41+
};
42+
};
43+
44+
};
45+
46+
&gpio6 {
47+
status = "okay";
48+
};
49+
50+
&exmif {
51+
status = "okay";
52+
pinctrl-0 = <&exmif_default>;
53+
pinctrl-1 = <&exmif_sleep>;
54+
pinctrl-names = "default", "sleep";
55+
ce-gpios = <&gpio6 3 GPIO_ACTIVE_LOW>;
56+
};
57+
58+
&mx25uw63 {
59+
status = "okay";
60+
mspi-max-frequency = <DT_FREQ_M(50)>;
61+
mspi-io-mode = "MSPI_IO_MODE_SINGLE";
62+
use-4byte-addressing;
63+
initial-soft-reset;
64+
};

‎tests/drivers/flash/common/boards/nrf54h20dk_nrf54h20_cpuapp.overlay‎

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Original file line numberDiff line numberDiff line change
@@ -4,6 +4,16 @@
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* SPDX-License-Identifier: Apache-2.0
55
*/
66

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/ {
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zephyr,user {
9+
test-gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
10+
};
11+
};
12+
13+
&gpio0 {
14+
status = "okay";
15+
};
16+
717
&gpio6 {
818
status = "okay";
919
zephyr,pm-device-runtime-auto;
@@ -16,4 +26,5 @@
1626

1727
&mx25uw63 {
1828
status = "okay";
29+
supply-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>;
1930
};

‎tests/drivers/flash/common/src/main.c‎

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Original file line numberDiff line numberDiff line change
@@ -9,6 +9,7 @@
99
#include <zephyr/drivers/flash.h>
1010
#include <zephyr/devicetree.h>
1111
#include <zephyr/storage/flash_map.h>
12+
#include <zephyr/drivers/gpio.h>
1213

1314
#if defined(CONFIG_NORDIC_QSPI_NOR)
1415
#define TEST_AREA_DEV_NODE DT_INST(0, nordic_qspi_nor)
@@ -322,6 +323,72 @@ ZTEST(flash_driver, test_flash_erase)
322323
zassert_not_equal(expected[0], erase_value, "These values shall be different");
323324
}
324325

326+
ZTEST(flash_driver, test_flash_erase_different_block_sizes)
327+
{
328+
if (!IS_ENABLED(CONFIG_SOC_NRF54H20)) {
329+
ztest_test_skip();
330+
}
331+
332+
int rc;
333+
334+
/* There is not enough RAM memory
335+
* to allocate the read buffer
336+
* for the entire erase sector size
337+
*/
338+
uint8_t read_buffer[EXPECTED_SIZE];
339+
uint32_t offset;
340+
uint32_t erase_block_size_to_expected_size_ratio;
341+
const uint8_t erase_block_size_kB[] = {4, 64};
342+
const struct flash_parameters *fparams = flash_get_parameters(flash_dev);
343+
344+
for (int i = 0; i < ARRAY_SIZE(erase_block_size_kB); i++) {
345+
346+
TC_PRINT("Flash erase with erase size = %ukB\n", erase_block_size_kB[i]);
347+
offset = 0;
348+
349+
rc = flash_erase(flash_dev, page_info.start_offset, erase_block_size_kB[i] * 1024);
350+
zassert_equal(rc, 0, "Flash memory not properly erased: %d", rc);
351+
352+
erase_block_size_to_expected_size_ratio =
353+
(erase_block_size_kB[i] * 1024) / EXPECTED_SIZE;
354+
TC_PRINT("Erase block is %u times %uB\n", erase_block_size_to_expected_size_ratio,
355+
EXPECTED_SIZE);
356+
357+
for (int block_num = 0; block_num < erase_block_size_to_expected_size_ratio;
358+
block_num++) {
359+
rc = flash_read(flash_dev, page_info.start_offset + offset, read_buffer,
360+
EXPECTED_SIZE);
361+
zassert_equal(rc, 0, "Cannot read flash");
362+
363+
for (int i = 0; i < EXPECTED_SIZE; i++) {
364+
if (read_buffer[i] != fparams->erase_value) {
365+
zassert_equal(read_buffer[i], fparams->erase_value,
366+
"Erase value != expected erase value, "
367+
"address offset = 0x%x\n",
368+
offset + i);
369+
}
370+
}
371+
offset += EXPECTED_SIZE;
372+
}
373+
}
374+
}
375+
376+
ZTEST(flash_driver, test_supply_gpios_control)
377+
{
378+
if (!DT_NODE_HAS_PROP(TEST_AREA_DEV_NODE, supply_gpios)) {
379+
ztest_test_skip();
380+
}
381+
382+
#if DT_NODE_HAS_PROP(DT_PATH(zephyr_user), test_gpios)
383+
const struct gpio_dt_spec test_gpio =
384+
GPIO_DT_SPEC_GET(DT_PATH(zephyr_user), test_gpios);
385+
zassert_true(gpio_is_ready_dt(&test_gpio), "Test GPIO is not ready\n");
386+
zassert_ok(gpio_pin_configure_dt(&test_gpio, GPIO_INPUT | GPIO_PULL_DOWN),
387+
"Failed to configure test pin\n");
388+
zassert_equal(gpio_pin_get(test_gpio.port, test_gpio.pin), 1, "Supply GPIO is not set\n");
389+
#endif
390+
}
391+
325392
struct test_cb_data_type {
326393
uint32_t page_counter; /* used to count how many pages was iterated */
327394
uint32_t exit_page; /* terminate iteration when this page is reached */

‎tests/drivers/flash/common/src/periphconf.c‎

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@@ -0,0 +1,167 @@
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/* Generated by nrf-regtool version 9.2.1 */
2+
#include <uicr/uicr.h>
3+
4+
/* SPU131 feature configuration for 0x5f934000UL ch. 0 */
5+
UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 0, true, NRF_OWNER_APPLICATION);
6+
/* SPU131 feature configuration for 0x5f934000UL ch. 1 */
7+
UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 1, true, NRF_OWNER_APPLICATION);
8+
/* SPU131 feature configuration for 0x5f934000UL ch. 2 */
9+
UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 2, true, NRF_OWNER_APPLICATION);
10+
/* SPU131 feature configuration for 0x5f934000UL ch. 3 */
11+
UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 3, true, NRF_OWNER_APPLICATION);
12+
/* SPU131 feature configuration for 0x5f934000UL ch. 4 */
13+
UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 4, true, NRF_OWNER_APPLICATION);
14+
/* SPU131 feature configuration for 0x5f934000UL ch. 5 */
15+
UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 5, true, NRF_OWNER_APPLICATION);
16+
/* SPU131 feature configuration for 0x5f934000UL ch. 6 */
17+
UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 6, true, NRF_OWNER_APPLICATION);
18+
/* SPU131 feature configuration for 0x5f934000UL ch. 7 */
19+
UICR_SPU_FEATURE_GPIOTE_CH_SET(0x5f920000UL, 0, 7, true, NRF_OWNER_APPLICATION);
20+
/* SPU133 feature configuration for GRTC CC4 */
21+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 4, true, NRF_OWNER_APPLICATION);
22+
/* SPU133 feature configuration for GRTC CC5 */
23+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 5, false, NRF_OWNER_APPLICATION);
24+
/* SPU133 feature configuration for GRTC CC6 */
25+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 6, false, NRF_OWNER_APPLICATION);
26+
/* SPU131 feature configuration for 0x5f938c00UL, P6.0 */
27+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 0, true, NRF_OWNER_APPLICATION);
28+
/* SPU131 feature configuration for 0x5f938c00UL, P6.2 */
29+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 2, true, NRF_OWNER_APPLICATION);
30+
/* SPU131 feature configuration for 0x5f938c00UL, P6.3 */
31+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 3, true, NRF_OWNER_APPLICATION);
32+
/* SPU131 feature configuration for 0x5f938c00UL, P6.4 */
33+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 4, true, NRF_OWNER_APPLICATION);
34+
/* SPU131 feature configuration for 0x5f938c00UL, P6.5 */
35+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 5, true, NRF_OWNER_APPLICATION);
36+
/* SPU131 feature configuration for 0x5f938c00UL, P6.6 */
37+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 6, true, NRF_OWNER_APPLICATION);
38+
/* SPU131 feature configuration for 0x5f938c00UL, P6.7 */
39+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 7, true, NRF_OWNER_APPLICATION);
40+
/* SPU131 feature configuration for 0x5f938c00UL, P6.8 */
41+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 8, true, NRF_OWNER_APPLICATION);
42+
/* SPU131 feature configuration for 0x5f938c00UL, P6.9 */
43+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 9, true, NRF_OWNER_APPLICATION);
44+
/* SPU131 feature configuration for 0x5f938c00UL, P6.10 */
45+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 10, true, NRF_OWNER_APPLICATION);
46+
/* SPU131 feature configuration for 0x5f938c00UL, P6.11 */
47+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 11, true, NRF_OWNER_APPLICATION);
48+
/* SPU131 feature configuration for 0x5f938c00UL, P6.12 */
49+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 6, 12, true, NRF_OWNER_APPLICATION);
50+
/* SPU131 feature configuration for 0x5f938000UL, P0.0 */
51+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 0, true, NRF_OWNER_APPLICATION);
52+
/* SPU131 feature configuration for 0x5f938000UL, P0.1 */
53+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 1, true, NRF_OWNER_APPLICATION);
54+
/* SPU131 feature configuration for 0x5f938000UL, P0.8 */
55+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 8, true, NRF_OWNER_APPLICATION);
56+
/* SPU131 feature configuration for 0x5f938000UL, P0.9 */
57+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 9, true, NRF_OWNER_APPLICATION);
58+
/* SPU131 feature configuration for 0x5f938000UL, P0.10 */
59+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 10, true, NRF_OWNER_APPLICATION);
60+
/* SPU131 feature configuration for 0x5f938000UL, P0.11 */
61+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 0, 11, true, NRF_OWNER_APPLICATION);
62+
/* SPU131 feature configuration for 0x5f939200UL, P9.0 */
63+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 0, true, NRF_OWNER_APPLICATION);
64+
/* SPU131 feature configuration for 0x5f939200UL, P9.1 */
65+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 1, true, NRF_OWNER_APPLICATION);
66+
/* SPU131 feature configuration for 0x5f939200UL, P9.2 */
67+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 2, true, NRF_OWNER_APPLICATION);
68+
/* SPU131 feature configuration for 0x5f939200UL, P9.3 */
69+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 3, true, NRF_OWNER_APPLICATION);
70+
/* SPU131 feature configuration for 0x5f939200UL, P9.4 */
71+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 4, true, NRF_OWNER_APPLICATION);
72+
/* SPU131 feature configuration for 0x5f939200UL, P9.5 */
73+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 9, 5, true, NRF_OWNER_APPLICATION);
74+
/* SPU131 feature configuration for 0x5f938400UL, P2.4 */
75+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 2, 4, true, NRF_OWNER_APPLICATION);
76+
/* SPU131 feature configuration for 0x5f938400UL, P2.5 */
77+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 2, 5, true, NRF_OWNER_APPLICATION);
78+
/* SPU131 feature configuration for 0x5f938400UL, P2.6 */
79+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 2, 6, true, NRF_OWNER_APPLICATION);
80+
/* SPU131 feature configuration for 0x5f938400UL, P2.7 */
81+
UICR_SPU_FEATURE_GPIO_PIN_SET(0x5f920000UL, 2, 7, true, NRF_OWNER_APPLICATION);
82+
/* 0x5f938c00UL - P6.0 CTRLSEL = 4 */
83+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 0, 4);
84+
/* 0x5f938c00UL - P6.2 CTRLSEL = 4 */
85+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 2, 4);
86+
/* 0x5f938c00UL - P6.3 CTRLSEL = 4 */
87+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 3, 4);
88+
/* 0x5f938c00UL - P6.4 CTRLSEL = 4 */
89+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 4, 4);
90+
/* 0x5f938c00UL - P6.5 CTRLSEL = 4 */
91+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 5, 4);
92+
/* 0x5f938c00UL - P6.6 CTRLSEL = 4 */
93+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 6, 4);
94+
/* 0x5f938c00UL - P6.7 CTRLSEL = 4 */
95+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 7, 4);
96+
/* 0x5f938c00UL - P6.8 CTRLSEL = 4 */
97+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 8, 4);
98+
/* 0x5f938c00UL - P6.9 CTRLSEL = 4 */
99+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 9, 4);
100+
/* 0x5f938c00UL - P6.10 CTRLSEL = 4 */
101+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 10, 4);
102+
/* 0x5f938c00UL - P6.11 CTRLSEL = 4 */
103+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 11, 4);
104+
/* 0x5f938c00UL - P6.12 CTRLSEL = 0 */
105+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 12, 0);
106+
/* 0x5f938000UL - P0.0 CTRLSEL = 0 */
107+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 0, 0);
108+
/* 0x5f938000UL - P0.1 CTRLSEL = 0 */
109+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 1, 0);
110+
/* 0x5f938000UL - P0.8 CTRLSEL = 0 */
111+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 8, 0);
112+
/* 0x5f938000UL - P0.9 CTRLSEL = 0 */
113+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 9, 0);
114+
/* 0x5f938000UL - P0.10 CTRLSEL = 0 */
115+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 10, 0);
116+
/* 0x5f938000UL - P0.11 CTRLSEL = 0 */
117+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938000UL, 11, 0);
118+
/* 0x5f939200UL - P9.0 CTRLSEL = 0 */
119+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 0, 0);
120+
/* 0x5f939200UL - P9.1 CTRLSEL = 0 */
121+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 1, 0);
122+
/* 0x5f939200UL - P9.2 CTRLSEL = 2 */
123+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 2, 2);
124+
/* 0x5f939200UL - P9.3 CTRLSEL = 0 */
125+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 3, 0);
126+
/* 0x5f939200UL - P9.4 CTRLSEL = 6 */
127+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 4, 6);
128+
/* 0x5f939200UL - P9.5 CTRLSEL = 6 */
129+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 5, 6);
130+
/* 0x5f938400UL - P2.4 CTRLSEL = 0 */
131+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938400UL, 4, 0);
132+
/* 0x5f938400UL - P2.5 CTRLSEL = 0 */
133+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938400UL, 5, 0);
134+
/* 0x5f938400UL - P2.6 CTRLSEL = 0 */
135+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938400UL, 6, 0);
136+
/* 0x5f938400UL - P2.7 CTRLSEL = 0 */
137+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938400UL, 7, 0);
138+
/* SPU110 configuration for 0x5f086000UL */
139+
UICR_SPU_PERIPH_PERM_SET(0x5f080000UL, 6, true, true, NRF_OWNER_APPLICATION);
140+
/* SPU111 configuration for 0x5f095000UL */
141+
UICR_SPU_PERIPH_PERM_SET(0x5f090000UL, 5, true, false, NRF_OWNER_APPLICATION);
142+
/* SPU120 configuration for 0x5f8c2000UL */
143+
UICR_SPU_PERIPH_PERM_SET(0x5f8c0000UL, 2, true, false, NRF_OWNER_APPLICATION);
144+
/* SPU121 configuration for 0x5f8d8000UL */
145+
UICR_SPU_PERIPH_PERM_SET(0x5f8d0000UL, 8, true, true, NRF_OWNER_APPLICATION);
146+
/* SPU132 configuration for 0x5f982000UL */
147+
UICR_SPU_PERIPH_PERM_SET(0x5f980000UL, 2, true, true, NRF_OWNER_APPLICATION);
148+
/* SPU132 configuration for 0x5f985000UL */
149+
UICR_SPU_PERIPH_PERM_SET(0x5f980000UL, 5, true, true, NRF_OWNER_APPLICATION);
150+
/* SPU134 configuration for 0x5f9a4000UL */
151+
UICR_SPU_PERIPH_PERM_SET(0x5f9a0000UL, 4, true, true, NRF_OWNER_APPLICATION);
152+
/* SPU137 configuration for 0x5f9d5000UL */
153+
UICR_SPU_PERIPH_PERM_SET(0x5f9d0000UL, 5, true, true, NRF_OWNER_APPLICATION);
154+
/* 0x5f086000UL IRQ => APPLICATION */
155+
UICR_IRQMAP_IRQ_SINK_SET(134, NRF_PROCESSOR_APPLICATION);
156+
/* 0x5f095000UL IRQ => APPLICATION */
157+
UICR_IRQMAP_IRQ_SINK_SET(149, NRF_PROCESSOR_APPLICATION);
158+
/* 0x5f8d8000UL IRQ => APPLICATION */
159+
UICR_IRQMAP_IRQ_SINK_SET(216, NRF_PROCESSOR_APPLICATION);
160+
/* 0x5f982000UL IRQ => APPLICATION */
161+
UICR_IRQMAP_IRQ_SINK_SET(386, NRF_PROCESSOR_APPLICATION);
162+
/* 0x5f985000UL IRQ => APPLICATION */
163+
UICR_IRQMAP_IRQ_SINK_SET(389, NRF_PROCESSOR_APPLICATION);
164+
/* 0x5f9a4000UL IRQ => APPLICATION */
165+
UICR_IRQMAP_IRQ_SINK_SET(420, NRF_PROCESSOR_APPLICATION);
166+
/* 0x5f9d5000UL IRQ => APPLICATION */
167+
UICR_IRQMAP_IRQ_SINK_SET(469, NRF_PROCESSOR_APPLICATION);

‎tests/drivers/flash/common/testcase.yaml‎

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -156,3 +156,13 @@ tests:
156156
- nrf54h20dk/nrf54h20/cpuapp
157157
extra_args:
158158
- EXTRA_DTC_OVERLAY_FILE=boards/mx25uw63_single_io.overlay
159+
drivers.flash.common.mspi_single_io.4B_addr_soft_reset:
160+
platform_allow:
161+
- nrf54h20dk/nrf54h20/cpuapp
162+
extra_args:
163+
- EXTRA_DTC_OVERLAY_FILE=boards/mx25uw63_single_io_4B_addr_sreset.overlay
164+
drivers.flash.common.mspi_low_frequency:
165+
platform_allow:
166+
- nrf54h20dk/nrf54h20/cpuapp
167+
extra_args:
168+
- EXTRA_DTC_OVERLAY_FILE=boards/mx25uw63_low_freq.overlay

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