@@ -94,6 +94,15 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
9494#define NRF_PSEL_QSPI (reg , line ) ((NRF_QSPI_Type *)reg)->PSEL.line
9595#endif
9696
97+ #if DT_HAS_COMPAT_STATUS_OKAY (nordic_nrf_grtc ) || defined(CONFIG_NRFX_GRTC )
98+ #if DT_NODE_HAS_PROP (DT_NODELABEL (grtc ), clkout_fast_frequency )
99+ #define NRF_GRTC_CLKOUT_FAST 1
100+ #endif
101+ #if DT_NODE_HAS_PROP (DT_NODELABEL (grtc ), clkout_32k_frequency )
102+ #define NRF_GRTC_CLKOUT_SLOW 1
103+ #endif
104+ #endif
105+
97106int pinctrl_configure_pins (const pinctrl_soc_pin_t * pins , uint8_t pin_cnt ,
98107 uintptr_t reg )
99108{
@@ -336,6 +345,24 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
336345 input = NRF_GPIO_PIN_INPUT_DISCONNECT ;
337346 break ;
338347#endif /* defined(NRF_PSEL_QSPI) */
348+ #if defined(NRF_GRTC_CLKOUT_FAST )
349+ case NRF_FUN_GRTC_CLKOUT_FAST :
350+ #if NRF_GPIO_HAS_SEL && defined(GPIO_PIN_CNF_CTRLSEL_GRTC )
351+ nrf_gpio_pin_control_select (psel , NRF_GPIO_PIN_SEL_GRTC );
352+ #endif
353+ dir = NRF_GPIO_PIN_DIR_OUTPUT ;
354+ input = NRF_GPIO_PIN_INPUT_DISCONNECT ;
355+ break ;
356+ #endif /* defined(NRF_GRTC_CLKOUT_FAST) */
357+ #if defined(NRF_GRTC_CLKOUT_SLOW )
358+ case NRF_FUN_GRTC_CLKOUT_32K :
359+ #if NRF_GPIO_HAS_SEL && defined(GPIO_PIN_CNF_CTRLSEL_GRTC )
360+ nrf_gpio_pin_control_select (psel , NRF_GPIO_PIN_SEL_GRTC );
361+ #endif
362+ dir = NRF_GPIO_PIN_DIR_OUTPUT ;
363+ input = NRF_GPIO_PIN_INPUT_DISCONNECT ;
364+ break ;
365+ #endif /* defined(NRF_GRTC_CLKOUT_SLOW) */
339366#if DT_HAS_COMPAT_STATUS_OKAY (nordic_nrf_can )
340367 /* Pin routing is controlled by secure domain, via UICR */
341368 case NRF_FUN_CAN_TX :
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