drivers: spi: nrfx_spi(m/s): enable cross domain pins for nRF54L15

mstasiaknordic · mstasiaknordic · commit 23678503dad3 · 2025-05-21T15:14:50.000+02:00
SPI(M/S)20 and SPIM(M/S)21 instances enable usage of pins on different
port, but require request for constant latency mode. Added
handling of such scenario in the driver. Added testcase
to cover it.

Signed-off-by: Michał Stasiak &lt;michal.stasiak@nordicsemi.no&gt;
diff --git a/drivers/spi/spi_nrfx_spim.c b/drivers/spi/spi_nrfx_spim.c
@@ -48,6 +48,21 @@ LOG_MODULE_REGISTER(spi_nrfx_spim, CONFIG_SPI_LOG_LEVEL);
 	 defined(CONFIG_HAS_HW_NRF_SPIM121))
 #define SPIM_REQUESTS_CLOCK(idx) UTIL_OR(IS_EQ(idx, 120), \
 					 IS_EQ(idx, 121))
+/*
+ * We use NODELABEL here because the nrfx API requires us to call
+ * functions which are named according to SoC peripheral instance
+ * being operated on. Since DT_INST() makes no guarantees about that,
+ * it won't work.
+ */
+#define SPIM(idx)			DT_NODELABEL(spi##idx)
+#define SPIM_PROP(idx, prop)		DT_PROP(SPIM(idx), prop)
+#define SPIM_HAS_PROP(idx, prop)	DT_NODE_HAS_PROP(SPIM(idx), prop)
+
+#if defined(CONFIG_CLOCK_CONTROL_NRF2_GLOBAL_HSFLL)
+#define SPIM_REQUESTS_CLOCK(node) \
+	DT_NODE_HAS_COMPAT(DT_NODELABEL(DT_CLOCKS_CTLR(node)), nordic_nrf_hsfll_global)
+#define SPIM_REQUESTS_CLOCK_OR(node) SPIM_REQUESTS_CLOCK(node) ||
+#if (DT_FOREACH_STATUS_OKAY(nordic_nrf_spim, SPIM_REQUESTS_CLOCK_OR) 0)
 #define USE_CLOCK_REQUESTS 1
 /* If fast instances are used then system managed device PM cannot be used because
  * it may call PM actions from locked context and fast SPIM PM actions can only be
@@ -58,6 +73,22 @@ BUILD_ASSERT(!IS_ENABLED(CONFIG_PM_DEVICE_SYSTEM_MANAGED));
 #define SPIM_REQUESTS_CLOCK(idx) 0
 #endif
 
+#define SPIM_PINS_CROSS_DOMAIN(unused, prefix, idx, _)				\
+	COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(SPIM(prefix##idx)),		\
+		   (UTIL_AND(SPIM_PROP(idx, cross_domain_constlat_required),	\
+		    SPIM_HAS_PROP(idx, default_port))),			\
+		   (0))
+
+#if (NRFX_FOREACH_PRESENT(SPIM, SPIM_PINS_CROSS_DOMAIN, (||), (0))) && defined(CONFIG_NRFX_POWER)
+#include <hal/nrf_gpio.h>
+#include <nrfx_power.h>
+/* Macro determines if there is any SPIM instance that needs constant latency mode if using
+ * cross domain pins. To use constant latency, NRFX_POWER needs to be enabled.
+ */
+#define SPIM_ANY_PINS_CROSS_DOMAIN 1
+#endif
+
+
 struct spi_nrfx_data {
 	struct spi_context ctx;
 	const struct device *dev;
@@ -97,6 +128,10 @@ struct spi_nrfx_config {
 	const struct device *clk_dev;
 	struct nrf_clock_spec clk_spec;
 #endif
+#if SPIM_ANY_PINS_CROSS_DOMAIN
+	bool cross_domain;
+	uint8_t default_port;
+#endif
 };
 
 static void event_handler(const nrfx_spim_evt_t *p_event, void *p_context);
@@ -146,6 +181,31 @@ static inline void release_clock(const struct device *dev)
 #endif
 }
 
+#if SPIM_ANY_PINS_CROSS_DOMAIN
+static bool spim_has_cross_domain_connection(const struct spi_nrfx_config *config)
+{
+	const struct pinctrl_dev_config *pcfg = config->pcfg;
+	const struct pinctrl_state *state;
+	int ret;
+
+	ret = pinctrl_lookup_state(pcfg, PINCTRL_STATE_DEFAULT, &state);
+	if (ret < 0) {
+		LOG_ERR("Unable to read pin state");
+		return false;
+	}
+
+	for (uint8_t i = 0U; i < state->pin_cnt; i++) {
+		uint32_t pin = NRF_GET_PIN(state->pins[i]);
+
+		if (nrf_gpio_pin_port_number_extract(&pin) != config->default_port) {
+			return true;
+		}
+	}
+
+	return false;
+}
+#endif
+
 static inline void finalize_spi_transaction(const struct device *dev, bool deactivate_cs)
 {
 	struct spi_nrfx_data *dev_data = dev->data;
@@ -670,6 +730,15 @@ static int spim_resume(const struct device *dev)
 #ifdef CONFIG_SOC_NRF54H20_GPD
 	nrf_gpd_retain_pins_set(dev_config->pcfg, false);
 #endif
+#if SPIM_ANY_PINS_CROSS_DOMAIN
+	if (dev_config->cross_domain && spim_has_cross_domain_connection(dev_config)) {
+		int err;
+
+		err = nrfx_power_constlat_mode_request();
+		(void)err;
+		__ASSERT_NO_MSG(err >= 0);
+	}
+#endif
 
 	return IS_ENABLED(CONFIG_PM_DEVICE_RUNTIME) ? request_clock(dev) : 0;
 }
@@ -691,6 +760,15 @@ static void spim_suspend(const struct device *dev)
 #ifdef CONFIG_SOC_NRF54H20_GPD
 	nrf_gpd_retain_pins_set(dev_config->pcfg, true);
 #endif
+#if SPIM_ANY_PINS_CROSS_DOMAIN
+	if (dev_config->cross_domain && spim_has_cross_domain_connection(dev_config)) {
+		int err;
+
+		err = nrfx_power_constlat_mode_free();
+		(void)err;
+		__ASSERT_NO_MSG(err >= 0);
+	}
+#endif
 
 	(void)pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_SLEEP);
 }
@@ -748,15 +826,7 @@ static int spi_nrfx_init(const struct device *dev)
 #endif
 	return pm_device_driver_init(dev, spim_nrfx_pm_action);
 }
-/*
- * We use NODELABEL here because the nrfx API requires us to call
- * functions which are named according to SoC peripheral instance
- * being operated on. Since DT_INST() makes no guarantees about that,
- * it won't work.
- */
-#define SPIM(idx)			DT_NODELABEL(spi##idx)
-#define SPIM_PROP(idx, prop)		DT_PROP(SPIM(idx), prop)
-#define SPIM_HAS_PROP(idx, prop)	DT_NODE_HAS_PROP(SPIM(idx), prop)
+
 #define SPIM_MEM_REGION(idx)		DT_PHANDLE(SPIM(idx), memory_regions)
 
 #define SPI_NRFX_SPIM_EXTENDED_CONFIG(idx)				\
@@ -846,6 +916,11 @@ static int spi_nrfx_init(const struct device *dev)
 			 .clk_spec = {					       \
 				.frequency = NRF_CLOCK_CONTROL_FREQUENCY_MAX,  \
 			 },))						       \
+		IF_ENABLED(UTIL_AND(					       \
+			SPIM_PINS_CROSS_DOMAIN(_, /*empty*/, idx, _),	       \
+			CONFIG_NRFX_POWER),				       \
+			(.cross_domain = true,				       \
+			 .default_port = SPIM_PROP(idx, default_port),))       \
 	};								       \
 	BUILD_ASSERT(!SPIM_HAS_PROP(idx, wake_gpios) ||			       \
 		     !(DT_GPIO_FLAGS(SPIM(idx), wake_gpios) & GPIO_ACTIVE_LOW),\
diff --git a/drivers/spi/spi_nrfx_spis.c b/drivers/spi/spi_nrfx_spis.c
@@ -19,6 +19,8 @@
 LOG_MODULE_REGISTER(spi_nrfx_spis, CONFIG_SPI_LOG_LEVEL);
 
 #include "spi_context.h"
+#include <hal/nrf_gpio.h>
+#include <nrfx_power.h>
 
 #ifdef CONFIG_SOC_NRF54H20_GPD
 #include <nrf/gpd.h>
@@ -36,6 +38,32 @@ LOG_MODULE_REGISTER(spi_nrfx_spis, CONFIG_SPI_LOG_LEVEL);
 BUILD_ASSERT(!IS_ENABLED(CONFIG_PM_DEVICE_SYSTEM_MANAGED));
 #endif
 
+/*
+ * Current factors requiring use of DT_NODELABEL:
+ *
+ * - HAL design (requirement of drv_inst_idx in nrfx_spis_t)
+ * - Name-based HAL IRQ handlers, e.g. nrfx_spis_0_irq_handler
+ */
+#define SPIS_NODE(idx) COND_CODE_1(SPIS_IS_FAST(idx), (spis##idx), (spi##idx))
+#define SPIS(idx) DT_NODELABEL(SPIS_NODE(idx))
+#define SPIS_PROP(idx, prop) DT_PROP(SPIS(idx), prop)
+#define SPIS_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(SPIS(idx), prop)
+
+#define SPIS_PINS_CROSS_DOMAIN(unused, prefix, idx, _)				\
+	COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(SPIS(prefix##idx)),		\
+		   (UTIL_AND(SPIS_PROP(idx, cross_domain_constlat_required),	\
+		    SPIS_HAS_PROP(idx, default_port))),			\
+		   (0))
+
+#if (NRFX_FOREACH_PRESENT(SPIS, SPIS_PINS_CROSS_DOMAIN, (||), (0))) && defined(CONFIG_NRFX_POWER)
+#include <hal/nrf_gpio.h>
+#include <nrfx_power.h>
+/* Macro determines if there is any SPIS instance that needs constant latency mode if using
+ * cross domain pins. To use constant latency, NRFX_POWER needs to be enabled.
+ */
+#define SPIS_ANY_PINS_CROSS_DOMAIN 1
+#endif
+
 struct spi_nrfx_data {
 	struct spi_context ctx;
 	const struct device *dev;
@@ -54,8 +82,37 @@ struct spi_nrfx_config {
 	const struct pinctrl_dev_config *pcfg;
 	struct gpio_dt_spec wake_gpio;
 	void *mem_reg;
+#if SPIS_ANY_PINS_CROSS_DOMAIN
+	bool cross_domain;
+	uint8_t default_port;
+#endif
 };
 
+#if SPIS_ANY_PINS_CROSS_DOMAIN
+static bool spis_has_cross_domain_connection(const struct spi_nrfx_config *config)
+{
+	const struct pinctrl_dev_config *pcfg = config->pcfg;
+	const struct pinctrl_state *state;
+	int ret;
+
+	ret = pinctrl_lookup_state(pcfg, PINCTRL_STATE_DEFAULT, &state);
+	if (ret < 0) {
+		LOG_ERR("Unable to read pin state");
+		return false;
+	}
+
+	for (uint8_t i = 0U; i < state->pin_cnt; i++) {
+		uint32_t pin = NRF_GET_PIN(state->pins[i]);
+
+		if (nrf_gpio_pin_port_number_extract(&pin) != config->default_port) {
+			return true;
+		}
+	}
+
+	return false;
+}
+#endif
+
 static inline nrf_spis_mode_t get_nrf_spis_mode(uint16_t operation)
 {
 	if (SPI_MODE_GET(operation) & SPI_MODE_CPOL) {
@@ -364,6 +421,15 @@ static void spi_nrfx_suspend(const struct device *dev)
 		nrf_gpd_retain_pins_set(dev_config->pcfg, true);
 	}
 #endif
+#if SPIS_ANY_PINS_CROSS_DOMAIN
+	if (dev_config->cross_domain && spis_has_cross_domain_connection(dev_config)) {
+		int err;
+
+		err = nrfx_power_constlat_mode_free();
+		(void)err;
+		__ASSERT_NO_MSG(err >= 0);
+	}
+#endif
 
 	(void)pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_SLEEP);
 }
@@ -379,6 +445,15 @@ static void spi_nrfx_resume(const struct device *dev)
 		nrf_gpd_retain_pins_set(dev_config->pcfg, false);
 	}
 #endif
+#if SPIS_ANY_PINS_CROSS_DOMAIN
+	if (dev_config->cross_domain && spis_has_cross_domain_connection(dev_config)) {
+		int err;
+
+		err = nrfx_power_constlat_mode_request();
+		(void)err;
+		__ASSERT_NO_MSG(err >= 0);
+	}
+#endif
 
 	if (dev_config->wake_gpio.port == NULL) {
 		nrf_spis_enable(dev_config->spis.p_reg);
@@ -462,19 +537,6 @@ static int spi_nrfx_init(const struct device *dev)
 	return pm_device_driver_init(dev, spi_nrfx_pm_action);
 }
 
-/*
- * Current factors requiring use of DT_NODELABEL:
- *
- * - HAL design (requirement of drv_inst_idx in nrfx_spis_t)
- * - Name-based HAL IRQ handlers, e.g. nrfx_spis_0_irq_handler
- */
-
-#define SPIS_NODE(idx) COND_CODE_1(SPIS_IS_FAST(idx), (spis##idx), (spi##idx))
-
-#define SPIS(idx) DT_NODELABEL(SPIS_NODE(idx))
-
-#define SPIS_PROP(idx, prop) DT_PROP(SPIS(idx), prop)
-
 #define SPI_NRFX_SPIS_DEFINE(idx)					       \
 	static void irq_connect##idx(void)				       \
 	{								       \
@@ -510,6 +572,11 @@ static int spi_nrfx_init(const struct device *dev)
 				NRFX_MHZ_TO_HZ(16UL),))			       \
 		.wake_gpio = GPIO_DT_SPEC_GET_OR(SPIS(idx), wake_gpios, {0}),  \
 		.mem_reg = DMM_DEV_TO_REG(SPIS(idx)),			       \
+		IF_ENABLED(UTIL_AND(					       \
+			SPIS_PINS_CROSS_DOMAIN(_, /*empty*/, idx, _),	       \
+			CONFIG_NRFX_POWER),				       \
+			(.cross_domain = true,				       \
+			 .default_port = SPIS_PROP(idx, default_port),))       \
 	};								       \
 	BUILD_ASSERT(!DT_NODE_HAS_PROP(SPIS(idx), wake_gpios) ||	       \
 		     !(DT_GPIO_FLAGS(SPIS(idx), wake_gpios) & GPIO_ACTIVE_LOW),\
diff --git a/dts/bindings/spi/nordic,nrf-spi-common.yaml b/dts/bindings/spi/nordic,nrf-spi-common.yaml
@@ -61,3 +61,13 @@ properties:
         and SPI master again keeps the line in the low state
       Please note that the line must be configured and properly handled on
       both sides for the mechanism to work correctly.
+
+  cross-domain-constlat-required:
+    type: boolean
+    description: |
+      SPI needs constant latency mode if using cross domain pins.
+
+  default-port:
+    type: int
+    description: |
+      SPI default GPIO port.
diff --git a/dts/common/nordic/nrf54l_05_10_15.dtsi b/dts/common/nordic/nrf54l_05_10_15.dtsi
@@ -311,6 +311,8 @@
 				rx-delay-supported;
 				rx-delay = <1>;
 				status = "disabled";
+				cross-domain-constlat-required;
+				default-port = <0x1>;
 			};
 
 			uart20: uart@c6000 {
@@ -352,6 +354,8 @@
 				rx-delay-supported;
 				rx-delay = <1>;
 				status = "disabled";
+				cross-domain-constlat-required;
+				default-port = <0x1>;
 			};
 
 			uart21: uart@c7000 {
diff --git a/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp_cross_domain.overlay b/tests/drivers/spi/spi_controller_peripheral/boards/nrf54l15dk_nrf54l15_cpuapp_cross_domain.overlay
@@ -0,0 +1,73 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	spi21_default_alt: spi21_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
+				<NRF_PSEL(SPIM_MISO, 2, 9)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 8)>;
+		};
+	};
+
+	spi21_sleep_alt: spi21_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIM_SCK, 2, 6)>,
+				<NRF_PSEL(SPIM_MISO, 2, 9)>,
+				<NRF_PSEL(SPIM_MOSI, 2, 8)>;
+			low-power-enable;
+		};
+	};
+
+	spi22_default_alt: spi22_default_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 11)>,
+				<NRF_PSEL(SPIS_MISO, 1, 13)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 12)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+		};
+	};
+
+	spi22_sleep_alt: spi22_sleep_alt {
+		group1 {
+			psels = <NRF_PSEL(SPIS_SCK, 1, 11)>,
+				<NRF_PSEL(SPIS_MISO, 1, 13)>,
+				<NRF_PSEL(SPIS_MOSI, 1, 12)>,
+				<NRF_PSEL(SPIS_CSN, 1, 14)>;
+			low-power-enable;
+		};
+	};
+};
+
+&gpio2 {
+	status = "okay";
+};
+
+&spi21 {
+	status = "okay";
+	pinctrl-0 = <&spi21_default_alt>;
+	pinctrl-1 = <&spi21_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	overrun-character = <0x00>;
+	cs-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>;
+	zephyr,pm-device-runtime-auto;
+	dut_spi_dt: test-spi-dev@0 {
+		compatible = "vnd,spi-device";
+		reg = <0>;
+		spi-max-frequency = <DT_FREQ_M(1)>;
+	};
+};
+
+dut_spis: &spi22 {
+	compatible = "nordic,nrf-spis";
+	status = "okay";
+	def-char = <0x00>;
+	pinctrl-0 = <&spi22_default_alt>;
+	pinctrl-1 = <&spi22_sleep_alt>;
+	pinctrl-names = "default", "sleep";
+	/delete-property/rx-delay-supported;
+	/delete-property/rx-delay;
+};
diff --git a/tests/drivers/spi/spi_controller_peripheral/testcase.yaml b/tests/drivers/spi/spi_controller_peripheral/testcase.yaml
