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carlescufinordicjm
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[nrf fromtree] boards: nordic: nRF54L15DK: Add basic support for the L05 and L10 ICs
The nRF54L05 and nRF54L10 are identical to the nRF54L15 except for their memory sizes. Add support for emulating those ICs on the nRF54L15DK. This commit only adds support for the main application core. Support for the FLPR core may be added later. Signed-off-by: Carles Cufi <[email protected]> (cherry picked from commit 2147577)
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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4-
if BOARD_NRF54L15DK_NRF54L15_CPUAPP
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if BOARD_NRF54L15DK_NRF54L05_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP || \
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BOARD_NRF54L15DK_NRF54L15_CPUAPP
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config BT_CTLR
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default BT
@@ -10,4 +11,5 @@ config ROM_START_OFFSET
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default 0 if PARTITION_MANAGER_ENABLED
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default 0x800 if BOOTLOADER_MCUBOOT
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endif # BOARD_NRF54L15DK_NRF54L15_CPUAPP
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endif # BOARD_NRF54L15DK_NRF54L05_CPUAPP || BOARD_NRF54L15DK_NRF54L10_CPUAPP || \
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# BOARD_NRF54L15DK_NRF54L15_CPUAPP

boards/nordic/nrf54l15dk/Kconfig.nrf54l15dk

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# SPDX-License-Identifier: Apache-2.0
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config BOARD_NRF54L15DK
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select SOC_NRF54L05_CPUAPP if BOARD_NRF54L15DK_NRF54L05_CPUAPP
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select SOC_NRF54L10_CPUAPP if BOARD_NRF54L15DK_NRF54L10_CPUAPP
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select SOC_NRF54L15_CPUAPP if BOARD_NRF54L15DK_NRF54L15_CPUAPP
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select SOC_NRF54L15_CPUFLPR if BOARD_NRF54L15DK_NRF54L15_CPUFLPR || \
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BOARD_NRF54L15DK_NRF54L15_CPUFLPR_XIP

boards/nordic/nrf54l15dk/board.cmake

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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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4-
if(CONFIG_SOC_NRF54L15_CPUAPP)
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if(CONFIG_SOC_NRF54L05_CPUAPP OR CONFIG_SOC_NRF54L10_CPUAPP OR
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CONFIG_SOC_NRF54L15_CPUAPP)
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board_runner_args(jlink "--device=cortex-m33" "--speed=4000")
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elseif(CONFIG_SOC_NRF54L15_CPUFLPR)
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elseif(CONFIG_SOC_NRF54L05_CPUFLPR OR CONFIG_SOC_NRF54L10_CPUFLPR OR
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CONFIG_SOC_NRF54L15_CPUFLPR)
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board_runner_args(jlink "--speed=4000")
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endif()
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boards/nordic/nrf54l15dk/board.yml

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full_name: nRF54L15 DK
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vendor: nordic
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socs:
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- name: nrf54l05
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- name: nrf54l10
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- name: nrf54l15
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variants:
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- name: xip

boards/nordic/nrf54l15dk/nrf54l15dk_common.dtsi

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* SPDX-License-Identifier: Apache-2.0
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*/
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7-
#include "nrf54l15dk_nrf54l15-pinctrl.dtsi"
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#include "nrf54l15dk_nrf54l_05_10_15-pinctrl.dtsi"
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/ {
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leds {
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nordic/nrf54l05_cpuapp.dtsi>
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#include "nrf54l_05_10_15_cpuapp_common.dtsi"
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/ {
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compatible = "nordic,nrf54l15dk_nrf54l05-cpuapp";
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model = "Nordic nRF54L15 DK nRF54L05 Application MCU";
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chosen {
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zephyr,code-partition = &slot0_partition;
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zephyr,sram = &cpuapp_sram;
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};
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};
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/* FLPR not supported yet, give all SRAM and RRAM to the APP core */
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&cpuapp_sram {
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reg = <0x20000000 DT_SIZE_K(96)>;
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ranges = <0x0 0x20000000 DT_SIZE_K(96)>;
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};
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&cpuapp_rram {
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reg = <0x0 DT_SIZE_K(500)>;
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};
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/* These partition sizes assume no FLPR area in RRAM */
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x10000 DT_SIZE_K(100)>;
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};
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slot0_ns_partition: partition@29000 {
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label = "image-0-nonsecure";
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reg = <0x29000 DT_SIZE_K(100)>;
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};
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slot1_partition: partition@42000 {
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label = "image-1";
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reg = <0x42000 DT_SIZE_K(100)>;
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};
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slot1_ns_partition: partition@5b000 {
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label = "image-1-nonsecure";
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reg = <0x5b000 DT_SIZE_K(100)>;
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};
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storage_partition: partition@74000 {
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label = "storage";
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reg = <0x74000 DT_SIZE_K(36)>;
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};
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};
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};
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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identifier: nrf54l15dk/nrf54l05/cpuapp
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name: nRF54L15-DK-nRF54L05-Application
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type: mcu
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arch: arm
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toolchain:
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- gnuarmemb
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- xtools
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- zephyr
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sysbuild: true
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ram: 96
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flash: 100
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supported:
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- adc
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- counter
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- gpio
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- i2c
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- pwm
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- retained_mem
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- spi
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- watchdog
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- i2s
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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# Enable UART driver
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CONFIG_SERIAL=y
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# Enable console
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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# Enable GPIO
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CONFIG_GPIO=y
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# Enable MPU
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CONFIG_ARM_MPU=y
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# Enable hardware stack protection
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CONFIG_HW_STACK_PROTECTION=y
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# MPU-based null-pointer dereferencing detection cannot
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# be applied as the (0x0 - 0x400) is unmapped for this target.
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CONFIG_NULL_POINTER_EXCEPTION_DETECTION_NONE=y
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# Enable Cache
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CONFIG_CACHE_MANAGEMENT=y
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CONFIG_EXTERNAL_CACHE=y
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# Start SYSCOUNTER on driver init
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CONFIG_NRF_GRTC_START_SYSCOUNTER=y
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <nordic/nrf54l10_cpuapp.dtsi>
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#include "nrf54l_05_10_15_cpuapp_common.dtsi"
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/ {
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compatible = "nordic,nrf54l15dk_nrf54l10-cpuapp";
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model = "Nordic nRF54L15 DK nRF54L10 Application MCU";
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chosen {
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zephyr,code-partition = &slot0_partition;
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zephyr,sram = &cpuapp_sram;
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};
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};
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/* FLPR not supported yet, give all SRAM and RRAM to the APP core */
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&cpuapp_sram {
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reg = <0x20000000 DT_SIZE_K(192)>;
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ranges = <0x0 0x20000000 DT_SIZE_K(192)>;
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};
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&cpuapp_rram {
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reg = <0x0 DT_SIZE_K(1022)>;
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};
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/* These partition sizes assume no FLPR area in RRAM */
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&cpuapp_rram {
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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boot_partition: partition@0 {
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label = "mcuboot";
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reg = <0x0 DT_SIZE_K(64)>;
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};
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slot0_partition: partition@10000 {
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label = "image-0";
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reg = <0x10000 DT_SIZE_K(230)>;
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};
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slot0_ns_partition: partition@49800 {
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label = "image-0-nonsecure";
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reg = <0x49800 DT_SIZE_K(230)>;
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};
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slot1_partition: partition@83000 {
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label = "image-1";
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reg = <0x83000 DT_SIZE_K(230)>;
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};
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slot1_ns_partition: partition@bc800 {
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label = "image-1-nonsecure";
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reg = <0xbc800 DT_SIZE_K(230)>;
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};
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storage_partition: partition@f6000 {
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label = "storage";
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reg = <0xf6000 DT_SIZE_K(38)>;
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};
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};
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};
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# Copyright (c) 2024 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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identifier: nrf54l15dk/nrf54l10/cpuapp
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name: nRF54L15-DK-nRF54L10-Application
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type: mcu
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arch: arm
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toolchain:
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- gnuarmemb
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- xtools
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- zephyr
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sysbuild: true
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ram: 192
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flash: 230
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supported:
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- adc
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- counter
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- gpio
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- i2c
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- pwm
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- retained_mem
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- spi
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- watchdog
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- i2s

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