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jaz1-nordicrlubos
jaz1-nordic
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[nrf noup] drivers: pinctrl: Add SDP MSPI pin configuration
Configure SDP MSPI pins to switch their control to VPR core Signed-off-by: Jakub Zymelka <[email protected]> Signed-off-by: Andrzej Głąbek <[email protected]> Signed-off-by: Magdalena Pastula <[email protected]> (cherry picked from commit a9bcc44)
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‎drivers/pinctrl/pinctrl_nrf.c

Lines changed: 32 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -112,6 +112,18 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
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#define NRF_PSEL_TDM(reg, line) ((NRF_TDM_Type *)reg)->PSEL.line
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#endif
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#if DT_HAS_COMPAT_STATUS_OKAY(nordic_hpf_mspi_controller) || \
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defined(CONFIG_MSPI_HPF) || \
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DT_ANY_COMPAT_HAS_PROP_STATUS_OKAY(nordic_nrf_vpr_coprocessor, pinctrl_0)
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#if defined(CONFIG_SOC_SERIES_NRF54LX)
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#define NRF_PSEL_SDP_MSPI(psel) \
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nrf_gpio_pin_control_select(psel, NRF_GPIO_PIN_SEL_VPR);
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#elif defined(CONFIG_SOC_SERIES_NRF54HX)
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/* On nRF54H, pin routing is controlled by secure domain, via UICR. */
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#define NRF_PSEL_SDP_MSPI(psel)
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#endif
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#endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_hpf_mspi_controller) || ... */
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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uintptr_t reg)
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{
@@ -465,6 +477,26 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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#endif /* defined(NRF_PSEL_TWIS) */
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#if defined(NRF_PSEL_SDP_MSPI)
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case NRF_FUN_SDP_MSPI_CS0:
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case NRF_FUN_SDP_MSPI_CS1:
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case NRF_FUN_SDP_MSPI_CS2:
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case NRF_FUN_SDP_MSPI_CS3:
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case NRF_FUN_SDP_MSPI_CS4:
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case NRF_FUN_SDP_MSPI_SCK:
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case NRF_FUN_SDP_MSPI_DQ0:
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case NRF_FUN_SDP_MSPI_DQ1:
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case NRF_FUN_SDP_MSPI_DQ2:
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case NRF_FUN_SDP_MSPI_DQ3:
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case NRF_FUN_SDP_MSPI_DQ4:
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case NRF_FUN_SDP_MSPI_DQ5:
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case NRF_FUN_SDP_MSPI_DQ6:
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case NRF_FUN_SDP_MSPI_DQ7:
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NRF_PSEL_SDP_MSPI(psel);
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dir = NRF_GPIO_PIN_DIR_OUTPUT;
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input = NRF_GPIO_PIN_INPUT_CONNECT;
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break;
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#endif /* defined(NRF_PSEL_SDP_MSPI) */
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default:
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return -ENOTSUP;
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}

‎include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h

Lines changed: 56 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -172,6 +172,62 @@
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#define NRF_FUN_GRTC_CLKOUT_FAST 55U
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/** GRTC slow clock output */
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#define NRF_FUN_GRTC_CLKOUT_32K 56U
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/** SDP_MSPI clock pin */
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#define NRF_FUN_SDP_MSPI_SCK 57U
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/** SDP_MSPI data pin 0 */
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#define NRF_FUN_SDP_MSPI_DQ0 58U
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/** SDP_MSPI data pin 1 */
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#define NRF_FUN_SDP_MSPI_DQ1 59U
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/** SDP_MSPI data pin 2 */
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#define NRF_FUN_SDP_MSPI_DQ2 60U
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/** SDP_MSPI data pin 3 */
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#define NRF_FUN_SDP_MSPI_DQ3 61U
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/** SDP_MSPI data pin 4 */
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#define NRF_FUN_SDP_MSPI_DQ4 62U
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/** SDP_MSPI data pin 5 */
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#define NRF_FUN_SDP_MSPI_DQ5 63U
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/** SDP_MSPI data pin 6 */
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#define NRF_FUN_SDP_MSPI_DQ6 64U
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/** SDP_MSPI data pin 7 */
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#define NRF_FUN_SDP_MSPI_DQ7 65U
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/** SDP_MSPI chip select 0 */
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#define NRF_FUN_SDP_MSPI_CS0 66U
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/** SDP_MSPI chip select 1 */
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#define NRF_FUN_SDP_MSPI_CS1 67U
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/** SDP_MSPI chip select 2 */
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#define NRF_FUN_SDP_MSPI_CS2 68U
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/** SDP_MSPI chip select 3 */
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#define NRF_FUN_SDP_MSPI_CS3 69U
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/** SDP_MSPI chip select 4 */
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#define NRF_FUN_SDP_MSPI_CS4 70U
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/** High-Performance Framework MSPI clock pin */
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#define NRF_FUN_HPF_MSPI_SCK NRF_FUN_SDP_MSPI_SCK
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/** High-Performance Framework MSPI data pin 0 */
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#define NRF_FUN_HPF_MSPI_DQ0 NRF_FUN_SDP_MSPI_DQ0
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/** High-Performance Framework MSPI data pin 1 */
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#define NRF_FUN_HPF_MSPI_DQ1 NRF_FUN_SDP_MSPI_DQ1
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/** High-Performance Framework MSPI data pin 2 */
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#define NRF_FUN_HPF_MSPI_DQ2 NRF_FUN_SDP_MSPI_DQ2
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/** High-Performance Framework MSPI data pin 3 */
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#define NRF_FUN_HPF_MSPI_DQ3 NRF_FUN_SDP_MSPI_DQ3
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/** High-Performance Framework MSPI data pin 4 */
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#define NRF_FUN_HPF_MSPI_DQ4 NRF_FUN_SDP_MSPI_DQ4
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/** High-Performance Framework MSPI data pin 5 */
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#define NRF_FUN_HPF_MSPI_DQ5 NRF_FUN_SDP_MSPI_DQ5
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/** High-Performance Framework MSPI data pin 6 */
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#define NRF_FUN_HPF_MSPI_DQ6 NRF_FUN_SDP_MSPI_DQ6
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/** High-Performance Framework MSPI data pin 7 */
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#define NRF_FUN_HPF_MSPI_DQ7 NRF_FUN_SDP_MSPI_DQ7
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/** High-Performance Framework MSPI chip select pin 0 */
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#define NRF_FUN_HPF_MSPI_CS0 NRF_FUN_SDP_MSPI_CS0
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/** High-Performance Framework MSPI chip select pin 1 */
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#define NRF_FUN_HPF_MSPI_CS1 NRF_FUN_SDP_MSPI_CS1
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/** High-Performance Framework MSPI chip select pin 2 */
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#define NRF_FUN_HPF_MSPI_CS2 NRF_FUN_SDP_MSPI_CS2
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/** High-Performance Framework MSPI chip select pin 3 */
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#define NRF_FUN_HPF_MSPI_CS3 NRF_FUN_SDP_MSPI_CS3
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/** High-Performance Framework MSPI chip select pin 4 */
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#define NRF_FUN_HPF_MSPI_CS4 NRF_FUN_SDP_MSPI_CS4
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/** TDM SCK in master mode */
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#define NRF_FUN_TDM_SCK_M 71U
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/** TDM SCK in slave mode */

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