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[nrf fromtree] soc: nxp: Add MCXW71
Add MCXW71 SOC, which inherits some qualitiies of kinetis heritage platforms. Signed-off-by: Declan Snyder <[email protected]> (cherry picked from commit cbee39e)
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‎soc/nxp/mcx/mcxw/CMakeLists.txt‎

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# Copyright 2023 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(soc.c mcxw71_platform_init.S)
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zephyr_include_directories(.)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

‎soc/nxp/mcx/mcxw/Kconfig‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_MCXW
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select ARM
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select CPU_CORTEX_M33
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select CPU_CORTEX_M_HAS_DWT
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select ARM_TRUSTZONE_M
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_HAS_FPU
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select ARMV8_M_DSP
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select HAS_MCUX
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select PLATFORM_SPECIFIC_INIT
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select CLOCK_CONTROL

‎soc/nxp/mcx/mcxw/Kconfig.defconfig‎

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# Copyright 2023-2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_MCXW
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config NUM_IRQS
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default 76
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 96000000 if CORTEX_M_SYSTICK
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endif # SOC_SERIES_MCXW

‎soc/nxp/mcx/mcxw/Kconfig.soc‎

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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_MCXW
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bool
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select SOC_FAMILY_NXP_MCX
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config SOC_SERIES
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default "mcxw" if SOC_SERIES_MCXW
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config SOC_MCXW716C
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bool
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select SOC_SERIES_MCXW
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config SOC
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default "mcxw716c" if SOC_MCXW716C
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config SOC_PART_NUMBER_MCXW716CMFTA
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bool
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config SOC_PART_NUMBER
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default "MCXW716CMFTA" if SOC_PART_NUMBER_MCXW716CMFTA

‎soc/nxp/mcx/mcxw/linker.ld‎

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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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m_sector_size = 0x2000;
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m_flash_end = 0x000FFFFF;
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m_fsl_prodInfo_size = m_sector_size;
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m_fsl_prodInfo_start = m_flash_end - m_fsl_prodInfo_size + 1;
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m_fsl_prodInfo_end = m_flash_end;
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PROD_DATA_BASE_ADDR = m_fsl_prodInfo_start;
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/*
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* We perform all custom placement before including the generic linker file. This
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* is done because calling this linker at the beginning will place some sections
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* first, such as .noinit*, and this includes the rpmsg_sh_mem, which results
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* in placing the rpmsg section in RAM instead of shared mem.
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*/
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#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>

‎soc/nxp/mcx/mcxw/mcxw71_platform_init.S‎

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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief MCXW71 Platform-Specific Initialization
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*
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* MCXW71 SOC reset code that initializes RAM
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* to prevent ECC causing faults, and calls SystemInit
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*/
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#include <zephyr/toolchain.h>
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#include <zephyr/linker/sections.h>
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_ASM_FILE_PROLOGUE
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#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
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GTEXT(z_arm_platform_init)
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SECTION_SUBSEC_FUNC(TEXT,_reset_section,z_arm_platform_init)
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.z_arm_platform_init:
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ldr r0, =0x14000000
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ldr r1, =.ram_init_ctcm01
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bics r1, #0x10000000
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cmp r0, r1
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bcc .ram_init_done
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.ram_init_ctcm01: /* Initialize ctcm01 */
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ldr r0, =0x14000000
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ldr r1, =0x14004000
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ldr r2, =0
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ldr r3, =0
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ldr r4, =0
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ldr r5, =0
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.loop01:
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stmia r0!, {r2 - r5}
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cmp r0, r1
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bcc .loop01
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.ram_init_stcm012: /* Initialize stcm012 */
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ldr r0, =0x30000000
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ldr r1, =0x30010000
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.loop012:
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stmia r0!, {r2 - r5}
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cmp r0, r1
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bcc .loop012
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.ram_init_stcm5:
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ldr r0, =0x3001a000
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ldr r1, =0x3001c000
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.loop5: /* Initialize stcm5 */
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stmia r0!, {r2 - r5}
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cmp r0, r1
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bcc .loop5
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.ram_init_done:
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b SystemInit
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#endif /* CONFIG_PLATFORM_SPECIFIC_INIT */

‎soc/nxp/mcx/mcxw/pinctrl_soc.h‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl/pinctrl_soc_kinetis_common.h>

‎soc/nxp/mcx/mcxw/soc.c‎

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/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/linker/sections.h>
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#include <soc.h>
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#include <fsl_ccm32k.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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extern uint32_t SystemCoreClock;
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static ALWAYS_INLINE void clock_init(void)
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{
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/* Unlock Reference Clock Status Registers to allow writes */
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CLOCK_UnlockFircControlStatusReg();
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CLOCK_UnlockSircControlStatusReg();
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CLOCK_UnlockRoscControlStatusReg();
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CLOCK_UnlockSysOscControlStatusReg();
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/*
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* Configuration for the 32 kHz Oscillator module
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* Internal capatitor bank is required in order to use the more stable OSC32K source
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*/
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ccm32k_osc_config_t ccm32k_osc_config = {
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.coarseAdjustment = kCCM32K_OscCoarseAdjustmentRange0, /* ESR_Range0 */
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.enableInternalCapBank = true, /* Internal capacitance bank is enabled */
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.xtalCap = kCCM32K_OscXtal8pFCap, /* 8 pF */
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.extalCap = kCCM32K_OscExtal8pFCap, /* 8 pF */
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};
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/* Enable OSC32K */
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CCM32K_Set32kOscConfig(CCM32K, kCCM32K_Enable32kHzCrystalOsc, &ccm32k_osc_config);
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/* Disable ROSC Monitor, because switching the source would generate an expected error */
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CLOCK_SetRoscMonitorMode(kSCG_RoscMonitorDisable);
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/* Select the Real Time Clock (RTC) source as OSC32K */
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CCM32K_SelectClockSource(CCM32K, kCCM32K_ClockSourceSelectOsc32k);
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/* Wait for RTC Oscillator to be Valid */
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while (!CLOCK_IsRoscValid())
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;
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/* Re-enable monitor */
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CLOCK_SetRoscMonitorMode(kSCG_RoscMonitorInt);
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/* Disable the FRO32K to save power */
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CCM32K_Enable32kFro(CCM32K, false);
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/* Configuration to set FIRC to maximum frequency */
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scg_firc_config_t scg_firc_config = {
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.enableMode = kSCG_FircEnable, /* Fast IRC is enabled */
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.range = kSCG_FircRange96M, /* 96 Mhz FIRC clock selected */
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.trimConfig = NULL,
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};
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scg_sys_clk_config_t sys_clk_safe_config_source = {
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.divSlow = (uint32_t)kSCG_SysClkDivBy4,
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.divCore = (uint32_t)kSCG_SysClkDivBy1,
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.src = (uint32_t)kSCG_SysClkSrcSirc,
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};
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CLOCK_SetRunModeSysClkConfig(&sys_clk_safe_config_source);
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scg_sys_clk_config_t cur_config;
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do {
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CLOCK_GetCurSysClkConfig(&cur_config);
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} while (cur_config.src != sys_clk_safe_config_source.src);
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(void)CLOCK_InitFirc(&scg_firc_config);
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scg_sys_clk_config_t sys_clk_config = {
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.divSlow = (uint32_t)kSCG_SysClkDivBy4, /* Slow Clock Divider: divided by 4 */
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.divBus = (uint32_t)kSCG_SysClkDivBy1, /* Bus Clock Divider: divided by 1 */
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.divCore = (uint32_t)kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
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.src = (uint32_t)kSCG_SysClkSrcFirc, /* Select Fast IRC as System Clock */
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};
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CLOCK_SetRunModeSysClkConfig(&sys_clk_config);
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/* Wait for clock source switch to finish */
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do {
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CLOCK_GetCurSysClkConfig(&cur_config);
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} while (cur_config.src != sys_clk_config.src);
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SystemCoreClock = 96000000U;
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/* OSC-RF / System Oscillator Configuration */
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scg_sosc_config_t sosc_config = {
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.freq = 32000U,
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.monitorMode = kSCG_SysOscMonitorDisable,
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.enableMode = kSCG_SoscEnable,
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};
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/* Init OSC-RF / SOSC */
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(void)CLOCK_InitSysOsc(&sosc_config);
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CLOCK_SetXtal0Freq(sosc_config.freq);
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/* Slow internal reference clock (SIRC) configuration */
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scg_sirc_config_t sirc_config = {
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.enableMode = kSCG_SircDisableInSleep,
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};
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/* Init SIRC */
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(void)CLOCK_InitSirc(&sirc_config);
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/* Attach Clocks */
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CLOCK_SetIpSrc(kCLOCK_Lpuart0, kCLOCK_IpSrcFro192M);
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CLOCK_SetIpSrc(kCLOCK_Lpuart1, kCLOCK_IpSrcFro192M);
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CLOCK_SetIpSrc(kCLOCK_Lpspi0, kCLOCK_IpSrcFro192M);
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CLOCK_SetIpSrc(kCLOCK_Lpspi1, kCLOCK_IpSrcFro192M);
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CLOCK_SetIpSrc(kCLOCK_Can0, kCLOCK_IpSrcFro192M);
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CLOCK_SetIpSrc(kCLOCK_Tpm0, kCLOCK_IpSrcFro192M);
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CLOCK_SetIpSrc(kCLOCK_Tpm1, kCLOCK_IpSrcFro192M);
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CLOCK_SetIpSrc(kCLOCK_Lpi2c0, kCLOCK_IpSrcFro192M);
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CLOCK_SetIpSrcDiv(kCLOCK_Lpi2c0, kSCG_SysClkDivBy16);
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CLOCK_SetIpSrc(kCLOCK_Lpi2c1, kCLOCK_IpSrcFro192M);
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CLOCK_SetIpSrcDiv(kCLOCK_Lpi2c1, kSCG_SysClkDivBy16);
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/* Ungate clocks if the peripheral is enabled in devicetree */
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#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart0), nxp_lpc_lpuart, okay))
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CLOCK_EnableClock(kCLOCK_Lpuart0);
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#endif
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#if (DT_NODE_HAS_COMPAT_STATUS(DT_NODELABEL(lpuart1), nxp_lpc_lpuart, okay))
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CLOCK_EnableClock(kCLOCK_Lpuart1);
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#endif
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}
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static void vbat_init(void)
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{
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VBAT_Type *base = (VBAT_Type *)DT_REG_ADDR(DT_NODELABEL(vbat));
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/* Write 1 to Clear POR detect status bit.
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*
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* Clearing this bit is acknowledement
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* that software has recognized a power on reset.
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*
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* This avoids also niche issues with NVIC read/write
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* when searching for available interrupt lines.
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*/
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base->STATUSA |= VBAT_STATUSA_POR_DET_MASK;
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};
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static int nxp_mcxw71_init(void)
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{
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unsigned int oldLevel; /* old interrupt lock level */
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/* disable interrupts */
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oldLevel = irq_lock();
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/* Initialize system clock to 40 MHz */
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clock_init();
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/* Smart power switch initialization */
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vbat_init();
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/* restore interrupt state */
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irq_unlock(oldLevel);
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return 0;
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}
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SYS_INIT(nxp_mcxw71_init, PRE_KERNEL_1, 0);

‎soc/nxp/mcx/mcxw/soc.h‎

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/*
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* Copyright 2023 NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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#include <fsl_port.h>
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#define PORT_MUX_GPIO kPORT_MuxAsGpio
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#endif /* _SOC__H_ */

‎soc/nxp/mcx/soc.yml‎

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- name: mcxa
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socs:
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- name: mcxa156
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- name: mcxw
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socs:
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- name: mcxw716c
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runners:
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run_once:
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'--erase':

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