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[nrf fromlist] drivers: clock_control: Separated nrf hfclk192m shim from nrf clock shim.
Separated clock_control_nrf_hfclk192m shim from clock_control_nrf shim. Upstream PR #: 99290 Signed-off-by: Michal Frankiewicz <[email protected]>
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‎drivers/clock_control/CMakeLists.txt‎

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@@ -63,6 +63,7 @@ zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_AUXPLL clock_cont
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_HFCLK clock_control_nrf_hfclk.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_XO clock_control_nrf_xo.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_LFCLK clock_control_nrf_lfclk.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_HFCLK192M clock_control_nrf_hfclk192m.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_NRF_COMMON clock_control_nrf_common.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BOUFFALOLAB_BL60X clock_control_bl60x.c)
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zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BOUFFALOLAB_BL61X clock_control_bl61x.c)

‎drivers/clock_control/Kconfig.nrf‎

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@@ -344,6 +344,12 @@ config CLOCK_CONTROL_NRF_LFCLK
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select CLOCK_CONTROL_NRF_COMMON
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default y
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config CLOCK_CONTROL_NRF_HFCLK192M
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bool "NRF HFCLK192M driver support"
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depends on DT_HAS_NORDIC_NRF_CLOCK_HFCLK192M_ENABLED
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select CLOCK_CONTROL_NRF_COMMON
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default y
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config CLOCK_CONTROL_NRF_AUXPLL
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bool "nRF Auxiliary PLL driver"
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default y

‎drivers/clock_control/clock_control_nrf_hfclk192m.c‎

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@@ -0,0 +1,321 @@
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/*
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* Copyright (c) 2016-2020 Nordic Semiconductor ASA
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* Copyright (c) 2016 Vinayak Kariappa Chettimada
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <zephyr/sys/onoff.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/nrf_clock_control.h>
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#include "nrf_clock_calibration.h"
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#include "clock_control_nrf_common.h"
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#include <nrfx_clock_hfclk192m.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/shell/shell.h>
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#include <zephyr/irq.h>
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LOG_MODULE_REGISTER(clock_control_hfclk192m, CONFIG_CLOCK_CONTROL_LOG_LEVEL);
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#define DT_DRV_COMPAT nordic_nrf_clock_hfclk192m
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#define CLOCK_DEVICE_HFCLK192M DEVICE_DT_GET(DT_NODELABEL(hfclk192m))
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#define CTX_ONOFF BIT(6)
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#define CTX_API BIT(7)
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#define CTX_MASK (CTX_ONOFF | CTX_API)
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#define STATUS_MASK 0x7
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#define GET_STATUS(flags) (flags & STATUS_MASK)
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#define GET_CTX(flags) (flags & CTX_MASK)
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/* Helper logging macros. */
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#ifdef CONFIG_LOG
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#define CLOCK_LOG(lvl, dev, ...) \
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LOG_##lvl("%s: " GET_ARG_N(1, __VA_ARGS__), \
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"hfclk192m" COND_CODE_0(NUM_VA_ARGS_LESS_1(__VA_ARGS__),\
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(), (, GET_ARGS_LESS_N(1, __VA_ARGS__))))
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#else
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#define CLOCK_LOG(...)
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#endif
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#define ERR(dev, ...) CLOCK_LOG(ERR, dev, __VA_ARGS__)
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#define WRN(dev, ...) CLOCK_LOG(WRN, dev, __VA_ARGS__)
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#define INF(dev, ...) CLOCK_LOG(INF, dev, __VA_ARGS__)
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#define DBG(dev, ...) CLOCK_LOG(DBG, dev, __VA_ARGS__)
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typedef void (*clk_ctrl_func_t)(void);
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typedef struct {
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struct onoff_manager mgr;
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clock_control_cb_t cb;
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void *user_data;
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uint32_t flags;
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} hfclk192m_data_t;
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typedef struct {
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clk_ctrl_func_t start; /* Clock start function */
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clk_ctrl_func_t stop; /* Clock stop function */
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} hfclk192m_config_t;
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static int set_off_state(uint32_t *flags, uint32_t ctx)
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{
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int err = 0;
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unsigned int key = irq_lock();
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uint32_t current_ctx = GET_CTX(*flags);
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if ((current_ctx != 0) && (current_ctx != ctx)) {
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err = -EPERM;
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} else {
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*flags = CLOCK_CONTROL_STATUS_OFF;
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}
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irq_unlock(key);
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return err;
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}
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static int set_starting_state(uint32_t *flags, uint32_t ctx)
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{
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int err = 0;
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unsigned int key = irq_lock();
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uint32_t current_ctx = GET_CTX(*flags);
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if ((*flags & (STATUS_MASK)) == CLOCK_CONTROL_STATUS_OFF) {
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*flags = CLOCK_CONTROL_STATUS_STARTING | ctx;
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} else if (current_ctx != ctx) {
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err = -EPERM;
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} else {
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err = -EALREADY;
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}
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irq_unlock(key);
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return err;
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}
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static void set_on_state(uint32_t *flags)
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{
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unsigned int key = irq_lock();
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*flags = CLOCK_CONTROL_STATUS_ON | GET_CTX(*flags);
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irq_unlock(key);
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}
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static void clkstarted_handle(const struct device *dev)
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{
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clock_control_cb_t callback = ((hfclk192m_data_t *)dev->data)->cb;
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((hfclk192m_data_t *)dev->data)->cb = NULL;
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set_on_state(&((hfclk192m_data_t *)dev->data)->flags);
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DBG(dev, "Clock started");
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if (callback) {
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callback(dev, NULL, (hfclk192m_data_t *)dev->data)->user_data);
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}
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}
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static void hfclk192m_start(void)
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{
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nrfx_clock_hfclk192m_start();
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}
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static void hfclk192m_stop(void)
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{
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nrfx_clock_hfclk192m_stop();
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}
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static int stop(const struct device *dev, uint32_t ctx)
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{
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int err;
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err = set_off_state(&((hfclk192m_data_t *)dev->data)->flags, ctx);
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if (err < 0) {
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return err;
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}
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((hfclk192m_config_t *)dev->config)->stop();
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return 0;
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}
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static int async_start(const struct device *dev, clock_control_cb_t cb, void *user_data,
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uint32_t ctx)
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{
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int err;
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err = set_starting_state(&((hfclk192m_data_t *)dev->data)->flags, ctx);
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if (err < 0) {
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return err;
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}
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((hfclk192m_data_t *)dev->data)->cb = cb;
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((hfclk192m_data_t *)dev->data)->user_data = user_data;
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((hfclk192m_config_t *)dev->config)->start();
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return 0;
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}
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static void blocking_start_callback(const struct device *dev, clock_control_subsys_t subsys,
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void *user_data)
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{
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ARG_UNUSED(subsys);
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struct k_sem *sem = user_data;
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k_sem_give(sem);
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}
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static void onoff_stop(struct onoff_manager *mgr, onoff_notify_fn notify)
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{
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int res;
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res = stop(CLOCK_DEVICE_HFCLK192M, CTX_ONOFF);
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notify(mgr, res);
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}
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static void onoff_started_callback(const struct device *dev, clock_control_subsys_t sys,
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void *user_data)
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{
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ARG_UNUSED(sys);
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onoff_notify_fn notify = user_data;
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notify(&((hfclk192m_data_t *)dev->data)->mgr, 0);
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}
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static void onoff_start(struct onoff_manager *mgr, onoff_notify_fn notify)
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{
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int err;
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err = async_start(CLOCK_DEVICE_HFCLK192M, onoff_started_callback, notify, CTX_ONOFF);
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if (err < 0) {
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notify(mgr, err);
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}
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}
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static void clock_event_handler(void)
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{
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const struct device *dev = CLOCK_DEVICE_HFCLK192M;
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clkstarted_handle(dev);
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}
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static int api_start(const struct device *dev, clock_control_subsys_t subsys, clock_control_cb_t cb,
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void *user_data)
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{
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ARG_UNUSED(subsys);
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return async_start(dev, cb, user_data, CTX_API);
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}
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static int api_blocking_start(const struct device *dev, clock_control_subsys_t subsys)
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{
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struct k_sem sem = Z_SEM_INITIALIZER(sem, 0, 1);
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int err;
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if (!IS_ENABLED(CONFIG_MULTITHREADING)) {
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return -ENOTSUP;
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}
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err = api_start(dev, subsys, blocking_start_callback, &sem);
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if (err < 0) {
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return err;
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}
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return k_sem_take(&sem, K_MSEC(500));
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}
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static int api_stop(const struct device *dev, clock_control_subsys_t subsys)
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{
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ARG_UNUSED(subsys);
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return stop(dev, CTX_API);
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}
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static enum clock_control_status api_get_status(const struct device *dev,
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clock_control_subsys_t subsys)
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{
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ARG_UNUSED(subsys);
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return GET_STATUS(((hfclk192m_data_t *)dev->data)->flags);
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}
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static int api_request(const struct device *dev, const struct nrf_clock_spec *spec,
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struct onoff_client *cli)
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{
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hfclk192m_data_t *dev_data = dev->data;
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ARG_UNUSED(spec);
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return onoff_request(&dev_data->mgr, cli);
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}
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static int api_release(const struct device *dev, const struct nrf_clock_spec *spec)
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{
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hfclk192m_data_t *dev_data = dev->data;
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ARG_UNUSED(spec);
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return onoff_release(&dev_data->mgr);
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}
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static int api_cancel_or_release(const struct device *dev, const struct nrf_clock_spec *spec,
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struct onoff_client *cli)
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{
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hfclk192m_data_t *dev_data = dev->data;
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ARG_UNUSED(spec);
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return onoff_cancel_or_release(&dev_data->mgr, cli);
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}
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static int clk_init(const struct device *dev)
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{
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int err;
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static const struct onoff_transitions transitions = {.start = onoff_start,
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.stop = onoff_stop};
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clock_control_nrf_common_connect_irq();
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if (nrfx_clock_hfclk192m_init(clock_event_handler) != 0) {
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return -EIO;
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}
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err = onoff_manager_init(&((hfclk192m_data_t *)dev->data)->mgr, &transitions);
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if (err < 0) {
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return err;
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}
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((hfclk192m_data_t *)dev->data)->flags = CLOCK_CONTROL_STATUS_OFF;
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return 0;
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}
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CLOCK_CONTROL_NRF_IRQ_HANDLERS_ITERABLE(clock_control_nrf_hfclk192m,
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&nrfx_clock_hfclk192m_irq_handler);
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static DEVICE_API(nrf_clock_control, clock_control_api) = {
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.std_api =
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{
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.on = api_blocking_start,
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.off = api_stop,
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.async_on = api_start,
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.get_status = api_get_status,
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},
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.request = api_request,
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.release = api_release,
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.cancel_or_release = api_cancel_or_release,
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};
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static hfclk192m_data_t data;
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static const hfclk192m_config_t config = {
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.start = hfclk192m_start,
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.stop = hfclk192m_stop,
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};
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DEVICE_DT_DEFINE(DT_NODELABEL(hfclk192m), clk_init, NULL, &data, &config, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY, &clock_control_api);

‎dts/arm/nordic/nrf5340_cpuapp_peripherals.dtsi‎

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@@ -82,6 +82,13 @@ lfclk: lfclk@5000 {
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status = "okay";
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};
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hfclk192m: hfclk192m@5000 {
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compatible = "nordic,nrf-clock-hfclk192m";
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reg = <0x5000 0x1000>;
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interrupts = <5 NRF_DEFAULT_IRQ_PRIORITY>;
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status = "okay";
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};
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power: power@5000 {
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compatible = "nordic,nrf-power";
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reg = <0x5000 0x1000>;

‎dts/bindings/clock/nordic,nrf-clock-hfclk192m.yaml‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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description: Nordic nRF hfclk192m clock control node
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compatible: "nordic,nrf-clock-hfclk192m"
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include: base.yaml
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properties:
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reg:
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required: true
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interrupts:
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required: true

‎tests/drivers/clock_control/clock_control_api/testcase.yaml‎

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@@ -21,6 +21,7 @@ tests:
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- nrf51dk/nrf51822
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- nrf52dk/nrf52832
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- nrf52840dk/nrf52840
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- nrf5340dk/nrf5340/cpuapp
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- nrf9160dk/nrf9160
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- nrf54l15dk/nrf54l15/cpuapp
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- nrf54l15dk/nrf54l15/cpuapp/ns

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