arch: riscv: added helper config to include isr wrapper

Added helper Kcoinfig option USE_ISR_WRAPPER which can be used to
include isr_wrapper even if GEN_SW_ISR_TABLE is not enabled. This
is needed to enable configurations where only IRQ vector table is
used with multithreading (only direct isr used). This change is
backward compatibible with previous config.

Signed-off-by: Łukasz Stępnicki <[email protected]>

Author: lstnl

arch/riscv/Kconfig

@@ -262,6 +262,15 @@ config RISCV_GENERIC_TOOLCHAIN
 	  Allow SOCs that have custom extended riscv ISA to still
 	  compile with generic riscv32 toolchain.
 
+config USE_ISR_WRAPPER
+	bool "Use isr_wrapper to handle interrupt and/or exception/fault"
+	default y if GEN_SW_ISR_TABLE
+	default y if MULTITHREADING
+	help
+	  This is helper config to be able to use exception handling
+	  when GEN_SW_ISR_TABLE is not used but multithreading is, which
+	  needs exception handling and thread entry/switch functions.
+
 config GEN_ISR_TABLES
 	default y
 

arch/riscv/core/CMakeLists.txt

@@ -26,7 +26,7 @@ endif()
 zephyr_library_sources_ifdef(CONFIG_FPU_SHARING fpu.c fpu.S)
 zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
 zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
-zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr.S)
+zephyr_library_sources_ifdef(CONFIG_USE_ISR_WRAPPER isr.S)
 zephyr_library_sources_ifdef(CONFIG_RISCV_PMP pmp.c pmp.S)
 zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)

arch/riscv/core/isr.S

@@ -73,6 +73,7 @@ GTEXT(__soc_is_irq)
 #endif
 GTEXT(__soc_handle_irq)
 GTEXT(z_riscv_fault)
+GTEXT(z_irq_spurious)
 #ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
 GTEXT(__soc_save_context)
 GTEXT(__soc_restore_context)
@@ -331,6 +332,7 @@ no_fp:	/* increment _current->arch.exception_depth */
 	 * function (that needs to be implemented by each SOC). The result is
 	 * returned via register a0 (1: interrupt, 0 exception)
 	 */
+
 #ifdef CONFIG_RISCV_SOC_EXCEPTION_FROM_IRQ
 	jal ra, __soc_is_irq
 	bnez a0, is_interrupt
@@ -646,6 +648,7 @@ on_irq_stack:
 	 */
 	jal ra, __soc_handle_irq
 
+#if defined CONFIG_GEN_SW_ISR_TABLE
 	/*
 	 * Call corresponding registered function in _sw_isr_table.
 	 * (table is 2-word wide, we should shift index accordingly)
@@ -659,6 +662,12 @@ on_irq_stack:
 
 	/* Load ISR function address in register t1 */
 	lr t1, RV_REGSIZE(t0)
+#else
+	/* Load spurious interrupt function in case _sw_isr_table does not exist */
+	la t1, z_irq_spurious
+	/* NULL as parameter */
+	li a0, 0
+#endif
 
 	/* Call ISR function */
 	jalr ra, t1, 0

soc/common/riscv-privileged/vector.S

@@ -12,7 +12,7 @@ GTEXT(__start)
 
 /* imports */
 GTEXT(__initialize)
-#if defined(CONFIG_GEN_SW_ISR_TABLE)
+#if defined(CONFIG_USE_ISR_WRAPPER)
 GTEXT(_isr_wrapper)
 #endif
 
@@ -41,7 +41,7 @@ SECTION_FUNC(vectors, __start)
 	 * mtvec.base must be aligned to 64 bytes (this is done using
 	 * CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT)
 	 */
-#if defined(CONFIG_GEN_SW_ISR_TABLE)
+#if defined(CONFIG_USE_ISR_WRAPPER)
 	la t0, _isr_wrapper
 #else
 	add t0, zero, zero