[nrf fromlist] soc: nordic: add IRONside SE compatible UICR support

Upstream PR #: 91005

Add support for generating UICR and associated artifacts in a
format compatible with IRONside SE, to be used for nRF SoCs
in the Haltium family.

The main feature added with this is the ability to configure certain
global domain peripherals that are managed by the secure domain
through setting UICR.PERIPHCONF. This register points at a blob of
(register address, register value) pairs which are loaded
into the peripherals by IRONside SE ahead of the application boot.

The added helper macros in uicr.h can be used to add register
configurations to the PERIPHCONF. Entries added through these macros
are then extracted by a script, post-processed and placed in a blob
located at specific part of MRAM.

A default PERIPHCONF configuration has been added for the nrf54h20
soc to support the standard BLE use case.

Signed-off-by: Jonathan Nilsen <[email protected]>

Author: jonathannilsen

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map_iron.dtsi

@@ -100,5 +100,11 @@
 		storage_partition: partition@1a8000 {
 			reg = <0x1a8000 DT_SIZE_K(40)>;
 		};
+
+		periphconf_partition: partition@1b2000 {
+			compatible = "zephyr,memory-region";
+			reg = <0x1b2000 DT_SIZE_K(8)>;
+			zephyr,memory-region = "PERIPHCONF";
+		};
 	};
 };

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_iron.dts

@@ -9,6 +9,25 @@
 #include "nrf54h20dk_nrf54h20-memory_map_iron.dtsi"
 
 /delete-node/ &cpusec_cpurad_ipc;
+/delete-node/ &cpuapp_uicr;
+
+/ {
+	soc {
+		uicr: uicr@fff8000 {
+			compatible = "zephyr,memory-region", "nordic,nrf-uicr";
+			zephyr,memory-region = "UICR";
+			reg = <0xfff8000 DT_SIZE_K(2)>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			ranges = <0x0 0xfff8000 DT_SIZE_K(2)>;
+
+			bicr: bicr@7b0 {
+				compatible = "nordic,nrf-bicr";
+				reg = <0x7b0 48>;
+			};
+		};
+	};
+};
 
 / {
 	chosen {

soc/nordic/common/CMakeLists.txt

@@ -3,6 +3,10 @@
 
 add_subdirectory_ifdef(CONFIG_RISCV_CORE_NORDIC_VPR vpr)
 
+if((CONFIG_NRF_PERIPHCONF_SECTION OR CONFIG_NRF_HALTIUM_GENERATE_UICR))
+  add_subdirectory(uicr)
+endif()
+
 # Let SystemInit() be called in place of soc_reset_hook() by default.
 zephyr_linker_symbol(SYMBOL soc_reset_hook EXPR "@SystemInit@")
 

soc/nordic/common/Kconfig

@@ -49,3 +49,4 @@ source "subsys/logging/Kconfig.template.log_config"
 endif # MRAM_LATENCY
 
 rsource "vpr/Kconfig"
+rsource "uicr/Kconfig"

soc/nordic/common/uicr/CMakeLists.txt

@@ -0,0 +1,42 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+if(CONFIG_NRF_PERIPHCONF_SECTION)
+  zephyr_linker_sources(SECTIONS uicr.ld)
+endif()
+
+if(CONFIG_NRF_HALTIUM_GENERATE_UICR)
+  set(uicr_hex_file ${PROJECT_BINARY_DIR}/uicr.hex)
+  set(periphconf_hex_file ${PROJECT_BINARY_DIR}/periphconf.hex)
+
+  set(uicrgen_command
+    ${CMAKE_COMMAND} -E env PYTHONPATH=${ZEPHYR_BASE}/scripts/dts/python-devicetree/src
+    ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_LIST_DIR}/uicrgen.py
+    --in-config ${DOTCONFIG}
+    --in-edt-pickle ${EDT_PICKLE}
+    --in-periphconf-elf $<TARGET_FILE:${ZEPHYR_LINK_STAGE_EXECUTABLE}>
+    --out-uicr-hex ${uicr_hex_file}
+    --out-periphconf-hex ${periphconf_hex_file}
+  )
+
+  if(CONFIG_NRF_HALTIUM_UICR_INCLUDE_IN_IMAGE)
+    set(uicr_source_file ${PROJECT_BINARY_DIR}/uicr_generated.c)
+    add_custom_command(
+      OUTPUT ${uicr_hex_file} ${periphconf_hex_file} ${uicr_source_file}
+      COMMAND ${uicrgen_command} --out-uicr-source ${uicr_source_file}
+      DEPENDS ${ZEPHYR_LINK_STAGE_EXECUTABLE}
+    )
+    add_library(generate_uicr_lib OBJECT ${uicr_source_file})
+    target_link_libraries(generate_uicr_lib PRIVATE zephyr_interface)
+
+    set_property(
+      GLOBAL APPEND
+      PROPERTY GENERATED_KERNEL_OBJECT_FILES $<TARGET_OBJECTS:generate_uicr_lib>
+    )
+  else()
+    set_property(
+      GLOBAL APPEND
+      PROPERTY extra_post_build_commands COMMAND ${uicrgen_command}
+    )
+  endif()
+endif()

soc/nordic/common/uicr/Kconfig

@@ -0,0 +1,41 @@
+# Copyright (c) 2025 Nordic Semiconductor ASA
+# SPDX-License-Identifier: Apache-2.0
+
+config NRF_HALTIUM_GENERATE_UICR
+	bool "Generate UICR file"
+	depends on SOC_NRF54H20_CPUAPP
+	depends on SOC_NRF54H20_IRON
+	default y
+	help
+	  Generate UICR HEX file.
+
+if NRF_HALTIUM_GENERATE_UICR
+
+config NRF_HALTIUM_UICR_PERIPHCONF
+	bool "Initialize global domain peripherals"
+	default y
+	depends on NRF_PERIPHCONF_SECTION
+	help
+	  Generates a blob containing static global domain peripheral initialization
+	  values extracted from the build artifacts, and configures UICR.PERIPHCONF
+	  to point at the blob. The initialization values are then loaded ahead of
+	  ahead of the application boot.
+
+config NRF_HALTIUM_UICR_INCLUDE_IN_IMAGE
+	bool "Include UICR data in the final binary"
+	default y
+	help
+	  Include static values for the UICR and PERIPHCONF areas in the
+	  final binary image.
+
+endif
+
+config NRF_PERIPHCONF_SECTION
+	bool "Populate global peripheral initialization section"
+	default y if SOC_NRF54H20_CPUAPP
+	depends on SOC_NRF54H20_IRON
+	depends on LINKER_DEVNULL_SUPPORT
+	imply LINKER_DEVNULL_MEMORY
+	help
+	  Include static global domain peripheral initialization values from the
+	  build in a dedicated section in the devnull region.