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[nrf fromtree] drivers: udc_dwc2: Avoid endpoint disable timeouts on bus reset
DWC2 core automatically clears USBActEP (for all endpoints other than endpoint 0) on bus reset. While core is deactivating the endpoint, it does not disarm it. On bus reset USB stack first calls ep_disable API and then ep_dequeue. This was leading to endpoint is not active warning followed by endpoint disable timeout. Disable timeout was effectively caused by waiting for EPDisbld interrupt on endpoint with disabled interrupts. Solve the issue by unconditionally disarming endpoint in ep_disable API handler. Remove the false warning because USBActEP cannot really be used for sanity checking as it is not only the driver that clears it. Signed-off-by: Tomasz Moń <[email protected]> (cherry picked from commit 6f0a400)
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drivers/usb/udc/udc_dwc2.c

Lines changed: 4 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -1748,20 +1748,11 @@ static int udc_dwc2_ep_deactivate(const struct device *dev,
17481748
dxepctl_reg = dwc2_get_dxepctl_reg(dev, cfg->addr);
17491749
}
17501750

1751-
dxepctl = sys_read32(dxepctl_reg);
1752-
1753-
if (dxepctl & USB_DWC2_DEPCTL_USBACTEP) {
1754-
LOG_DBG("Disable ep 0x%02x DxEPCTL%u %x",
1755-
cfg->addr, ep_idx, dxepctl);
1756-
1757-
udc_dwc2_ep_disable(dev, cfg, false, true);
1751+
udc_dwc2_ep_disable(dev, cfg, false, true);
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1759-
dxepctl = sys_read32(dxepctl_reg);
1760-
dxepctl &= ~USB_DWC2_DEPCTL_USBACTEP;
1761-
} else {
1762-
LOG_WRN("ep 0x%02x is not active DxEPCTL%u %x",
1763-
cfg->addr, ep_idx, dxepctl);
1764-
}
1753+
dxepctl = sys_read32(dxepctl_reg);
1754+
LOG_DBG("Disable ep 0x%02x DxEPCTL%u %x", cfg->addr, ep_idx, dxepctl);
1755+
dxepctl &= ~USB_DWC2_DEPCTL_USBACTEP;
17651756

17661757
if (USB_EP_DIR_IS_IN(cfg->addr) && udc_mps_ep_size(cfg) != 0U &&
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ep_idx != 0U) {

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