[nrf noup] soc: nrf54h: work around missing power domain handling

This patch should be dropped as part of the next upmerge.

The upcoming release of IronSide SE no longer disables RETAIN
in all GPIO instances on boot, so the application must be able
to handle the hardware default state of RETAIN being enabled.

The GPIO retention is properly handled by changes that are
currently only upstream and will be pulled in by the next upmerge.
This patch exists a workaround to be able to integrate
IronSide SE before the proper solution is pulled in.

Signed-off-by: Jonathan Nilsen <[email protected]>

Author: jonathannilsen

soc/nordic/nrf54h/soc.c

@@ -14,6 +14,7 @@
 #include <zephyr/logging/log_frontend_stmesp.h>
 #endif
 
+#include <hal/nrf_gpio.h>
 #include <hal/nrf_hsfll.h>
 #include <hal/nrf_lrcconf.h>
 #include <hal/nrf_spu.h>
@@ -143,6 +144,18 @@ bool z_arm_on_enter_cpu_idle(void)
 }
 #endif
 
+static void disable_all_gpio_retention(void)
+{
+	NRF_GPIO_Type *gpio_regs[GPIO_COUNT] = GPIO_REG_LIST;
+
+	/* Some pins may not be owned by this core, depending on the configuration. The effect of
+	 * this should be that retention is disabled only for the pins owned by this core.
+	 */
+	for (int i = 0; i < NRFX_ARRAY_SIZE(gpio_regs); i++) {
+		nrf_gpio_port_retain_set(gpio_regs[i], 0);
+	}
+}
+
 void soc_early_init_hook(void)
 {
 	int err;
@@ -173,6 +186,11 @@ void soc_early_init_hook(void)
 	    DT_PROP_OR(DT_NODELABEL(nfct), nfct_pins_as_gpios, 0)) {
 		nrf_nfct_pad_config_enable_set(NRF_NFCT, false);
 	}
+
+	/* This is a workaround for not yet having upstream patches for properly handling
+	 * pin retention. It should be removed as part of the next upmerge.
+	 */
+	disable_all_gpio_retention();
 }
 
 #if defined(CONFIG_SOC_LATE_INIT_HOOK)