[nrf fromlist] drivers: udc_dwc2: Set bit 17 if needed on Hibernation Exit

Programming Guide states that bit 17 on PCGCCTL writes should be set if
the controller was enumerated for High Speed operation. Add the missing
bit set to adhere to the Programming Guide.

Upstream PR #: 85039

Signed-off-by: Tomasz Moń <[email protected]>

Author: tmon-nordic

drivers/usb/common/usb_dwc2_hw.h

@@ -997,6 +997,33 @@ USB_DWC2_SET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE)
 
 /* Power and Clock Gating Control Register */
 #define USB_DWC2_PCGCCTL			0x0E00UL
+#define USB_DWC2_PCGCCTL_IF_DEV_MODE_POS	31UL
+#define USB_DWC2_PCGCCTL_IF_DEV_MODE		BIT(USB_DWC2_PCGCCTL_IF_DEV_MODE_POS)
+#define USB_DWC2_PCGCCTL_P2HD_PRT_SPD_POS	29UL
+#define USB_DWC2_PCGCCTL_P2HD_PRT_SPD_MASK	(0x3UL << USB_DWC2_PCGCCTL_P2HD_PRT_SPD_POS)
+#define USB_DWC2_PCGCCTL_P2HD_PRT_SPD_LS	2
+#define USB_DWC2_PCGCCTL_P2HD_PRT_SPD_FS	1
+#define USB_DWC2_PCGCCTL_P2HD_PRT_SPD_HS	0
+#define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_POS	27UL
+#define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_MASK	(0x3UL << USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_POS)
+#define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_FS48	3
+#define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_LS	2
+#define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_FS	1
+#define USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_HS	0
+#define USB_DWC2_PCGCCTL_MAC_DEV_ADDR_POS	20UL
+#define USB_DWC2_PCGCCTL_MAC_DEV_ADDR_MASK	(0x7FUL << USB_DWC2_PCGCCTL_MAC_DEV_ADDR_POS)
+#define USB_DWC2_PCGCCTL_MAX_TERMSELECT_POS	19UL
+#define USB_DWC2_PCGCCTL_MAX_TERMSELECT		BIT(USB_DWC2_PCGCCTL_MAX_TERMSELECT_POS)
+#define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_POS	17UL
+#define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_MASK	(0x3UL << USB_DWC2_PCGCCTL_MAC_XCVRSELECT_POS)
+#define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_LFS	3
+#define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_LS	2
+#define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_FS	1
+#define USB_DWC2_PCGCCTL_MAC_XCVRSELECT_HS	0
+#define USB_DWC2_PCGCCTL_SH2PL_PRT_CTL0_POS	16UL
+#define USB_DWC2_PCGCCTL_SH2PL_PRT_CTL0		BIT(USB_DWC2_PCGCCTL_SH2PL_PRT_CTL0_POS)
+#define USB_DWC2_PCGCCTL_PRT_CLK_SEL_POS	14UL
+#define USB_DWC2_PCGCCTL_PRT_CLK_SEL_MASK	(0x3UL << USB_DWC2_PCGCCTL_PRT_CLK_SEL_POS)
 #define USB_DWC2_PCGCCTL_RESTOREVALUE_POS	14UL
 #define USB_DWC2_PCGCCTL_RESTOREVALUE_MASK	(0x3FFFFUL << USB_DWC2_PCGCCTL_RESTOREVALUE_POS)
 #define USB_DWC2_PCGCCTL_ESSREGRESTORED_POS	13UL
@@ -1016,6 +1043,11 @@ USB_DWC2_SET_FIELD_DEFINE(doeptsizn_xfersize, DOEPTSIZN_XFERSIZE)
 #define USB_DWC2_PCGCCTL_STOPPCLK_POS		0UL
 #define USB_DWC2_PCGCCTL_STOPPCLK		BIT(USB_DWC2_PCGCCTL_STOPPCLK_POS)
 
+USB_DWC2_GET_FIELD_DEFINE(pcgcctl_p2hd_prt_spd, PCGCCTL_P2HD_PRT_SPD)
+USB_DWC2_GET_FIELD_DEFINE(pcgcctl_p2hd_dev_enum_spd, PCGCCTL_P2HD_DEV_ENUM_SPD)
+USB_DWC2_GET_FIELD_DEFINE(pcgcctl_mac_dev_addr, PCGCCTL_MAC_DEV_ADDR)
+USB_DWC2_GET_FIELD_DEFINE(pcgcctl_mac_xcvrselect, PCGCCTL_MAC_XCVRSELECT)
+USB_DWC2_GET_FIELD_DEFINE(pcgcctl_prt_clk_sel, PCGCCTL_PRT_CLK_SEL)
 USB_DWC2_GET_FIELD_DEFINE(pcgcctl_restorevalue, PCGCCTL_RESTOREVALUE)
 USB_DWC2_SET_FIELD_DEFINE(pcgcctl_restorevalue, PCGCCTL_RESTOREVALUE)
 

drivers/usb/udc/udc_dwc2.c

@@ -915,6 +915,11 @@ static void dwc2_restore_essential_registers(const struct device *dev,
 	struct dwc2_reg_backup *backup = &priv->backup;
 	uint32_t pcgcctl = backup->pcgcctl & USB_DWC2_PCGCCTL_RESTOREVALUE_MASK;
 
+	if (usb_dwc2_get_pcgcctl_p2hd_dev_enum_spd(pcgcctl) ==
+	    USB_DWC2_PCGCCTL_P2HD_DEV_ENUM_SPD_HS) {
+		pcgcctl |= BIT(17);
+	}
+
 	sys_write32(backup->glpmcfg, (mem_addr_t)&base->glpmcfg);
 	sys_write32(backup->gi2cctl, (mem_addr_t)&base->gi2cctl);
 	sys_write32(pcgcctl, (mem_addr_t)&base->pcgcctl);