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[nrf fromtree] drivers: flash_mspi_nor: Flash control commands to use their own configs
Also in preparation for allowing control command frequency to be different from the read/write frequency and initialization frequency. Signed-off-by: Utsav Munendra <[email protected]> (cherry picked from commit abd35f8)
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-28
lines changed

2 files changed

+24
-28
lines changed

drivers/flash/flash_mspi_nor.c

Lines changed: 22 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -94,10 +94,14 @@ static int perform_xfer(const struct device *dev, uint8_t cmd)
9494
dev_data->packet.cmd = cmd;
9595
}
9696

97-
if (dev_config->multi_io_cmd ||
98-
dev_config->mspi_nor_cfg.io_mode == MSPI_IO_MODE_SINGLE) {
99-
/* If multiple IO lines are used in all the transfer phases
100-
* or in none of them, there's no need to switch the IO mode.
97+
if (!dev_data->chip_initialized ||
98+
dev_config->multi_io_cmd ||
99+
dev_config->mspi_nor_cfg.io_mode == MSPI_IO_MODE_SINGLE) {
100+
/* Commands before chip is initialized manually apply a MSPI config
101+
* which all flash chips support by JEDEC standard. Do not switch
102+
* to device tree config yet.
103+
* If multiple IO lines are used in all the transfer phases
104+
* there's no need to switch the IO mode.
101105
*/
102106
} else if (mem_access) {
103107
/* For commands accessing the flash memory (read and program),
@@ -107,26 +111,13 @@ static int perform_xfer(const struct device *dev, uint8_t cmd)
107111
cfg = &dev_config->mspi_nor_cfg;
108112
}
109113
} else {
110-
/* For all other commands, switch to Single IO mode if a given
111-
* command needs the data or address phase and in the target IO
112-
* mode multiple IO lines are used in these phases.
113-
*/
114-
if (dev_data->in_target_io_mode) {
115-
if (dev_data->packet.num_bytes != 0 ||
116-
(dev_data->xfer.addr_length != 0 &&
117-
!dev_config->single_io_addr)) {
118-
/* Only the IO mode is to be changed, so the
119-
* initial configuration structure can be used
120-
* for this operation.
121-
*/
122-
cfg = &dev_config->mspi_nor_init_cfg;
123-
}
124-
}
114+
/* For all other commands, use control command config */
115+
cfg = &dev_config->mspi_control_cfg;
125116
}
126117

127118
if (cfg && cfg != dev_data->last_applied_cfg) {
128119
rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id,
129-
MSPI_DEVICE_CONFIG_IO_MODE, cfg);
120+
MSPI_DEVICE_CONFIG_IO_MODE | MSPI_DEVICE_CONFIG_FREQUENCY, cfg);
130121
if (rc < 0) {
131122
LOG_ERR("%s: dev_config() failed: %d", __func__, rc);
132123
return rc;
@@ -981,12 +972,12 @@ static int soft_reset(const struct device *dev)
981972

982973
rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id,
983974
MSPI_DEVICE_CONFIG_IO_MODE,
984-
&dev_config->mspi_nor_init_cfg);
975+
&dev_config->mspi_control_cfg);
985976
if (rc < 0) {
986977
LOG_ERR("%s: dev_config() failed: %d", __func__, rc);
987978
return rc;
988979
}
989-
dev_data->last_applied_cfg = &dev_config->mspi_nor_init_cfg;
980+
dev_data->last_applied_cfg = &dev_config->mspi_control_cfg;
990981
dev_data->in_target_io_mode = false;
991982
}
992983

@@ -1003,20 +994,23 @@ static int flash_chip_init(const struct device *dev)
1003994
{
1004995
const struct flash_mspi_nor_config *dev_config = dev->config;
1005996
struct flash_mspi_nor_data *dev_data = dev->data;
997+
struct mspi_dev_cfg mspi_nor_init_cfg;
1006998
uint8_t id[JESD216_READ_ID_LEN] = {0};
1007999
uint16_t dts_cmd = 0;
10081000
uint32_t sfdp_signature;
10091001
bool flash_reset = false;
10101002
int rc;
10111003

1004+
/* Do initial checks at max 50MHz required to be supported by JEDEC */
1005+
memcpy(&mspi_nor_init_cfg, &dev_config->mspi_control_cfg, sizeof(mspi_nor_init_cfg));
1006+
mspi_nor_init_cfg.freq = MIN(dev_config->mspi_control_cfg.freq, MHZ(50));
10121007
rc = mspi_dev_config(dev_config->bus, &dev_config->mspi_id,
10131008
MSPI_DEVICE_CONFIG_ALL,
1014-
&dev_config->mspi_nor_init_cfg);
1009+
&mspi_nor_init_cfg);
10151010
if (rc < 0) {
10161011
LOG_ERR("%s: dev_config() failed: %d", __func__, rc);
10171012
return rc;
10181013
}
1019-
dev_data->last_applied_cfg = &dev_config->mspi_nor_init_cfg;
10201014
dev_data->in_target_io_mode = false;
10211015

10221016
#if defined(WITH_SUPPLY_GPIO)
@@ -1115,6 +1109,7 @@ static int flash_chip_init(const struct device *dev)
11151109
LOG_ERR("Failed to switch to target io mode: %d", rc);
11161110
return rc;
11171111
}
1112+
dev_data->chip_initialized = true;
11181113

11191114
dev_data->in_target_io_mode = true;
11201115

@@ -1267,10 +1262,10 @@ static DEVICE_API(flash, drv_api) = {
12671262
#endif
12681263
};
12691264

1270-
#define FLASH_INITIAL_CONFIG(inst) \
1265+
#define FLASH_CONTROL_CMD_CONFIG(inst) \
12711266
{ \
12721267
.ce_num = DT_INST_PROP_OR(inst, mspi_hardware_ce_num, 0), \
1273-
.freq = MIN(DT_INST_PROP(inst, mspi_max_frequency), MHZ(50)), \
1268+
.freq = DT_INST_PROP(inst, mspi_max_frequency), \
12741269
.io_mode = MSPI_IO_MODE_SINGLE, \
12751270
.data_rate = MSPI_DATA_RATE_SINGLE, \
12761271
.cpp = MSPI_CPP_MODE_0, \
@@ -1336,7 +1331,7 @@ BUILD_ASSERT((FLASH_SIZE(inst) % CONFIG_FLASH_MSPI_NOR_LAYOUT_PAGE_SIZE) == 0, \
13361331
.page_size = FLASH_PAGE_SIZE(inst), \
13371332
.mspi_id = MSPI_DEVICE_ID_DT_INST(inst), \
13381333
.mspi_nor_cfg = MSPI_DEVICE_CONFIG_DT_INST(inst), \
1339-
.mspi_nor_init_cfg = FLASH_INITIAL_CONFIG(inst), \
1334+
.mspi_control_cfg = FLASH_CONTROL_CMD_CONFIG(inst), \
13401335
IF_ENABLED(CONFIG_MSPI_XIP, \
13411336
(.xip_cfg = MSPI_XIP_CONFIG_DT_INST(inst),)) \
13421337
IF_ENABLED(WITH_SUPPLY_GPIO, \

drivers/flash/flash_mspi_nor.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -75,7 +75,7 @@ struct flash_mspi_nor_config {
7575
uint16_t page_size;
7676
struct mspi_dev_id mspi_id;
7777
struct mspi_dev_cfg mspi_nor_cfg;
78-
struct mspi_dev_cfg mspi_nor_init_cfg;
78+
struct mspi_dev_cfg mspi_control_cfg;
7979
#if defined(CONFIG_MSPI_XIP)
8080
struct mspi_xip_cfg xip_cfg;
8181
#endif
@@ -115,6 +115,7 @@ struct flash_mspi_nor_data {
115115
struct flash_mspi_nor_switch_info switch_info;
116116
bool in_target_io_mode;
117117
const struct mspi_dev_cfg *last_applied_cfg;
118+
bool chip_initialized;
118119
};
119120

120121
#ifdef __cplusplus

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