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22 | 22 |
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23 | 23 | LOG_MODULE_REGISTER(pwm_nrfx, CONFIG_PWM_LOG_LEVEL); |
24 | 24 |
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25 | | -#if NRF_ERRATA_STATIC_CHECK(52, 109) |
26 | | -#define ANOMALY_109_EGU_IRQ_CONNECT(idx) _EGU_IRQ_CONNECT(idx) |
27 | | -#define _EGU_IRQ_CONNECT(idx) \ |
28 | | - extern void nrfx_egu_##idx##_irq_handler(void); \ |
29 | | - IRQ_CONNECT(DT_IRQN(DT_NODELABEL(egu##idx)), \ |
30 | | - DT_IRQ(DT_NODELABEL(egu##idx), priority), \ |
31 | | - nrfx_isr, nrfx_egu_##idx##_irq_handler, 0) |
32 | | -#else |
33 | | -#define ANOMALY_109_EGU_IRQ_CONNECT(idx) |
34 | | -#endif |
35 | | - |
36 | 25 | #define PWM_NRFX_IS_FAST(inst) NRF_DT_IS_FAST(DT_DRV_INST(inst)) |
37 | 26 |
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38 | 27 | #if NRF_DT_INST_ANY_IS_FAST |
@@ -78,6 +67,42 @@ struct pwm_nrfx_data { |
78 | 67 | bool clock_requested; |
79 | 68 | #endif |
80 | 69 | }; |
| 70 | + |
| 71 | +#if NRF_ERRATA_STATIC_CHECK(52, 109) |
| 72 | +/* Forward-declare pwm_nrfx_<inst>_data structs to be able to access nrfx_pwm_t needed for the |
| 73 | + * workaround. |
| 74 | + */ |
| 75 | +#define _PWM_DATA_STRUCT_NAME_GET(inst) pwm_nrfx_##inst##_data |
| 76 | +#define _PWM_DATA_STRUCT_DECLARE(inst) static struct pwm_nrfx_data _PWM_DATA_STRUCT_NAME_GET(inst); |
| 77 | +DT_INST_FOREACH_STATUS_OKAY(_PWM_DATA_STRUCT_DECLARE); |
| 78 | + |
| 79 | +/* Create an array of pointers to all active PWM instances to loop over them in an EGU interrupt |
| 80 | + * handler. |
| 81 | + */ |
| 82 | +#define _PWM_DATA_STRUCT_PWM_PTR_COMMA_GET &_PWM_DATA_STRUCT_NAME_GET(inst).pwm, |
| 83 | +static const nrfx_pwm_t *pwm_instances[] = { |
| 84 | + DT_INST_FOREACH_STATUS_OKAY(_PWM_DATA_STRUCT_PWM_PTR_COMMA_GET) |
| 85 | +}; |
| 86 | + |
| 87 | +/* Define an interrupt handler for the EGU instance used by the workaround which calls |
| 88 | + * nrfx_pwm_ftpan_109_handler for all active PWM instances. |
| 89 | + */ |
| 90 | +void CONCAT(nrfx_egu_, idx, _irq_handler)(void) |
| 91 | +{ |
| 92 | + for (int i = 0; i < ARRAY_SIZE(pwm_instances); i++) { |
| 93 | + nrfx_pwm_ftpan_109_handler(pwm_instances[i]); |
| 94 | + } |
| 95 | +} |
| 96 | + |
| 97 | +#define ANOMALY_109_EGU_IRQ_CONNECT(idx) _EGU_IRQ_CONNECT(idx) |
| 98 | +#define _EGU_IRQ_CONNECT(idx) \ |
| 99 | + IRQ_CONNECT(DT_IRQN(DT_NODELABEL(egu##idx)), \ |
| 100 | + DT_IRQ(DT_NODELABEL(egu##idx), priority), \ |
| 101 | + NULL, nrfx_egu_##idx##_irq_handler, 0) |
| 102 | +#else |
| 103 | +#define ANOMALY_109_EGU_IRQ_CONNECT(idx) |
| 104 | +#endif |
| 105 | + |
81 | 106 | /* Ensure the pwm_needed bit mask can accommodate all available channels. */ |
82 | 107 | #if (NRF_PWM_CHANNEL_COUNT > 8) |
83 | 108 | #error "Current implementation supports maximum 8 channels." |
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