soc: nordic: nrf54h: Add TDD enable option

Allow starting the trace and debug domain in the soc_late_init() hook.

Signed-off-by: Karsten Koenig <[email protected]>

Author: karstenkoenig

soc/nordic/nrf54h/Kconfig

@@ -8,7 +8,6 @@ config SOC_SERIES_NRF54HX
 	select HAS_NRFX
 	select HAS_NORDIC_DRIVERS
 	select SOC_EARLY_INIT_HOOK if ARM
-	select SOC_LATE_INIT_HOOK if SOC_NRF54H20_CPURAD_ENABLE
 	select NRF_PLATFORM_HALTIUM
 
 config SOC_NRF54H20_CPUAPP_COMMON
@@ -72,11 +71,23 @@ config SOC_NRF54H20_CPURAD_ENABLE
 	default y if NRF_802154_SER_HOST
 	depends on SOC_NRF54H20_CPUAPP
 	select NRF_IRONSIDE_CPUCONF_SERVICE
+	select SOC_LATE_INIT_HOOK
 	help
 	  This will at application boot time enable clock to the
 	  Radiocore, and also power will be requested to the Radiocore
 	  subsystem. The Radiocore will then start executing instructions.
 
+config SOC_NRF54H20_ENABLE_TDD_WITH_PINS
+	bool "Enable the trace and debug domain (TDD) with pins"
+	depends on SOC_NRF54H20_CPUAPP
+	select NRF_IRONSIDE_TDD_SERVICE
+	select SOC_LATE_INIT_HOOK
+	help
+	  This will at application boot time request that the trace and
+	  debug domain (TDD) is powered up and that the TPIU pins are
+	  configured. This allows configuring the coresight peripherals from
+	  the application domain.
+
 config SOC_NRF54H20_CPURAD
 	select SOC_NRF54H20_CPURAD_COMMON
 

soc/nordic/nrf54h/soc.c

@@ -23,6 +23,7 @@
 #include <soc_lrcconf.h>
 #include <dmm.h>
 #include <zephyr/drivers/firmware/nrf_ironside/cpuconf.h>
+#include <zephyr/drivers/firmware/nrf_ironside/tdd.h>
 
 LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
 
@@ -159,10 +160,19 @@ void soc_early_init_hook(void)
 	}
 }
 
-#if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE)
+#if defined(CONFIG_SOC_LATE_INIT_HOOK)
+
 void soc_late_init_hook(void)
 {
-	int err;
+#if defined(CONFIG_SOC_NRF54H20_ENABLE_TDD_WITH_PINS)
+	int err_tdd;
+
+	err_tdd = ironside_tdd(IRONSIDE_TDD_CONFIG_ON_DEFAULT);
+	__ASSERT(err_tdd == 0, "err_tdd was %d", err_tdd);
+#endif
+
+#if defined(CONFIG_SOC_NRF54H20_CPURAD_ENABLE)
+	int err_cpuconf;
 
 	/* The msg will be used for communication prior to IPC
 	 * communication being set up. But at this moment no such
@@ -178,8 +188,9 @@ void soc_late_init_hook(void)
 	/* Don't wait as this is not yet supported. */
 	bool cpu_wait = false;
 
-	err = ironside_cpuconf(NRF_PROCESSOR_RADIOCORE, radiocore_address, cpu_wait, msg, msg_size);
-	__ASSERT(err == 0, "err was %d", err);
+	err_cpuconf = ironside_cpuconf(NRF_PROCESSOR_RADIOCORE, radiocore_address, cpu_wait, msg, msg_size);
+	__ASSERT(err_cpuconf == 0, "err_cpuconf was %d", err_cpuconf);
+#endif
 }
 #endif