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[nrf fromtree] soc: renode: Add cortex_r8_virtual
Add virtual Cortex R8 SoC. This target does not represent a real SoC, but can be easily run in Renode. This will allow to easily test basic architecture support. Signed-off-by: Krzysztof Sychla <[email protected]> Signed-off-by: Marek Slowinski <[email protected]> Signed-off-by: Piotr Zierhoffer <[email protected]> Signed-off-by: Mateusz Hołenko <[email protected]> (cherry picked from commit dc433dd)
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‎dts/arm/cortex_r8_virt.dtsi‎

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/*
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* Copyright (c) 2024 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-r8f";
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reg = <0>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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interrupt-parent = < &gic >;
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flash0: flash@c0000000 {
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compatible = "soc-nv-flash";
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reg = < 0xc0000000 0x2000000 >;
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};
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sram0: memory@0 {
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compatible = "mmio-sram";
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reg = < 0x0 0x4000000 >;
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};
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uart0: uart@ff000000 {
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compatible = "xlnx,xuartps";
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reg = < 0xff000000 0x4c >;
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status = "disabled";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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};
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ttc0: timer@ff110000 {
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compatible = "xlnx,ttcps";
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status = "okay";
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interrupts = < 0x0 0x24 0x2 0xa0 >,
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< 0x0 0x25 0x2 0xa0 >,
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< 0x0 0x26 0x2 0xa0 >;
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interrupt-names = "irq_0", "irq_1", "irq_2";
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reg = < 0xff110000 0x1000 >;
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clock-frequency = < 5000000 >;
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};
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gic: interrupt-controller@f9000000 {
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compatible = "arm,gic-v1", "arm,gic";
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reg = < 0xf9000000 0x1000 >, < 0xf9001000 0x100 >;
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interrupt-controller;
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#interrupt-cells = < 0x4 >;
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status = "okay";
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phandle = < 0x1 >;
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};
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};
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};

‎soc/renode/cortex_r8_virtual/CMakeLists.txt‎

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# Copyright (c) 2024 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources(soc.c)
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zephyr_sources_ifdef(
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CONFIG_ARM_MPU
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arm_mpu_regions.c
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)
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zephyr_include_directories(.)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_a_r/scripts/linker.ld CACHE INTERNAL "")

‎soc/renode/cortex_r8_virtual/Kconfig‎

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# Copyright (c) 2024 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_CORTEX_R8_VIRTUAL
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select ARM
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select CPU_CORTEX_R8
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select PLATFORM_SPECIFIC_INIT
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select CPU_HAS_ARM_MPU
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select VFP_DP_D16

‎soc/renode/cortex_r8_virtual/Kconfig.defconfig‎

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# Copyright (c) 2024 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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if SOC_CORTEX_R8_VIRTUAL
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config NUM_IRQS
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default 220
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 5000000
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DT_CHOSEN_Z_FLASH := zephyr,flash
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config FLASH_SIZE
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
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config FLASH_BASE_ADDRESS
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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endif # SOC_CORTEX_R8_VIRTUAL

‎soc/renode/cortex_r8_virtual/Kconfig.soc‎

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# Copyright (c) 2024 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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config SOC_CORTEX_R8_VIRTUAL
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bool
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help
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Cortex R8 Virtual system implementation
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config SOC
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default "cortex_r8_virtual" if SOC_CORTEX_R8_VIRTUAL

‎soc/renode/cortex_r8_virtual/arm_mpu_regions.c‎

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/* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2021 Lexmark International, Inc.
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* Copyright (c) 2024 Antmicro <www.antmicro.com>
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/arm/mpu/arm_mpu.h>
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#define MPUTYPE_READ_ONLY \
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{ \
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.rasr = (P_RO_U_RO_Msk \
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| (7 << MPU_RASR_TEX_Pos) \
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| MPU_RASR_C_Msk \
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| MPU_RASR_B_Msk \
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| MPU_RASR_XN_Msk) \
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}
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#define MPUTYPE_READ_ONLY_PRIV \
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{ \
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.rasr = (P_RO_U_RO_Msk \
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| (5 << MPU_RASR_TEX_Pos) \
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| MPU_RASR_B_Msk) \
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}
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#define MPUTYPE_PRIV_WBWACACHE_XN \
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{ \
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.rasr = (P_RW_U_NA_Msk \
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| (5 << MPU_RASR_TEX_Pos) \
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| MPU_RASR_B_Msk \
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| MPU_RASR_XN_Msk) \
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}
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#define MPUTYPE_PRIV_DEVICE \
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{ \
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.rasr = (P_RW_U_NA_Msk \
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| (2 << MPU_RASR_TEX_Pos)) \
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}
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extern uint32_t _image_rom_end_order;
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static const struct arm_mpu_region mpu_regions[] = {
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MPU_REGION_ENTRY("FLASH0",
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0xc0000000,
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REGION_32M,
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MPUTYPE_READ_ONLY),
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MPU_REGION_ENTRY("SRAM_PRIV",
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0x00000000,
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REGION_2G,
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MPUTYPE_PRIV_WBWACACHE_XN),
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MPU_REGION_ENTRY("SRAM",
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0x00000000,
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((uint32_t)&_image_rom_end_order),
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MPUTYPE_READ_ONLY_PRIV),
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MPU_REGION_ENTRY("REGISTERS",
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0xf8000000,
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REGION_128M,
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MPUTYPE_PRIV_DEVICE),
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};

‎soc/renode/cortex_r8_virtual/soc.c‎

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/*
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* Copyright (c) 2019 Lexmark International, Inc.
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* Copyright (c) 2024 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <cmsis_core.h>
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void z_arm_platform_init(void)
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{
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/*
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* Use normal exception vectors address range (0x0-0x1C).
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*/
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unsigned int sctlr = __get_SCTLR();
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sctlr &= ~SCTLR_V_Msk;
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__set_SCTLR(sctlr);
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}

‎soc/renode/cortex_r8_virtual/soc.h‎

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/*
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* Copyright (c) 2024 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#ifndef ZEPHYR_SOC_CORTEX_R8_VIRTUAL_SOC_H_
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#define ZEPHYR_SOC_CORTEX_R8_VIRTUAL_SOC_H_
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#define __CR_REV 1U
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#define __GIC_PRESENT 0U
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#define __TIM_PRESENT 0U
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#endif /* ZEPHYR_SOC_CORTEX_R8_VIRTUAL_SOC_H_ */

‎soc/renode/cortex_r8_virtual/soc.yml‎

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socs:
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- name: cortex_r8_virtual

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