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[nrf fromtree] tests: add twister tests for CMake board and SoC extension
This commit adds new tests for verifying the functionality of the board and SoC extension feature. It does so by defining: - A new CPU cluster on an existing SoC - Two new board variants on top of an existing board The new board variants are defined on top of the existing `native_sim` board, so that the following native_sim board targets are available for the test. Existing board targets: - native_sim/native - native_sim/native/64 Extended board targets: - native_sim/native/one - native_sim/native/64/two The new CPU cluster is defined for the existing `an521` SoC. Existing CPU Clusters on an521: - cpu0 - cpu1 New CPU Cluster: - cputest For SoC tests the mps2 board is used. This means that for testing, the following board targets using the an521 SoC are: - mps2/an521/cpu0 - mps2/an521/cpu1 - mps2/an521/cputest Signed-off-by: Torsten Rasmussen <[email protected]> (cherry picked from commit f315157)
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‎tests/cmake/hwm/board_extend/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2024 Nordic Semiconductor ASA
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cmake_minimum_required(VERSION 3.20.0)
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set(BOARD_ROOT ${CMAKE_CURRENT_LIST_DIR}/oot_root)
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set(SOC_ROOT ${CMAKE_CURRENT_LIST_DIR}/oot_root)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(native_sim_extend)
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FILE(GLOB app_sources src/*.c)
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target_sources(app PRIVATE ${app_sources})

‎tests/cmake/hwm/board_extend/Kconfig‎

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# Copyright (c) 2024 Nordic Semiconductor ASA
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#
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# SPDX-License-Identifier: Apache-2.0
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config BASE_BOARD_SETTING
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bool "Base board test string"
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help
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This kconfig is set when the base board config fragment is supposed to
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be sourced, that is when oot variant defines
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'extends:'
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' board: native_sim'
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' qualifier: posix'
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' inherit: 1'
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source "Kconfig.zephyr"

‎tests/cmake/hwm/board_extend/boards/native_sim.conf‎

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CONFIG_BASE_BOARD_SETTING=y

‎tests/cmake/hwm/board_extend/boards/native_sim_native_64_two.conf‎

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CONFIG_EXTENDED_VARIANT_BOARD_SETTING=y

‎tests/cmake/hwm/board_extend/boards/native_sim_native_one.conf‎

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CONFIG_EXTENDED_VARIANT_BOARD_SETTING=y

‎tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/Kconfig.mps2‎

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# Copyright (c) 2017 Linaro Limited
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_MPS2
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select SOC_MPS2_AN521_CPUTEST if BOARD_MPS2_AN521_CPUTEST

‎tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/board.cmake‎

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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2024, Nordic Semiconductor ASA
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if(CONFIG_BOARD_MPS2_AN521_CPUTEST)
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set(QEMU_CPU_TYPE_${ARCH} cortex-m33)
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set(QEMU_FLAGS_${ARCH}
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-cpu ${QEMU_CPU_TYPE_${ARCH}}
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-machine mps2-an521
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-nographic
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-m 16
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-vga none
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)
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endif()

‎tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/board.yml‎

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board:
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extend: mps2

‎tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521-common.dtsi‎

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/*
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* Copyright (c) 2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <25000000>;
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#clock-cells = <0>;
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};
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timer0: timer@0 {
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compatible = "arm,cmsdk-timer";
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reg = <0x0 0x1000>;
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interrupts = <3 3>;
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};
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timer1: timer@1000 {
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compatible = "arm,cmsdk-timer";
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reg = <0x1000 0x1000>;
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interrupts = <4 3>;
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};
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dtimer0: dtimer@2000 {
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compatible = "arm,cmsdk-dtimer";
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reg = <0x2000 0x1000>;
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interrupts = <5 3>;
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};
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mhu0: mhu@3000 {
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compatible = "arm,mhu";
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reg = <0x3000 0x1000>;
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interrupts = <6 3>;
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};
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mhu1: mhu@4000 {
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compatible = "arm,mhu";
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reg = <0x4000 0x1000>;
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interrupts = <7 3>;
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};
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gpio0: gpio@100000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x100000 0x1000>;
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interrupts = <68 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio1: gpio@101000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x101000 0x1000>;
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interrupts = <69 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio2: gpio@102000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x102000 0x1000>;
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interrupts = <70 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio3: gpio@103000 {
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compatible = "arm,cmsdk-gpio";
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reg = <0x103000 0x1000>;
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interrupts = <71 3>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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wdog0: wdog@81000 {
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compatible = "arm,cmsdk-watchdog";
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reg = <0x81000 0x1000>;
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clocks = <&sysclk>;
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};
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uart0: uart@200000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x200000 0x1000>;
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interrupts = <33 3 32 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart1: uart@201000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x201000 0x1000>;
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interrupts = <35 3 34 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart2: uart@202000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x202000 0x1000>;
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interrupts = <37 3 36 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart3: uart@203000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x203000 0x1000>;
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interrupts = <39 3 38 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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uart4: uart@204000 {
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compatible = "arm,cmsdk-uart";
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reg = <0x204000 0x1000>;
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interrupts = <41 3 40 3>;
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interrupt-names = "tx", "rx";
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clocks = <&sysclk>;
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current-speed = <115200>;
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};
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i2c_touch: i2c@207000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x207000 0x1000>;
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};
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i2c_audio_conf: i2c@208000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x208000 0x1000>;
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};
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i2c_shield0: i2c@20c000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x20c000 0x1000>;
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};
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i2c_shield1: i2c@20d000 {
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compatible = "arm,versatile-i2c";
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clock-frequency = <I2C_BITRATE_STANDARD>;
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x20d000 0x1000>;
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};
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gpio_led0: mps2_fpgaio@302000 {
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compatible = "arm,mps2-fpgaio-gpio";
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reg = <0x302000 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <2>;
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};
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gpio_button: mps2_fpgaio@302008 {
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compatible = "arm,mps2-fpgaio-gpio";
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reg = <0x302008 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <2>;
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};
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gpio_misc: mps2_fpgaio@30204c {
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compatible = "arm,mps2-fpgaio-gpio";
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reg = <0x30204c 0x4>;
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gpio-controller;
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#gpio-cells = <1>;
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ngpios = <10>;
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};
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eth0: eth@2000000 {
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/* Linux has "smsc,lan9115" */
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compatible = "smsc,lan9220";
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/* Actual reg range is ~0x200 */
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reg = <0x2000000 0x100000>;
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interrupts = <48 3>;
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};

‎tests/cmake/hwm/board_extend/oot_root/boards/arm/mps2/mps2_an521_cputest.dts‎

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/*
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* Copyright (c) 2018-2019 Linaro Limited
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#include <arm/armv8-m.dtsi>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/input/input-event-codes.h>
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/ {
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compatible = "arm,mps2";
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#address-cells = <1>;
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#size-cells = <1>;
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aliases {
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led0 = &led_0;
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led1 = &led_1;
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sw0 = &user_button_0;
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sw1 = &user_button_1;
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uart-1 = &uart1;
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watchdog0 = &wdog0;
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};
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chosen {
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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/*
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* These SRAM and flash settings give the entire available
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* code and data memories to this secure firmware image.
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* This may conflict with mps2_an521_remote firmware. Use
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* caution when using both targets simultaneously.
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*/
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zephyr,sram = &ssram2_3;
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zephyr,flash = &ssram1;
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};
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leds {
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compatible = "gpio-leds";
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led_0: led_0 {
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gpios = <&gpio_led0 0>;
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label = "USERLED0";
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};
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led_1: led_1 {
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gpios = <&gpio_led0 1>;
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label = "USERLED1";
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};
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};
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gpio_keys {
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compatible = "gpio-keys";
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user_button_0: button_0 {
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label = "USERPB0";
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gpios = <&gpio_button 0>;
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zephyr,code = <INPUT_KEY_0>;
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};
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user_button_1: button_1 {
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label = "USERPB1";
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gpios = <&gpio_button 1>;
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zephyr,code = <INPUT_KEY_1>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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/*
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* The memory regions defined below are according to AN521:
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* https://documentation-service.arm.com/static/5fa12fe9b1a7c5445f29017f
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*
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* Please see tables mentioned in individual comments below for details.
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*/
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ssram1: memory@10000000 {
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/* Table 3-2, row 6. */
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x10000000 DT_SIZE_M(4)>;
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zephyr,memory-region = "SSRAM1";
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};
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ssram2_3: memory@38000000 {
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/* Table 3-4, rows 16 and 17. */
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compatible = "zephyr,memory-region", "mmio-sram";
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reg = <0x38000000 DT_SIZE_M(4)>;
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zephyr,memory-region = "SSRAM2_3";
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};
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psram: memory@80000000 {
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/* Table 3-6, row 1. */
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device_type = "memory";
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reg = <0x80000000 DT_SIZE_M(16)>;
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};
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soc {
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peripheral@50000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x50000000 0x10000000>;
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#include "mps2_an521-common.dtsi"
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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&uart1 {
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status = "okay";
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};

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