[nrf fromlist] soc: nordic_nrf: Add address validation entries for nRF54H/L dts nodes

Add entries for checking if the recently added dts nodes for nRF54H20
and nRF54L15 have correct base addresses (if they match those provided
by MDK).

Signed-off-by: Andrzej Głąbek <[email protected]>
(cherry picked from commit f3e6d39b90bbcf763fca76e0752a703f49a9c58e)

Upstream PR: zephyrproject-rtos/zephyr#69811

Author: anangl

soc/arm/nordic_nrf/validate_base_addresses.c

@@ -133,17 +133,39 @@ CHECK_DT_REG(cryptocell, NRF_CRYPTOCELL);
 CHECK_DT_REG(ctrlap, NRF_CTRLAP);
 CHECK_DT_REG(dcnf, NRF_DCNF);
 CHECK_DT_REG(dppic, NRF_DPPIC);
+CHECK_DT_REG(dppic00, NRF_DPPIC00);
+CHECK_DT_REG(dppic10, NRF_DPPIC10);
+CHECK_DT_REG(dppic20, NRF_DPPIC20);
+CHECK_DT_REG(dppic30, NRF_DPPIC30);
+CHECK_DT_REG(dppic020, NRF_DPPIC020);
+CHECK_DT_REG(dppic120, NRF_DPPIC120);
+CHECK_DT_REG(dppic130, NRF_DPPIC130);
+CHECK_DT_REG(dppic131, NRF_DPPIC131);
+CHECK_DT_REG(dppic132, NRF_DPPIC132);
+CHECK_DT_REG(dppic133, NRF_DPPIC133);
+CHECK_DT_REG(dppic134, NRF_DPPIC134);
+CHECK_DT_REG(dppic135, NRF_DPPIC135);
+CHECK_DT_REG(dppic136, NRF_DPPIC136);
 CHECK_DT_REG(ecb, NRF_ECB);
+CHECK_DT_REG(ecb020, NRF_ECB020);
+CHECK_DT_REG(ecb030, NRF_ECB030);
 CHECK_DT_REG(egu0, NRF_EGU0);
 CHECK_DT_REG(egu1, NRF_EGU1);
 CHECK_DT_REG(egu2, NRF_EGU2);
 CHECK_DT_REG(egu3, NRF_EGU3);
 CHECK_DT_REG(egu4, NRF_EGU4);
 CHECK_DT_REG(egu5, NRF_EGU5);
+CHECK_DT_REG(egu10, NRF_EGU10);
+CHECK_DT_REG(egu20, NRF_EGU20);
+CHECK_DT_REG(egu020, NRF_EGU020);
 CHECK_DT_REG(ficr, NRF_FICR);
 CHECK_DT_REG(flash_controller, NRF_NVMC);
 CHECK_DT_REG(gpio0, NRF_P0);
 CHECK_DT_REG(gpio1, NRF_P1);
+CHECK_DT_REG(gpio2, NRF_P2);
+CHECK_DT_REG(gpio6, NRF_P6);
+CHECK_DT_REG(gpio7, NRF_P7);
+CHECK_DT_REG(gpio9, NRF_P9);
 CHECK_DT_REG(gpiote, NRF_GPIOTE);
 CHECK_DT_REG(gpiote0, NRF_GPIOTE0);
 CHECK_DT_REG(gpiote1, NRF_GPIOTE1);
@@ -155,8 +177,25 @@ CHECK_I2C_REG(i2c0, 0);
 CHECK_I2C_REG(i2c1, 1);
 CHECK_DT_REG(i2c2, NRF_TWIM2);
 CHECK_DT_REG(i2c3, NRF_TWIM3);
+CHECK_DT_REG(i2c20, NRF_TWIM20);
+CHECK_DT_REG(i2c21, NRF_TWIM21);
+CHECK_DT_REG(i2c22, NRF_TWIM22);
+CHECK_DT_REG(i2c30, NRF_TWIM30);
+CHECK_DT_REG(i2c130, NRF_TWIM130);
+CHECK_DT_REG(i2c131, NRF_TWIM131);
+CHECK_DT_REG(i2c132, NRF_TWIM132);
+CHECK_DT_REG(i2c133, NRF_TWIM133);
+CHECK_DT_REG(i2c134, NRF_TWIM134);
+CHECK_DT_REG(i2c135, NRF_TWIM135);
+CHECK_DT_REG(i2c136, NRF_TWIM136);
+CHECK_DT_REG(i2c137, NRF_TWIM137);
 CHECK_DT_REG(i2s0, NRF_I2S0);
+CHECK_DT_REG(i2s20, NRF_I2S20);
 CHECK_DT_REG(ipc, NRF_IPC);
+CHECK_DT_REG(cpuapp_ipct, NRF_IPCT);
+CHECK_DT_REG(cpurad_ipct, NRF_IPCT);
+CHECK_DT_REG(ipct120, NRF_IPCT120);
+CHECK_DT_REG(ipct130, NRF_IPCT130);
 CHECK_DT_REG(kmu, NRF_KMU);
 CHECK_DT_REG(mutex, NRF_MUTEX);
 CHECK_DT_REG(mwu, NRF_MWU);
@@ -173,18 +212,40 @@ CHECK_DT_REG(pwm3, NRF_PWM3);
 CHECK_DT_REG(qdec, NRF_QDEC0);	/* this should be the same node as qdec0 */
 CHECK_DT_REG(qdec0, NRF_QDEC0);
 CHECK_DT_REG(qdec1, NRF_QDEC1);
+CHECK_DT_REG(qdec20, NRF_QDEC20);
+CHECK_DT_REG(qdec21, NRF_QDEC21);
+CHECK_DT_REG(qdec130, NRF_QDEC130);
+CHECK_DT_REG(qdec131, NRF_QDEC131);
 CHECK_DT_REG(radio, NRF_RADIO);
 CHECK_DT_REG(regulators, NRF_REGULATORS);
 CHECK_DT_REG(reset, NRF_RESET);
 CHECK_DT_REG(rng, NRF_RNG);
+CHECK_DT_REG(rtc, NRF_RTC);
 CHECK_DT_REG(rtc0, NRF_RTC0);
 CHECK_DT_REG(rtc1, NRF_RTC1);
 CHECK_DT_REG(rtc2, NRF_RTC2);
+CHECK_DT_REG(rtc130, NRF_RTC130);
+CHECK_DT_REG(rtc131, NRF_RTC131);
 CHECK_SPI_REG(spi0, 0);
 CHECK_SPI_REG(spi1, 1);
 CHECK_SPI_REG(spi2, 2);
 CHECK_DT_REG(spi3, NRF_SPIM3);
 CHECK_DT_REG(spi4, NRF_SPIM4);
+CHECK_DT_REG(spi00, NRF_SPIM00);
+CHECK_DT_REG(spi20, NRF_SPIM20);
+CHECK_DT_REG(spi21, NRF_SPIM21);
+CHECK_DT_REG(spi22, NRF_SPIM22);
+CHECK_DT_REG(spi30, NRF_SPIM30);
+CHECK_DT_REG(spi120, NRF_SPIM120);
+CHECK_DT_REG(spi121, NRF_SPIM121);
+CHECK_DT_REG(spi130, NRF_SPIM130);
+CHECK_DT_REG(spi131, NRF_SPIM131);
+CHECK_DT_REG(spi132, NRF_SPIM132);
+CHECK_DT_REG(spi133, NRF_SPIM133);
+CHECK_DT_REG(spi134, NRF_SPIM134);
+CHECK_DT_REG(spi135, NRF_SPIM135);
+CHECK_DT_REG(spi136, NRF_SPIM136);
+CHECK_DT_REG(spi137, NRF_SPIM137);
 CHECK_DT_REG(spu, NRF_SPU);
 CHECK_DT_REG(swi0, NRF_SWI0);
 CHECK_DT_REG(swi1, NRF_SWI1);
@@ -205,6 +266,19 @@ CHECK_DT_REG(timer21, NRF_TIMER21);
 CHECK_DT_REG(timer22, NRF_TIMER22);
 CHECK_DT_REG(timer23, NRF_TIMER23);
 CHECK_DT_REG(timer24, NRF_TIMER24);
+CHECK_DT_REG(timer020, NRF_TIMER020);
+CHECK_DT_REG(timer021, NRF_TIMER021);
+CHECK_DT_REG(timer022, NRF_TIMER022);
+CHECK_DT_REG(timer120, NRF_TIMER120);
+CHECK_DT_REG(timer121, NRF_TIMER121);
+CHECK_DT_REG(timer130, NRF_TIMER130);
+CHECK_DT_REG(timer131, NRF_TIMER131);
+CHECK_DT_REG(timer132, NRF_TIMER132);
+CHECK_DT_REG(timer133, NRF_TIMER133);
+CHECK_DT_REG(timer134, NRF_TIMER134);
+CHECK_DT_REG(timer135, NRF_TIMER135);
+CHECK_DT_REG(timer136, NRF_TIMER136);
+CHECK_DT_REG(timer137, NRF_TIMER137);
 CHECK_UART_REG(uart0, 0);
 CHECK_DT_REG(uart1, NRF_UARTE1);
 CHECK_DT_REG(uart2, NRF_UARTE2);
@@ -232,6 +306,8 @@ CHECK_DT_REG(wdt0, NRF_WDT0);
 CHECK_DT_REG(wdt1, NRF_WDT1);
 CHECK_DT_REG(wdt30, NRF_WDT30);
 CHECK_DT_REG(wdt31, NRF_WDT31);
+CHECK_DT_REG(wdt131, NRF_WDT131);
+CHECK_DT_REG(wdt132, NRF_WDT132);
 
 /* nRF51/nRF52-specific addresses */
 #if defined(CONFIG_SOC_SERIES_NRF51X) || defined(CONFIG_SOC_SERIES_NRF52X)