88#include <zephyr/drivers/spi/rtio.h>
99#include <zephyr/cache.h>
1010#include <zephyr/pm/device.h>
11- #include <zephyr/pm/device_runtime.h>
1211#include <zephyr/drivers/pinctrl.h>
1312#include <zephyr/mem_mgmt/mem_attr.h>
1413#include <soc.h>
@@ -141,56 +140,15 @@ static inline nrf_spim_bit_order_t get_nrf_spim_bit_order(uint16_t operation)
141140 }
142141}
143142
144- static int spim_init (const struct device * dev )
145- {
146- struct spi_nrfx_data * dev_data = dev -> data ;
147- const struct spi_nrfx_config * dev_config = dev -> config ;
148- nrfx_spim_config_t config ;
149- struct spi_context * ctx = & dev_data -> ctx ;
150- const struct spi_config * spi_cfg = ctx -> config ;
151- uint32_t max_freq = dev_config -> max_freq ;
152- nrfx_err_t result = NRFX_SUCCESS ;
153-
154- #if defined(CONFIG_SOC_NRF5340_CPUAPP )
155- /* On nRF5340, the 32 Mbps speed is supported by the application core
156- * when it is running at 128 MHz (see the Timing specifications section
157- * in the nRF5340 PS).
158- */
159- if (max_freq > 16000000 &&
160- nrf_clock_hfclk_div_get (NRF_CLOCK ) != NRF_CLOCK_HFCLK_DIV_1 ) {
161- max_freq = 16000000 ;
162- }
163- #endif
164-
165- config = dev_config -> def_config ;
166-
167- /* Limit the frequency to that supported by the SPIM instance. */
168- config .frequency = get_nrf_spim_frequency (MIN (spi_cfg -> frequency ,
169- max_freq ));
170- config .mode = get_nrf_spim_mode (spi_cfg -> operation );
171- config .bit_order = get_nrf_spim_bit_order (spi_cfg -> operation );
172-
173- if (dev_data -> initialized ) {
174- nrfx_spim_uninit (& dev_config -> spim );
175- dev_data -> initialized = false;
176- }
177-
178- result = nrfx_spim_init (& dev_config -> spim , & config ,
179- event_handler , (void * )dev );
180- if (result != NRFX_SUCCESS ) {
181- LOG_ERR ("Failed to initialize nrfx driver: %08x" , result );
182- return - EIO ;
183- }
184- return 0 ;
185- }
186-
187143static int configure (const struct device * dev ,
188144 const struct spi_config * spi_cfg )
189145{
190146 struct spi_nrfx_data * dev_data = dev -> data ;
191147 const struct spi_nrfx_config * dev_config = dev -> config ;
192148 struct spi_context * ctx = & dev_data -> ctx ;
193- int ret ;
149+ uint32_t max_freq = dev_config -> max_freq ;
150+ nrfx_spim_config_t config ;
151+ nrfx_err_t result ;
194152
195153 if (dev_data -> initialized && spi_context_configured (ctx , spi_cfg )) {
196154 /* Already configured. No need to do it again. */
@@ -228,22 +186,44 @@ static int configure(const struct device *dev,
228186 return - EINVAL ;
229187 }
230188
189+ #if defined(CONFIG_SOC_NRF5340_CPUAPP )
190+ /* On nRF5340, the 32 Mbps speed is supported by the application core
191+ * when it is running at 128 MHz (see the Timing specifications section
192+ * in the nRF5340 PS).
193+ */
194+ if (max_freq > 16000000 &&
195+ nrf_clock_hfclk_div_get (NRF_CLOCK ) != NRF_CLOCK_HFCLK_DIV_1 ) {
196+ max_freq = 16000000 ;
197+ }
198+ #endif
199+
200+ config = dev_config -> def_config ;
201+
202+ /* Limit the frequency to that supported by the SPIM instance. */
203+ config .frequency = get_nrf_spim_frequency (MIN (spi_cfg -> frequency ,
204+ max_freq ));
205+ config .mode = get_nrf_spim_mode (spi_cfg -> operation );
206+ config .bit_order = get_nrf_spim_bit_order (spi_cfg -> operation );
207+
231208 nrfy_gpio_pin_write (nrfy_spim_sck_pin_get (dev_config -> spim .p_reg ),
232209 spi_cfg -> operation & SPI_MODE_CPOL ? 1 : 0 );
233210
234- ctx -> config = spi_cfg ;
235- #ifdef CONFIG_PM_DEVICE_RUNTIME
236- ret = pm_device_runtime_get (dev );
237- #else
238- ret = spim_init (dev );
239- #endif
240- if (ret < 0 ) {
211+ if (dev_data -> initialized ) {
212+ nrfx_spim_uninit (& dev_config -> spim );
213+ dev_data -> initialized = false;
214+ }
241215
242- return ret ;
216+ result = nrfx_spim_init (& dev_config -> spim , & config ,
217+ event_handler , (void * )dev );
218+ if (result != NRFX_SUCCESS ) {
219+ LOG_ERR ("Failed to initialize nrfx driver: %08x" , result );
220+ return - EIO ;
243221 }
244222
245223 dev_data -> initialized = true;
246224
225+ ctx -> config = spi_cfg ;
226+
247227 return 0 ;
248228}
249229
@@ -341,7 +321,6 @@ static void finish_transaction(const struct device *dev, int error)
341321 dev_data -> busy = false;
342322
343323 finalize_spi_transaction (dev , true);
344- (void )pm_device_runtime_put (dev );
345324}
346325
347326static void transfer_next_chunk (const struct device * dev )
@@ -604,7 +583,9 @@ static int spim_nrfx_pm_action(const struct device *dev,
604583 if (ret < 0 ) {
605584 return ret ;
606585 }
607- ret = spim_init (dev );
586+ /* nrfx_spim_init() will be called at configuration before
587+ * the next transfer.
588+ */
608589 break ;
609590
610591 case PM_DEVICE_ACTION_SUSPEND :
@@ -635,10 +616,7 @@ static int spi_nrfx_init(const struct device *dev)
635616 struct spi_nrfx_data * dev_data = dev -> data ;
636617 int err ;
637618
638- err = pinctrl_apply_state (dev_config -> pcfg ,
639- COND_CODE_1 (CONFIG_PM_DEVICE_RUNTIME ,
640- (PINCTRL_STATE_SLEEP ),
641- (PINCTRL_STATE_DEFAULT )));
619+ err = pinctrl_apply_state (dev_config -> pcfg , PINCTRL_STATE_DEFAULT );
642620 if (err < 0 ) {
643621 return err ;
644622 }
@@ -664,11 +642,6 @@ static int spi_nrfx_init(const struct device *dev)
664642
665643 spi_context_unlock_unconditionally (& dev_data -> ctx );
666644
667- #ifdef CONFIG_PM_DEVICE_RUNTIME
668- pm_device_init_suspended (dev );
669- pm_device_runtime_enable (dev );
670- #endif
671-
672645#ifdef CONFIG_SOC_NRF52832_ALLOW_SPIM_DESPITE_PAN_58
673646 return anomaly_58_workaround_init (dev );
674647#else
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