[nrf fromlist] drivers: pwm: pwm_nrf_sw: Align to use new GPPI API

Use new GPPI API.

Upstream PR #: 98327

Signed-off-by: Krzysztof Chruściński <[email protected]>

Author: nordic-krch

drivers/pwm/pwm_nrf_sw.c

@@ -72,8 +72,9 @@ struct pwm_config {
 struct pwm_data {
 	uint32_t period_cycles;
 	uint32_t pulse_cycles[PWM_0_MAP_SIZE];
-	uint8_t ppi_ch[PWM_0_MAP_SIZE][PPI_PER_CH];
+	nrfx_gppi_handle_t ppi_h[PWM_0_MAP_SIZE][PPI_PER_CH];
 	uint8_t gpiote_ch[PWM_0_MAP_SIZE];
+	uint32_t ppi_ch_mask[PWM_0_MAP_SIZE];
 };
 
 static inline NRF_RTC_Type *pwm_config_rtc(const struct pwm_config *config)
@@ -130,7 +131,8 @@ static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel,
 	uint8_t active_level;
 	uint8_t psel_ch;
 	uint8_t gpiote_ch;
-	const uint8_t *ppi_chs;
+	const nrfx_gppi_handle_t *ppi_chs;
+	uint32_t src_domain = nrfx_gppi_domain_id_get(USE_RTC ? (uint32_t)rtc : (uint32_t)timer);
 	int ret;
 
 	if (channel >= config->map_size) {
@@ -171,10 +173,8 @@ static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel,
 	LOG_DBG("channel %u, period %u, pulse %u",
 		channel, period_cycles, pulse_cycles);
 
-	/* clear PPI used */
-	ppi_mask = BIT(ppi_chs[0]) | BIT(ppi_chs[1]) |
-		   (PPI_PER_CH > 2 ? BIT(ppi_chs[2]) : 0);
-	nrfx_gppi_channels_disable(ppi_mask);
+	/* disable PPI used */
+	nrfx_gppi_channels_disable(src_domain, data->ppi_ch_mask[channel]);
 
 	active_level = (flags & PWM_POLARITY_INVERTED) ? 0 : 1;
 
@@ -278,12 +278,10 @@ static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel,
 				nrf_rtc_compare_event_get(0));
 
 #if PPI_FORK_AVAILABLE
-		nrfx_gppi_fork_endpoint_setup(ppi_chs[1],
-					      clear_task_address);
+        nrfx_gppi_ep_attach(ppi_chs[1], clear_task_address);
 #else
-		nrfx_gppi_channel_endpoints_setup(ppi_chs[2],
-						  period_end_event_address,
-						  clear_task_address);
+        nrfx_gppi_ep_attach(ppi_chs[2], period_end_event_address);
+        nrfx_gppi_ep_attach(ppi_chs[2], clear_task_address);
 #endif
 	} else {
 		pulse_end_event_address =
@@ -294,13 +292,13 @@ static int pwm_nrf_sw_set_cycles(const struct device *dev, uint32_t channel,
 				nrf_timer_compare_event_get(0));
 	}
 
-	nrfx_gppi_channel_endpoints_setup(ppi_chs[0],
-					  pulse_end_event_address,
-					  pulse_end_task_address);
-	nrfx_gppi_channel_endpoints_setup(ppi_chs[1],
-					  period_end_event_address,
-					  period_end_task_address);
-	nrfx_gppi_channels_enable(ppi_mask);
+	nrfx_gppi_ep_attach(ppi_chs[0], pulse_end_event_address);
+	nrfx_gppi_ep_attach(ppi_chs[0], pulse_end_task_address);
+
+	nrfx_gppi_ep_attach(ppi_chs[1], period_end_event_address);
+	nrfx_gppi_ep_attach(ppi_chs[1], period_end_task_address);
+
+	nrfx_gppi_channels_enable(src_domain, data->ppi_ch_mask[channel]);
 
 	/* start timer, hence PWM */
 	if (USE_RTC) {
@@ -352,18 +350,29 @@ static int pwm_nrf_sw_init(const struct device *dev)
 
 	for (uint32_t i = 0; i < config->map_size; i++) {
 		nrfx_err_t err;
+		uint32_t src_domain = nrfx_gppi_domain_id_get(USE_RTC ? (uint32_t)rtc : (uint32_t)timer);
+		uint32_t dst_domain = nrfx_gppi_domain_id_get((uint32_t)config->gpiote[i].p_reg);
+		int rv;
 
 		/* Allocate resources. */
 		for (uint32_t j = 0; j < PPI_PER_CH; j++) {
-			err = nrfx_gppi_channel_alloc(&data->ppi_ch[i][j]);
-			if (err != NRFX_SUCCESS) {
+			int ch;
+
+			rv = nrfx_gppi_domain_conn_alloc(src_domain, dst_domain, &data->ppi_h[i][j]);
+			if (rv < 0) {
 				/* Do not free allocated resource. It is a fatal condition,
 				 * system requires reconfiguration.
 				 */
 				LOG_ERR("Failed to allocate PPI channel");
-				return -ENOMEM;
+				return rv;
 			}
+			/* Enable connection but at the end disable channel on the source domain. */
+			nrfx_gppi_conn_enable(data->ppi_h[i][j]);
+			ch = nrfx_gppi_domain_channel_get(data->ppi_h[i][j], src_domain);
+			__ASSERT_NO_MSG(ch >= 0);
+			data->ppi_ch_mask[i] |= BIT(ch);
 		}
+		nrfx_gppi_channels_disable(src_domain, data->ppi_ch_mask[i]);
 
 		err = nrfx_gpiote_channel_alloc(&config->gpiote[i],
 						&data->gpiote_ch[i]);