[nrf fromlist] arch:riscv: Support for Direct ISRs for RISCV targets

Added support for Direct ISRs in the multithreaded enviroment

Signed-off-by: Rafal Dyla <[email protected]>

Author: Rafal-Nordic

arch/riscv/core/CMakeLists.txt

@@ -6,6 +6,7 @@ zephyr_library_sources(
   cpu_idle.c
   fatal.c
   irq_manage.c
+  isr.S
   prep_c.c
   reboot.c
   reset.S
@@ -26,7 +27,6 @@ endif()
 zephyr_library_sources_ifdef(CONFIG_FPU_SHARING fpu.c fpu.S)
 zephyr_library_sources_ifdef(CONFIG_DEBUG_COREDUMP coredump.c)
 zephyr_library_sources_ifdef(CONFIG_IRQ_OFFLOAD irq_offload.c)
-zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr.S)
 zephyr_library_sources_ifdef(CONFIG_RISCV_PMP pmp.c pmp.S)
 zephyr_library_sources_ifdef(CONFIG_THREAD_LOCAL_STORAGE tls.c)
 zephyr_library_sources_ifdef(CONFIG_USERSPACE userspace.S)

arch/riscv/core/irq_manage.c

@@ -10,6 +10,7 @@
 #include <zephyr/arch/riscv/csr.h>
 #include <zephyr/irq_multilevel.h>
 #include <zephyr/sw_isr_table.h>
+#include <zephyr/pm/pm.h>
 
 #ifdef CONFIG_RISCV_HAS_PLIC
 #include <zephyr/drivers/interrupt_controller/riscv_plic.h>
@@ -75,3 +76,20 @@ int arch_irq_disconnect_dynamic(unsigned int irq, unsigned int priority,
 }
 #endif /* CONFIG_SHARED_INTERRUPTS */
 #endif /* CONFIG_DYNAMIC_INTERRUPTS */
+
+#ifdef CONFIG_PM
+void _arch_isr_direct_pm(void)
+{
+	unsigned int key;
+
+	/* irq_lock() does what we want for this CPU */
+	key = irq_lock();
+
+	if (_kernel.idle) {
+		_kernel.idle = 0;
+		pm_system_resume();
+	}
+
+	irq_unlock(key);
+}
+#endif

arch/riscv/core/isr.S

@@ -646,6 +646,7 @@ on_irq_stack:
 	 */
 	jal ra, __soc_handle_irq
 
+#ifdef CONFIG_GEN_SW_ISR_TABLE
 	/*
 	 * Call corresponding registered function in _sw_isr_table.
 	 * (table is 2-word wide, we should shift index accordingly)
@@ -662,7 +663,7 @@ on_irq_stack:
 
 	/* Call ISR function */
 	jalr ra, t1, 0
-
+#endif
 #ifdef CONFIG_TRACING_ISR
 	call sys_trace_isr_exit
 #endif

drivers/timer/nrf_grtc_timer.c

@@ -449,12 +449,26 @@ uint32_t sys_clock_elapsed(void)
 	return (uint32_t)(counter_sub(counter(), last_count) / CYC_PER_TICK);
 }
 
+#if !defined(CONFIG_GEN_SW_ISR_TABLE)
+ISR_DIRECT_DECLARE(nrfx_grtc_direct_irq_handler)
+{
+	nrfx_grtc_irq_handler();
+	ISR_DIRECT_PM();
+	return 1;
+}
+#endif
+
 static int sys_clock_driver_init(void)
 {
 	nrfx_err_t err_code;
 
+#if defined(CONFIG_GEN_SW_ISR_TABLE)
 	IRQ_CONNECT(DT_IRQN(GRTC_NODE), DT_IRQ(GRTC_NODE, priority), nrfx_isr,
 		    nrfx_grtc_irq_handler, 0);
+#else
+	IRQ_DIRECT_CONNECT(DT_IRQN(GRTC_NODE), DT_IRQ(GRTC_NODE, priority), nrfx_grtc_direct_irq_handler, 0);
+	irq_enable(DT_IRQN(GRTC_NODE));
+#endif
 
 #if defined(CONFIG_NRF_GRTC_TIMER_CLOCK_MANAGEMENT) && NRF_GRTC_HAS_CLKSEL
 #if defined(CONFIG_CLOCK_CONTROL_NRF_K32SRC_RC)

include/zephyr/arch/riscv/irq.h

@@ -83,6 +83,13 @@ extern void z_riscv_irq_vector_set(unsigned int irq);
 	z_riscv_irq_vector_set(irq_p); \
 }
 
+#ifdef CONFIG_PM
+extern void _arch_isr_direct_pm(void);
+#define ARCH_ISR_DIRECT_PM() _arch_isr_direct_pm()
+#else
+#define ARCH_ISR_DIRECT_PM() do { } while (false)
+#endif
+
 #define ARCH_ISR_DIRECT_HEADER() arch_isr_direct_header()
 #define ARCH_ISR_DIRECT_FOOTER(swap) arch_isr_direct_footer(swap)
 

soc/common/riscv-privileged/vector.S

@@ -12,7 +12,7 @@ GTEXT(__start)
 
 /* imports */
 GTEXT(__initialize)
-#if defined(CONFIG_GEN_SW_ISR_TABLE)
+#if defined(CONFIG_GEN_SW_ISR_TABLE) || defined (CONFIG_GEN_IRQ_VECTOR_TABLE)
 GTEXT(_isr_wrapper)
 #endif
 
@@ -41,7 +41,7 @@ SECTION_FUNC(vectors, __start)
 	 * mtvec.base must be aligned to 64 bytes (this is done using
 	 * CONFIG_RISCV_TRAP_HANDLER_ALIGNMENT)
 	 */
-#if defined(CONFIG_GEN_SW_ISR_TABLE)
+#if defined(CONFIG_GEN_SW_ISR_TABLE) || defined (CONFIG_GEN_IRQ_VECTOR_TABLE)
 	la t0, _isr_wrapper
 #else
 	add t0, zero, zero