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jonathannilsenjonathannilsen
committed
adapt some test cases that were incorrectly handled by script
1 parent 8e93603 commit 95d8954

22 files changed

+652
-11
lines changed

‎tests/boards/nrf/i2c/i2c_slave/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf‎

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1+
CONFIG_NRFX_TWIS131=y

‎tests/drivers/i2c/i2c_target_api/boards/nrf54h20dk_nrf54h20_cpuapp_iron.conf‎

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# Copyright (c) 2025 Nordic Semiconductor ASA
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_I2C_NRFX_TWIS_BUF_SIZE=256

‎tests/drivers/spi/spi_controller_peripheral/CMakeLists.txt‎

Lines changed: 6 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -9,5 +9,10 @@ FILE(GLOB app_sources src/*.c)
99

1010
target_sources(app PRIVATE ${app_sources})
1111
if(CONFIG_SOC_NRF54H20_IRON)
12-
target_sources(app PRIVATE periphconf_migrated_src/periphconf_migrated_from_uicr.c)
12+
zephyr_get(PERIPHCONF_FILE)
13+
if(DEFINED PERIPHCONF_FILE)
14+
target_sources(app PRIVATE ${PERIPHCONF_FILE})
15+
else()
16+
target_sources(app PRIVATE periphconf_migrated_src/periphconf_migrated_from_uicr.c)
17+
endif()
1318
endif()

‎tests/drivers/spi/spi_controller_peripheral/periphconf_migrated_src/drivers.spi.pm_runtime.c‎

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/* Generated by nrf-regtool version 9.1.2.dev0+ga4a246e.d20250602 */
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#include <uicr/uicr.h>
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4+
/* SPU131 feature configuration for GRTC CC5 */
5+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 5, false, NRF_OWNER_NONE);
6+
/* SPU131 feature configuration for GRTC CC6 */
7+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 6, false, NRF_OWNER_NONE);
8+
/* gpio6 - P6.0 CTRLSEL = 4 */
9+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 0, 4);
10+
/* gpio6 - P6.2 CTRLSEL = 4 */
11+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 2, 4);
12+
/* gpio6 - P6.3 CTRLSEL = 4 */
13+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 3, 4);
14+
/* gpio6 - P6.4 CTRLSEL = 4 */
15+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 4, 4);
16+
/* gpio6 - P6.5 CTRLSEL = 4 */
17+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 5, 4);
18+
/* gpio6 - P6.6 CTRLSEL = 4 */
19+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 6, 4);
20+
/* gpio6 - P6.7 CTRLSEL = 4 */
21+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 7, 4);
22+
/* gpio6 - P6.8 CTRLSEL = 4 */
23+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 8, 4);
24+
/* gpio6 - P6.9 CTRLSEL = 4 */
25+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 9, 4);
26+
/* gpio6 - P6.10 CTRLSEL = 4 */
27+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 10, 4);
28+
/* gpio6 - P6.11 CTRLSEL = 4 */
29+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 11, 4);
30+
/* gpio9 - P9.2 CTRLSEL = 2 */
31+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 2, 2);
32+
/* gpio9 - P9.4 CTRLSEL = 6 */
33+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 4, 6);
34+
/* gpio9 - P9.5 CTRLSEL = 6 */
35+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 5, 6);

‎tests/drivers/spi/spi_controller_peripheral/periphconf_migrated_src/drivers.spi.spi_4MHz.c‎

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1+
/* Generated by nrf-regtool version 9.1.2.dev0+ga4a246e.d20250602 */
2+
#include <uicr/uicr.h>
3+
4+
/* SPU131 feature configuration for GRTC CC5 */
5+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 5, false, NRF_OWNER_NONE);
6+
/* SPU131 feature configuration for GRTC CC6 */
7+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 6, false, NRF_OWNER_NONE);
8+
/* gpio6 - P6.0 CTRLSEL = 4 */
9+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 0, 4);
10+
/* gpio6 - P6.2 CTRLSEL = 4 */
11+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 2, 4);
12+
/* gpio6 - P6.3 CTRLSEL = 4 */
13+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 3, 4);
14+
/* gpio6 - P6.4 CTRLSEL = 4 */
15+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 4, 4);
16+
/* gpio6 - P6.5 CTRLSEL = 4 */
17+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 5, 4);
18+
/* gpio6 - P6.6 CTRLSEL = 4 */
19+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 6, 4);
20+
/* gpio6 - P6.7 CTRLSEL = 4 */
21+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 7, 4);
22+
/* gpio6 - P6.8 CTRLSEL = 4 */
23+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 8, 4);
24+
/* gpio6 - P6.9 CTRLSEL = 4 */
25+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 9, 4);
26+
/* gpio6 - P6.10 CTRLSEL = 4 */
27+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 10, 4);
28+
/* gpio6 - P6.11 CTRLSEL = 4 */
29+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 11, 4);
30+
/* gpio9 - P9.2 CTRLSEL = 2 */
31+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 2, 2);
32+
/* gpio9 - P9.4 CTRLSEL = 6 */
33+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 4, 6);
34+
/* gpio9 - P9.5 CTRLSEL = 6 */
35+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 5, 6);

‎tests/drivers/spi/spi_controller_peripheral/periphconf_migrated_src/drivers.spi.spi_8MHz.c‎

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1+
/* Generated by nrf-regtool version 9.1.2.dev0+ga4a246e.d20250602 */
2+
#include <uicr/uicr.h>
3+
4+
/* SPU131 feature configuration for GRTC CC5 */
5+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 5, false, NRF_OWNER_NONE);
6+
/* SPU131 feature configuration for GRTC CC6 */
7+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 6, false, NRF_OWNER_NONE);
8+
/* gpio6 - P6.0 CTRLSEL = 4 */
9+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 0, 4);
10+
/* gpio6 - P6.2 CTRLSEL = 4 */
11+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 2, 4);
12+
/* gpio6 - P6.3 CTRLSEL = 4 */
13+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 3, 4);
14+
/* gpio6 - P6.4 CTRLSEL = 4 */
15+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 4, 4);
16+
/* gpio6 - P6.5 CTRLSEL = 4 */
17+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 5, 4);
18+
/* gpio6 - P6.6 CTRLSEL = 4 */
19+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 6, 4);
20+
/* gpio6 - P6.7 CTRLSEL = 4 */
21+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 7, 4);
22+
/* gpio6 - P6.8 CTRLSEL = 4 */
23+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 8, 4);
24+
/* gpio6 - P6.9 CTRLSEL = 4 */
25+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 9, 4);
26+
/* gpio6 - P6.10 CTRLSEL = 4 */
27+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 10, 4);
28+
/* gpio6 - P6.11 CTRLSEL = 4 */
29+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 11, 4);
30+
/* gpio9 - P9.2 CTRLSEL = 2 */
31+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 2, 2);
32+
/* gpio9 - P9.4 CTRLSEL = 6 */
33+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 4, 6);
34+
/* gpio9 - P9.5 CTRLSEL = 6 */
35+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 5, 6);

‎tests/drivers/spi/spi_controller_peripheral/periphconf_migrated_src/drivers.spi.spi_error_cases.c‎

Lines changed: 35 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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1+
/* Generated by nrf-regtool version 9.1.2.dev0+ga4a246e.d20250602 */
2+
#include <uicr/uicr.h>
3+
4+
/* SPU131 feature configuration for GRTC CC5 */
5+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 5, false, NRF_OWNER_NONE);
6+
/* SPU131 feature configuration for GRTC CC6 */
7+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 6, false, NRF_OWNER_NONE);
8+
/* gpio6 - P6.0 CTRLSEL = 4 */
9+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 0, 4);
10+
/* gpio6 - P6.2 CTRLSEL = 4 */
11+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 2, 4);
12+
/* gpio6 - P6.3 CTRLSEL = 4 */
13+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 3, 4);
14+
/* gpio6 - P6.4 CTRLSEL = 4 */
15+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 4, 4);
16+
/* gpio6 - P6.5 CTRLSEL = 4 */
17+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 5, 4);
18+
/* gpio6 - P6.6 CTRLSEL = 4 */
19+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 6, 4);
20+
/* gpio6 - P6.7 CTRLSEL = 4 */
21+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 7, 4);
22+
/* gpio6 - P6.8 CTRLSEL = 4 */
23+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 8, 4);
24+
/* gpio6 - P6.9 CTRLSEL = 4 */
25+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 9, 4);
26+
/* gpio6 - P6.10 CTRLSEL = 4 */
27+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 10, 4);
28+
/* gpio6 - P6.11 CTRLSEL = 4 */
29+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 11, 4);
30+
/* gpio9 - P9.2 CTRLSEL = 2 */
31+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 2, 2);
32+
/* gpio9 - P9.4 CTRLSEL = 6 */
33+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 4, 6);
34+
/* gpio9 - P9.5 CTRLSEL = 6 */
35+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 5, 6);

‎tests/drivers/spi/spi_controller_peripheral/periphconf_migrated_src/drivers.spi.spi_error_cases.fast.c‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,41 @@
1+
/* Generated by nrf-regtool version 9.1.2.dev0+ga4a246e.d20250602 */
2+
#include <uicr/uicr.h>
3+
4+
/* SPU131 feature configuration for GRTC CC5 */
5+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 5, false, NRF_OWNER_NONE);
6+
/* SPU131 feature configuration for GRTC CC6 */
7+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 6, false, NRF_OWNER_NONE);
8+
/* gpio6 - P6.0 CTRLSEL = 4 */
9+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 0, 4);
10+
/* gpio6 - P6.2 CTRLSEL = 4 */
11+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 2, 4);
12+
/* gpio6 - P6.3 CTRLSEL = 4 */
13+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 3, 4);
14+
/* gpio6 - P6.4 CTRLSEL = 4 */
15+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 4, 4);
16+
/* gpio6 - P6.5 CTRLSEL = 4 */
17+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 5, 4);
18+
/* gpio6 - P6.6 CTRLSEL = 4 */
19+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 6, 4);
20+
/* gpio6 - P6.7 CTRLSEL = 4 */
21+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 7, 4);
22+
/* gpio6 - P6.8 CTRLSEL = 4 */
23+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 8, 4);
24+
/* gpio6 - P6.9 CTRLSEL = 4 */
25+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 9, 4);
26+
/* gpio6 - P6.10 CTRLSEL = 4 */
27+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 10, 4);
28+
/* gpio6 - P6.11 CTRLSEL = 4 */
29+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 11, 4);
30+
/* gpio9 - P9.2 CTRLSEL = 2 */
31+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 2, 2);
32+
/* gpio9 - P9.4 CTRLSEL = 6 */
33+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 4, 6);
34+
/* gpio9 - P9.5 CTRLSEL = 6 */
35+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 5, 6);
36+
/* gpio7 - P7.0 CTRLSEL = 4 */
37+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938e00UL, 0, 4);
38+
/* gpio7 - P7.1 CTRLSEL = 4 */
39+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938e00UL, 1, 4);
40+
/* gpio7 - P7.2 CTRLSEL = 4 */
41+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938e00UL, 2, 4);

‎tests/drivers/spi/spi_controller_peripheral/periphconf_migrated_src/drivers.spi.spi_fast.c‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
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1+
/* Generated by nrf-regtool version 9.1.2.dev0+ga4a246e.d20250602 */
2+
#include <uicr/uicr.h>
3+
4+
/* SPU131 feature configuration for GRTC CC5 */
5+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 5, false, NRF_OWNER_NONE);
6+
/* SPU131 feature configuration for GRTC CC6 */
7+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 6, false, NRF_OWNER_NONE);
8+
/* gpio6 - P6.0 CTRLSEL = 4 */
9+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 0, 4);
10+
/* gpio6 - P6.2 CTRLSEL = 4 */
11+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 2, 4);
12+
/* gpio6 - P6.3 CTRLSEL = 4 */
13+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 3, 4);
14+
/* gpio6 - P6.4 CTRLSEL = 4 */
15+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 4, 4);
16+
/* gpio6 - P6.5 CTRLSEL = 4 */
17+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 5, 4);
18+
/* gpio6 - P6.6 CTRLSEL = 4 */
19+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 6, 4);
20+
/* gpio6 - P6.7 CTRLSEL = 4 */
21+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 7, 4);
22+
/* gpio6 - P6.8 CTRLSEL = 4 */
23+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 8, 4);
24+
/* gpio6 - P6.9 CTRLSEL = 4 */
25+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 9, 4);
26+
/* gpio6 - P6.10 CTRLSEL = 4 */
27+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 10, 4);
28+
/* gpio6 - P6.11 CTRLSEL = 4 */
29+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 11, 4);
30+
/* gpio9 - P9.2 CTRLSEL = 2 */
31+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 2, 2);
32+
/* gpio9 - P9.4 CTRLSEL = 6 */
33+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 4, 6);
34+
/* gpio9 - P9.5 CTRLSEL = 6 */
35+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 5, 6);
36+
/* gpio7 - P7.0 CTRLSEL = 4 */
37+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938e00UL, 0, 4);
38+
/* gpio7 - P7.1 CTRLSEL = 4 */
39+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938e00UL, 1, 4);
40+
/* gpio7 - P7.2 CTRLSEL = 4 */
41+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938e00UL, 2, 4);

‎tests/drivers/spi/spi_controller_peripheral/periphconf_migrated_src/drivers.spi.spi_mode0.c‎

Lines changed: 35 additions & 0 deletions
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1+
/* Generated by nrf-regtool version 9.1.2.dev0+ga4a246e.d20250602 */
2+
#include <uicr/uicr.h>
3+
4+
/* SPU131 feature configuration for GRTC CC5 */
5+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 5, false, NRF_OWNER_NONE);
6+
/* SPU131 feature configuration for GRTC CC6 */
7+
UICR_SPU_FEATURE_GRTC_CC_SET(0x5f990000UL, 6, false, NRF_OWNER_NONE);
8+
/* gpio6 - P6.0 CTRLSEL = 4 */
9+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 0, 4);
10+
/* gpio6 - P6.2 CTRLSEL = 4 */
11+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 2, 4);
12+
/* gpio6 - P6.3 CTRLSEL = 4 */
13+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 3, 4);
14+
/* gpio6 - P6.4 CTRLSEL = 4 */
15+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 4, 4);
16+
/* gpio6 - P6.5 CTRLSEL = 4 */
17+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 5, 4);
18+
/* gpio6 - P6.6 CTRLSEL = 4 */
19+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 6, 4);
20+
/* gpio6 - P6.7 CTRLSEL = 4 */
21+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 7, 4);
22+
/* gpio6 - P6.8 CTRLSEL = 4 */
23+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 8, 4);
24+
/* gpio6 - P6.9 CTRLSEL = 4 */
25+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 9, 4);
26+
/* gpio6 - P6.10 CTRLSEL = 4 */
27+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 10, 4);
28+
/* gpio6 - P6.11 CTRLSEL = 4 */
29+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f938c00UL, 11, 4);
30+
/* gpio9 - P9.2 CTRLSEL = 2 */
31+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 2, 2);
32+
/* gpio9 - P9.4 CTRLSEL = 6 */
33+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 4, 6);
34+
/* gpio9 - P9.5 CTRLSEL = 6 */
35+
UICR_GPIO_PIN_CNF_CTRLSEL_SET(0x5f939200UL, 5, 6);

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