[nrf fromtree] drivers: serial: nrfx_uarte: Perform flushing only when disabling

Previously, RX FIFO flushing was performed after each RXTO
(disabling of RX). However, it is necessary only when whole
UARTE is disabled. It is disabled when there is no RX or TX
active or when runtime device PM is enabled it is disabled
when there is no one requesting UARTE to be active. In case
of PM it is possible that UARTE will be kept powered up for
longer period of time and in that case flushing is not
performed. Because currently UARTE in all Nordic SoCs has
a bug in the RX FIFO we would like to avoid flushing if
possible since workaround is not covering 100% of cases.

Because UARTE is disabling is performed with interrupts
locked we try to limit number of operations there. RX FIFO
flushing is split into preparation (rx_flush_prepare())
which is performed in every RXTO event handling and actual
flush (rx_flush()) which is performed only when UARTE is
disabled.

Upstream PR: zephyrproject-rtos/zephyr#80201

Signed-off-by: Krzysztof Chruściński <[email protected]>

Author: nordic-krch

drivers/serial/uart_nrfx_uarte.c

@@ -160,6 +160,7 @@ struct uarte_async_rx {
 	/* Flag to ensure that RX timeout won't be executed during ENDRX ISR */
 	volatile bool is_in_irq;
 #endif /* CONFIG_UART_NRFX_UARTE_ENHANCED_RX */
+	uint16_t prev_amount;
 	uint8_t flush_cnt;
 	volatile bool enabled;
 	volatile bool discard_fifo;
@@ -658,6 +659,104 @@ static void tx_start(const struct device *dev, const uint8_t *buf, size_t len)
 }
 
 #if defined(UARTE_ANY_ASYNC)
+
+/* Function for preparing flushing internal RX fifo. Actual flushing is performed
+ * only if UARTE is going to be disabled. For example when runtime device PM is used
+ * then UARTE might kept enabled and flushing is not performed. Preparation is
+ * harmless so it is always possible to just start another RX.
+ *
+ * However, UARTE does not update RXAMOUNT register if fifo is empty. Old value
+ * remains. In certain cases it makes it impossible to distinguish between
+ * case when fifo was empty and not. Function is trying to minimize chances of
+ * error with following measures:
+ * - RXAMOUNT is read before flushing and compared against value after flushing
+ *   if they differ it indicates that data was flushed
+ * - user buffer is dirtied and if RXAMOUNT did not changed it is checked if
+ *   it is still dirty. If not then it indicates that data was flushed
+ *
+ * In other cases function indicates that fifo was empty. It means that if
+ * number of bytes in the fifo equal last rx transfer length and data is equal
+ * to dirty marker it will be discarded.
+ *
+ * @param dev Device.
+ */
+static void rx_flush_prepare(const struct device *dev)
+{
+	/* Flushing RX fifo requires buffer bigger than 4 bytes to empty fifo*/
+	static const uint8_t dirty = CONFIG_UART_NRFX_UARTE_RX_FLUSH_MAGIC_BYTE;
+	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
+	const struct uarte_nrfx_config *config = dev->config;
+	struct uarte_nrfx_data *data = dev->data;
+
+	if (IS_ENABLED(RX_FLUSH_WORKAROUND)) {
+		memset(config->rx_flush_buf, dirty, UARTE_HW_RX_FIFO_SIZE);
+		if (IS_ENABLED(UARTE_ANY_CACHE) && (config->flags & UARTE_CFG_FLAG_CACHEABLE)) {
+			sys_cache_data_flush_range(config->rx_flush_buf, UARTE_HW_RX_FIFO_SIZE);
+		}
+	}
+
+	data->async->rx.prev_amount = nrf_uarte_rx_amount_get(uarte);
+	nrf_uarte_rx_buffer_set(uarte, config->rx_flush_buf, UARTE_HW_RX_FIFO_SIZE);
+	/* Final part of handling RXTO event is in ENDRX interrupt
+	 * handler. ENDRX is generated as a result of FLUSHRX task.
+	 */
+	__ASSERT_NO_MSG(!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX));
+}
+
+/** @brief Actual RX FIFO flushing
+ *
+ * @param dev Device.
+ *
+ * @return number of bytes flushed from the fifo.
+ */
+static uint8_t rx_flush(const struct device *dev)
+{
+	/* Flushing RX fifo requires buffer bigger than 4 bytes to empty fifo*/
+	static const uint8_t dirty = CONFIG_UART_NRFX_UARTE_RX_FLUSH_MAGIC_BYTE;
+	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
+	const struct uarte_nrfx_config *config = dev->config;
+	struct uarte_nrfx_data *data = dev->data;
+	uint32_t rx_amount;
+
+	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_FLUSHRX);
+	while (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
+		/* empty */
+	}
+	nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
+	nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXSTARTED);
+
+	if (IS_ENABLED(UARTE_ANY_CACHE) && (config->flags & UARTE_CFG_FLAG_CACHEABLE)) {
+		sys_cache_data_invd_range(config->rx_flush_buf, UARTE_HW_RX_FIFO_SIZE);
+	}
+
+	rx_amount = nrf_uarte_rx_amount_get(uarte);
+	if (!IS_ENABLED(RX_FLUSH_WORKAROUND)) {
+		return rx_amount;
+	}
+
+	if (rx_amount != data->async->rx.prev_amount) {
+		return rx_amount;
+	}
+
+	if (rx_amount > UARTE_HW_RX_FIFO_SIZE) {
+		return 0;
+	}
+
+	/* If event is set that means it came after ENDRX so there was at least
+	 * one byte in the RX FIFO.
+	 */
+	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXDRDY)) {
+		return rx_amount;
+	}
+
+	for (int i = 0; i < rx_amount; i++) {
+		if (config->rx_flush_buf[i] != dirty) {
+			return rx_amount;
+		}
+	}
+
+	return 0;
+}
 /** @brief Disable UARTE peripheral is not used by RX or TX.
  *
  * It must be called with interrupts locked so that deciding if no direction is
@@ -678,6 +777,9 @@ static void uarte_disable_locked(const struct device *dev, uint32_t dis_mask, ui
 		return;
 	}
 
+	if (data->async && data->async->rx.prev_amount) {
+		data->async->rx.flush_cnt = rx_flush(dev);
+	}
 #if !defined(CONFIG_UART_NRFX_UARTE_ENHANCED_RX)
 	const struct uarte_nrfx_config *config = dev->config;
 
@@ -691,9 +793,6 @@ static void uarte_disable_locked(const struct device *dev, uint32_t dis_mask, ui
 
 	nrf_uarte_disable(get_uarte_instance(dev));
 }
-#endif
-
-#ifdef UARTE_ANY_ASYNC
 
 static void rx_timeout(struct k_timer *timer);
 static void tx_timeout(struct k_timer *timer);
@@ -1434,93 +1533,6 @@ static void endrx_isr(const struct device *dev)
 #endif
 }
 
-/* Function for flushing internal RX fifo. Function can be called in case
- * flushed data is discarded or when data is valid and needs to be retrieved.
- *
- * However, UARTE does not update RXAMOUNT register if fifo is empty. Old value
- * remains. In certain cases it makes it impossible to distinguish between
- * case when fifo was empty and not. Function is trying to minimize chances of
- * error with following measures:
- * - RXAMOUNT is read before flushing and compared against value after flushing
- *   if they differ it indicates that data was flushed
- * - user buffer is dirtied and if RXAMOUNT did not changed it is checked if
- *   it is still dirty. If not then it indicates that data was flushed
- *
- * In other cases function indicates that fifo was empty. It means that if
- * number of bytes in the fifo equal last rx transfer length and data is equal
- * to dirty marker it will be discarded.
- *
- * @param dev Device.
- * @param buf Buffer for flushed data, null indicates that flushed data can be
- *	      dropped but we still want to get amount of data flushed.
- * @param len Buffer size, not used if @p buf is null.
- *
- * @return number of bytes flushed from the fifo.
- */
-
-static uint8_t rx_flush(const struct device *dev, uint8_t *buf)
-{
-	/* Flushing RX fifo requires buffer bigger than 4 bytes to empty fifo*/
-	static const uint8_t dirty = CONFIG_UART_NRFX_UARTE_RX_FLUSH_MAGIC_BYTE;
-	NRF_UARTE_Type *uarte = get_uarte_instance(dev);
-	const struct uarte_nrfx_config *config = dev->config;
-	uint32_t prev_rx_amount;
-	uint32_t rx_amount;
-
-	if (IS_ENABLED(RX_FLUSH_WORKAROUND)) {
-		memset(buf, dirty, UARTE_HW_RX_FIFO_SIZE);
-		if (IS_ENABLED(UARTE_ANY_CACHE) && (config->flags & UARTE_CFG_FLAG_CACHEABLE)) {
-			sys_cache_data_flush_range(buf, UARTE_HW_RX_FIFO_SIZE);
-		}
-		prev_rx_amount = nrf_uarte_rx_amount_get(uarte);
-	} else {
-		prev_rx_amount = 0;
-	}
-
-	nrf_uarte_rx_buffer_set(uarte, buf, UARTE_HW_RX_FIFO_SIZE);
-	/* Final part of handling RXTO event is in ENDRX interrupt
-	 * handler. ENDRX is generated as a result of FLUSHRX task.
-	 */
-	nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
-	nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_FLUSHRX);
-	while (!nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_ENDRX)) {
-		/* empty */
-	}
-	nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
-	nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_RXSTARTED);
-
-	rx_amount = nrf_uarte_rx_amount_get(uarte);
-	if (!buf || !IS_ENABLED(RX_FLUSH_WORKAROUND)) {
-		return rx_amount;
-	}
-
-	if (rx_amount != prev_rx_amount) {
-		return rx_amount;
-	}
-
-	if (rx_amount > UARTE_HW_RX_FIFO_SIZE) {
-		return 0;
-	}
-
-	/* If event is set that means it came after ENDRX so there was at least
-	 * one byte in the RX FIFO.
-	 */
-	if (nrf_uarte_event_check(uarte, NRF_UARTE_EVENT_RXDRDY)) {
-		return rx_amount;
-	}
-
-	if (IS_ENABLED(UARTE_ANY_CACHE) && (config->flags & UARTE_CFG_FLAG_CACHEABLE)) {
-		sys_cache_data_invd_range(buf, UARTE_HW_RX_FIFO_SIZE);
-	}
-
-	for (int i = 0; i < rx_amount; i++) {
-		if (buf[i] != dirty) {
-			return rx_amount;
-		}
-	}
-
-	return 0;
-}
 
 /* This handler is called when the receiver is stopped. If rx was aborted
  * data from fifo is flushed.
@@ -1553,17 +1565,16 @@ static void rxto_isr(const struct device *dev)
 		async_rx->discard_fifo = false;
 #if !defined(CONFIG_UART_NRFX_UARTE_ENHANCED_RX)
 		if (HW_RX_COUNTING_ENABLED(config)) {
-			uint8_t buf[UARTE_HW_RX_FIFO_SIZE];
-
 			/* It need to be included because TIMER+PPI got RXDRDY events
 			 * and counted those flushed bytes.
 			 */
-			async_rx->total_user_byte_cnt += rx_flush(dev, buf);
-			(void)buf;
+			rx_flush_prepare(dev);
+			async_rx->total_user_byte_cnt += rx_flush(dev);
 		}
+		async_rx->prev_amount = 0;
 #endif
 	} else {
-		async_rx->flush_cnt = rx_flush(dev, config->rx_flush_buf);
+		rx_flush_prepare(dev);
 	}
 
 #ifdef UARTE_HAS_FRAME_TIMEOUT
@@ -2175,6 +2186,9 @@ static void uarte_pm_suspend(const struct device *dev)
 	(void)data;
 #ifdef UARTE_ANY_ASYNC
 	if (data->async) {
+		if (data->async->rx.prev_amount) {
+			data->async->rx.flush_cnt = rx_flush(dev);
+		}
 		/* Entering inactive state requires device to be no
 		 * active asynchronous calls.
 		 */