1414#include <zephyr/kernel.h>
1515#include <zephyr/sys/util_macro.h>
1616
17- /* nPM1300 GPIO base address */
17+ /* nPM13xx GPIO base address */
1818#define NPM_GPIO_BASE 0x06U
1919
20- /* nPM1300 GPIO registers offsets */
20+ /* nPM13xx GPIO registers offsets */
2121#define NPM_GPIO_OFFSET_MODE 0x00U
2222#define NPM_GPIO_OFFSET_DRIVE 0x05U
2323#define NPM_GPIO_OFFSET_PULLUP 0x0AU
2626#define NPM_GPIO_OFFSET_DEBOUNCE 0x19U
2727#define NPM_GPIO_OFFSET_STATUS 0x1EU
2828
29- /* nPM1300 Channel counts */
30- #define NPM1300_GPIO_PINS 5U
31-
32- #define NPM1300_GPIO_GPIINPUT 0
33- #define NPM1300_GPIO_GPILOGIC1 1
34- #define NPM1300_GPIO_GPILOGIC0 2
35- #define NPM1300_GPIO_GPIEVENTRISE 3
36- #define NPM1300_GPIO_GPIEVENTFALL 4
37- #define NPM1300_GPIO_GPOIRQ 5
38- #define NPM1300_GPIO_GPORESET 6
39- #define NPM1300_GPIO_GPOPWRLOSSWARN 7
40- #define NPM1300_GPIO_GPOLOGIC1 8
41- #define NPM1300_GPIO_GPOLOGIC0 9
42-
43- struct gpio_npm1300_config {
29+ /* nPM13xx Channel counts */
30+ #define NPM13XX_GPIO_PINS 5U
31+
32+ #define NPM13XX_GPIO_GPIINPUT 0
33+ #define NPM13XX_GPIO_GPILOGIC1 1
34+ #define NPM13XX_GPIO_GPILOGIC0 2
35+ #define NPM13XX_GPIO_GPIEVENTRISE 3
36+ #define NPM13XX_GPIO_GPIEVENTFALL 4
37+ #define NPM13XX_GPIO_GPOIRQ 5
38+ #define NPM13XX_GPIO_GPORESET 6
39+ #define NPM13XX_GPIO_GPOPWRLOSSWARN 7
40+ #define NPM13XX_GPIO_GPOLOGIC1 8
41+ #define NPM13XX_GPIO_GPOLOGIC0 9
42+
43+ struct gpio_npm13xx_config {
4444 struct gpio_driver_config common ;
4545 const struct device * mfd ;
4646};
4747
48- struct gpio_npm1300_data {
48+ struct gpio_npm13xx_data {
4949 struct gpio_driver_data common ;
5050};
5151
52- static int gpio_npm1300_port_get_raw (const struct device * dev , uint32_t * value )
52+ static int gpio_npm13xx_port_get_raw (const struct device * dev , uint32_t * value )
5353{
54- const struct gpio_npm1300_config * config = dev -> config ;
54+ const struct gpio_npm13xx_config * config = dev -> config ;
5555 int ret ;
5656 uint8_t data ;
5757
58- ret = mfd_npm1300_reg_read (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_STATUS , & data );
58+ ret = mfd_npm13xx_reg_read (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_STATUS , & data );
5959
6060 if (ret < 0 ) {
6161 return ret ;
@@ -66,22 +66,22 @@ static int gpio_npm1300_port_get_raw(const struct device *dev, uint32_t *value)
6666 return 0 ;
6767}
6868
69- static int gpio_npm1300_port_set_masked_raw (const struct device * dev , gpio_port_pins_t mask ,
69+ static int gpio_npm13xx_port_set_masked_raw (const struct device * dev , gpio_port_pins_t mask ,
7070 gpio_port_value_t value )
7171{
72- const struct gpio_npm1300_config * config = dev -> config ;
72+ const struct gpio_npm13xx_config * config = dev -> config ;
7373 int ret = 0 ;
7474
75- for (size_t idx = 0 ; idx < NPM1300_GPIO_PINS ; idx ++ ) {
75+ for (size_t idx = 0 ; idx < NPM13XX_GPIO_PINS ; idx ++ ) {
7676 if ((mask & BIT (idx )) != 0U ) {
7777 if ((value & BIT (idx )) != 0U ) {
78- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE ,
78+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE ,
7979 NPM_GPIO_OFFSET_MODE + idx ,
80- NPM1300_GPIO_GPOLOGIC1 );
80+ NPM13XX_GPIO_GPOLOGIC1 );
8181 } else {
82- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE ,
82+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE ,
8383 NPM_GPIO_OFFSET_MODE + idx ,
84- NPM1300_GPIO_GPOLOGIC0 );
84+ NPM13XX_GPIO_GPOLOGIC0 );
8585 }
8686 if (ret != 0U ) {
8787 return ret ;
@@ -92,118 +92,118 @@ static int gpio_npm1300_port_set_masked_raw(const struct device *dev, gpio_port_
9292 return ret ;
9393}
9494
95- static int gpio_npm1300_port_set_bits_raw (const struct device * dev , gpio_port_pins_t pins )
95+ static int gpio_npm13xx_port_set_bits_raw (const struct device * dev , gpio_port_pins_t pins )
9696{
97- return gpio_npm1300_port_set_masked_raw (dev , pins , pins );
97+ return gpio_npm13xx_port_set_masked_raw (dev , pins , pins );
9898}
9999
100- static int gpio_npm1300_port_clear_bits_raw (const struct device * dev , gpio_port_pins_t pins )
100+ static int gpio_npm13xx_port_clear_bits_raw (const struct device * dev , gpio_port_pins_t pins )
101101{
102- return gpio_npm1300_port_set_masked_raw (dev , pins , 0U );
102+ return gpio_npm13xx_port_set_masked_raw (dev , pins , 0U );
103103}
104104
105- static inline int gpio_npm1300_configure (const struct device * dev , gpio_pin_t pin ,
105+ static inline int gpio_npm13xx_configure (const struct device * dev , gpio_pin_t pin ,
106106 gpio_flags_t flags )
107107{
108- const struct gpio_npm1300_config * config = dev -> config ;
108+ const struct gpio_npm13xx_config * config = dev -> config ;
109109 int ret = 0 ;
110110
111111 if (k_is_in_isr ()) {
112112 return - EWOULDBLOCK ;
113113 }
114114
115- if (pin >= NPM1300_GPIO_PINS ) {
115+ if (pin >= NPM13XX_GPIO_PINS ) {
116116 return - EINVAL ;
117117 }
118118
119119 /* Configure mode */
120120 if ((flags & GPIO_INPUT ) != 0U ) {
121121 if (flags & GPIO_ACTIVE_LOW ) {
122- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE ,
122+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE ,
123123 NPM_GPIO_OFFSET_MODE + pin ,
124- NPM1300_GPIO_GPIEVENTFALL );
124+ NPM13XX_GPIO_GPIEVENTFALL );
125125 } else {
126- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE ,
126+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE ,
127127 NPM_GPIO_OFFSET_MODE + pin ,
128- NPM1300_GPIO_GPIEVENTRISE );
128+ NPM13XX_GPIO_GPIEVENTRISE );
129129 }
130- } else if ((flags & NPM1300_GPIO_WDT_RESET_ON ) != 0U ) {
131- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_MODE + pin ,
132- NPM1300_GPIO_GPORESET );
133- } else if ((flags & NPM1300_GPIO_PWRLOSSWARN_ON ) != 0U ) {
134- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_MODE + pin ,
135- NPM1300_GPIO_GPOPWRLOSSWARN );
130+ } else if ((flags & NPM13XX_GPIO_WDT_RESET_ON ) != 0U ) {
131+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_MODE + pin ,
132+ NPM13XX_GPIO_GPORESET );
133+ } else if ((flags & NPM13XX_GPIO_PWRLOSSWARN_ON ) != 0U ) {
134+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_MODE + pin ,
135+ NPM13XX_GPIO_GPOPWRLOSSWARN );
136136 } else if ((flags & GPIO_OUTPUT_INIT_HIGH ) != 0U ) {
137- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_MODE + pin ,
138- NPM1300_GPIO_GPOLOGIC1 );
137+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_MODE + pin ,
138+ NPM13XX_GPIO_GPOLOGIC1 );
139139 } else if ((flags & GPIO_OUTPUT ) != 0U ) {
140- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_MODE + pin ,
141- NPM1300_GPIO_GPOLOGIC0 );
140+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_MODE + pin ,
141+ NPM13XX_GPIO_GPOLOGIC0 );
142142 }
143143
144144 if (ret < 0 ) {
145145 return ret ;
146146 }
147147
148148 /* Configure open drain */
149- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_OPENDRAIN + pin ,
149+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_OPENDRAIN + pin ,
150150 !!(flags & GPIO_SINGLE_ENDED ));
151151 if (ret < 0 ) {
152152 return ret ;
153153 }
154154
155155 /* Configure pulls */
156- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_PULLUP + pin ,
156+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_PULLUP + pin ,
157157 !!(flags & GPIO_PULL_UP ));
158158 if (ret < 0 ) {
159159 return ret ;
160160 }
161161
162- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_PULLDOWN + pin ,
162+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_PULLDOWN + pin ,
163163 !!(flags & GPIO_PULL_DOWN ));
164164 if (ret < 0 ) {
165165 return ret ;
166166 }
167167
168168 /* Configure drive strength and debounce */
169- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_DRIVE + pin ,
170- !!(flags & NPM1300_GPIO_DRIVE_6MA ));
169+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_DRIVE + pin ,
170+ !!(flags & NPM13XX_GPIO_DRIVE_6MA ));
171171 if (ret < 0 ) {
172172 return ret ;
173173 }
174174
175- ret = mfd_npm1300_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_DEBOUNCE + pin ,
176- !!(flags & NPM1300_GPIO_DEBOUNCE_ON ));
175+ ret = mfd_npm13xx_reg_write (config -> mfd , NPM_GPIO_BASE , NPM_GPIO_OFFSET_DEBOUNCE + pin ,
176+ !!(flags & NPM13XX_GPIO_DEBOUNCE_ON ));
177177
178178 return ret ;
179179}
180180
181- static int gpio_npm1300_port_toggle_bits (const struct device * dev , gpio_port_pins_t pins )
181+ static int gpio_npm13xx_port_toggle_bits (const struct device * dev , gpio_port_pins_t pins )
182182{
183183 int ret ;
184184 uint32_t value ;
185185
186- ret = gpio_npm1300_port_get_raw (dev , & value );
186+ ret = gpio_npm13xx_port_get_raw (dev , & value );
187187
188188 if (ret < 0 ) {
189189 return ret ;
190190 }
191191
192- return gpio_npm1300_port_set_masked_raw (dev , pins , ~value );
192+ return gpio_npm13xx_port_set_masked_raw (dev , pins , ~value );
193193}
194194
195- static DEVICE_API (gpio , gpio_npm1300_api ) = {
196- .pin_configure = gpio_npm1300_configure ,
197- .port_get_raw = gpio_npm1300_port_get_raw ,
198- .port_set_masked_raw = gpio_npm1300_port_set_masked_raw ,
199- .port_set_bits_raw = gpio_npm1300_port_set_bits_raw ,
200- .port_clear_bits_raw = gpio_npm1300_port_clear_bits_raw ,
201- .port_toggle_bits = gpio_npm1300_port_toggle_bits ,
195+ static DEVICE_API (gpio , gpio_npm13xx_api ) = {
196+ .pin_configure = gpio_npm13xx_configure ,
197+ .port_get_raw = gpio_npm13xx_port_get_raw ,
198+ .port_set_masked_raw = gpio_npm13xx_port_set_masked_raw ,
199+ .port_set_bits_raw = gpio_npm13xx_port_set_bits_raw ,
200+ .port_clear_bits_raw = gpio_npm13xx_port_clear_bits_raw ,
201+ .port_toggle_bits = gpio_npm13xx_port_toggle_bits ,
202202};
203203
204- static int gpio_npm1300_init (const struct device * dev )
204+ static int gpio_npm13xx_init (const struct device * dev )
205205{
206- const struct gpio_npm1300_config * config = dev -> config ;
206+ const struct gpio_npm13xx_config * config = dev -> config ;
207207
208208 if (!device_is_ready (config -> mfd )) {
209209 return - ENODEV ;
@@ -212,18 +212,18 @@ static int gpio_npm1300_init(const struct device *dev)
212212 return 0 ;
213213}
214214
215- #define GPIO_NPM1300_DEFINE (n ) \
216- static const struct gpio_npm1300_config gpio_npm1300_config ##n = { \
215+ #define GPIO_NPM13XX_DEFINE (n ) \
216+ static const struct gpio_npm13xx_config gpio_npm13xx_config ##n = { \
217217 .common = \
218218 { \
219219 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \
220220 }, \
221221 .mfd = DEVICE_DT_GET(DT_INST_PARENT(n))}; \
222222 \
223- static struct gpio_npm1300_data gpio_npm1300_data ##n; \
223+ static struct gpio_npm13xx_data gpio_npm13xx_data ##n; \
224224 \
225- DEVICE_DT_INST_DEFINE(n, gpio_npm1300_init , NULL, &gpio_npm1300_data ##n, \
226- &gpio_npm1300_config ##n, POST_KERNEL, \
227- CONFIG_GPIO_NPM1300_INIT_PRIORITY , &gpio_npm1300_api );
225+ DEVICE_DT_INST_DEFINE(n, gpio_npm13xx_init , NULL, &gpio_npm13xx_data ##n, \
226+ &gpio_npm13xx_config ##n, POST_KERNEL, \
227+ CONFIG_GPIO_NPM13XX_INIT_PRIORITY , &gpio_npm13xx_api );
228228
229- DT_INST_FOREACH_STATUS_OKAY (GPIO_NPM1300_DEFINE )
229+ DT_INST_FOREACH_STATUS_OKAY (GPIO_NPM13XX_DEFINE )
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