Revert "[nrf fromlist] boards: nrf54h20dk: Merge iron variants into the base variants"

This reverts commit 6a5823e.

Signed-off-by: Jonathan Nilsen <[email protected]>

Author: jonathannilsen

boards/nordic/nrf54h20dk/Kconfig.defconfig

@@ -9,26 +9,28 @@ config BT_HCI_IPC
 config MAX_THREAD_BYTES
 	default 3 if USERSPACE
 
-config ROM_START_OFFSET
-	default 0x800 if BOOTLOADER_MCUBOOT
-
-if !USE_DT_CODE_PARTITION
-
-# Application core firmware must start at this offset when not using MCUboot.
-# However, the default 'zephyr,code-partition' in DT is set for MCUboot.
-config FLASH_LOAD_OFFSET
-	default $(dt_nodelabel_reg_addr_hex,cpuapp_boot_partition)
-
-endif # !USE_DT_CODE_PARTITION
-
 endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP
 
 if BOARD_NRF54H20DK_NRF54H20_CPURAD
 
 config MAX_THREAD_BYTES
 	default 3 if USERSPACE
 
+endif # BOARD_NRF54H20DK_NRF54H20_CPURAD
+
+if BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON
+
 config ROM_START_OFFSET
 	default 0x800 if BOOTLOADER_MCUBOOT
 
-endif # BOARD_NRF54H20DK_NRF54H20_CPURAD
+config FLASH_LOAD_OFFSET
+	default 0x2c000 if !USE_DT_CODE_PARTITION
+
+endif # BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON
+
+if BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON
+
+config ROM_START_OFFSET
+	default 0x800 if BOOTLOADER_MCUBOOT
+
+endif # BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON

boards/nordic/nrf54h20dk/Kconfig.nrf54h20dk

@@ -2,9 +2,13 @@
 # SPDX-License-Identifier: Apache-2.0
 
 config BOARD_NRF54H20DK
-	select SOC_NRF54H20_CPUAPP if BOARD_NRF54H20DK_NRF54H20_CPUAPP
-	select SOC_NRF54H20_CPURAD if BOARD_NRF54H20DK_NRF54H20_CPURAD
+	select SOC_NRF54H20_CPUAPP if (BOARD_NRF54H20DK_NRF54H20_CPUAPP || \
+				       BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON)
+	select SOC_NRF54H20_CPURAD if (BOARD_NRF54H20DK_NRF54H20_CPURAD || \
+				       BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON)
 	select SOC_NRF54H20_CPUPPR if (BOARD_NRF54H20DK_NRF54H20_CPUPPR || \
 				       BOARD_NRF54H20DK_NRF54H20_CPUPPR_XIP)
 	select SOC_NRF54H20_CPUFLPR if (BOARD_NRF54H20DK_NRF54H20_CPUFLPR || \
 				        BOARD_NRF54H20DK_NRF54H20_CPUFLPR_XIP)
+	select SOC_NRF54H20_IRON if (BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON || \
+				       BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON)

boards/nordic/nrf54h20dk/board.cmake

@@ -2,7 +2,10 @@
 
 include(${ZEPHYR_BASE}/boards/common/nrfutil.board.cmake)
 
-if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD)
+if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR
+   CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD OR
+   CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP_IRON OR
+   CONFIG_BOARD_NRF54H20DK_NRF54H20_CPURAD_IRON)
   if(CONFIG_SOC_NRF54H20_CPUAPP)
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuapp.JLinkScript)
   else()
@@ -14,7 +17,7 @@ if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUAPP OR CONFIG_BOARD_NRF54H20DK_NRF54H20_C
 endif()
 
 if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR OR CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUFLPR)
-  if(CONFIG_SOC_NRF54H20_CPUPPR)
+  if(CONFIG_BOARD_NRF54H20DK_NRF54H20_CPUPPR)
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuppr.JLinkScript)
   else()
     set(JLINKSCRIPTFILE ${CMAKE_CURRENT_LIST_DIR}/support/nrf54h20_cpuflpr.JLinkScript)

boards/nordic/nrf54h20dk/board.yml

@@ -9,6 +9,10 @@ board:
       cpucluster: cpuppr
     - name: xip
       cpucluster: cpuflpr
+    - name: iron
+      cpucluster: cpuapp
+    - name: iron
+      cpucluster: cpurad
   revision:
     format: major.minor.patch
     default: "0.9.0"

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf.dtsi

@@ -7,17 +7,17 @@
 / {
 	ipc {
 		cpusec_cpuapp_ipc: ipc-1-2 {
-			compatible = "nordic,ironside-call";
+			compatible = "zephyr,ipc-icmsg";
 			status = "disabled";
-			memory-region = <&cpusec_cpuapp_ipc_shm>;
+			dcache-alignment = <32>;
 			mboxes = <&cpusec_bellboard 12>,
 				 <&cpuapp_bellboard 0>;
 		};
 
 		cpusec_cpurad_ipc: ipc-1-3 {
-			compatible = "nordic,ironside-call";
+			compatible = "zephyr,ipc-icmsg";
 			status = "disabled";
-			memory-region = <&cpusec_cpurad_ipc_shm>;
+			dcache-alignment = <32>;
 			mboxes = <&cpusec_bellboard 18>,
 				 <&cpurad_bellboard 0>;
 		};

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-ipc_conf_iron.dtsi

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is to be merged with the original ipc_conf.dtsi in the future. */
+
+/ {
+	ipc {
+		/delete-node/ ipc-1-2;
+		/delete-node/ ipc-1-3;
+
+		cpusec_cpuapp_ipc: ipc-1-2 {
+			compatible = "nordic,ironside-call";
+			memory-region = <&cpusec_cpuapp_ipc_shm>;
+			mboxes = <&cpusec_bellboard 12>,
+				 <&cpuapp_bellboard 0>;
+			status = "disabled";
+		};
+
+		cpusec_cpurad_ipc: ipc-1-3 {
+			compatible = "nordic,ironside-call";
+			memory-region = <&cpusec_cpurad_ipc_shm>;
+			mboxes = <&cpusec_bellboard 18>,
+				 <&cpurad_bellboard 0>;
+			status = "disabled";
+		};
+	};
+};

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map.dtsi

@@ -16,6 +16,14 @@
 			#size-cells = <1>;
 			ranges = <0x0 0x2f010000 0x41000>;
 
+			cpusec_cpuapp_ipc_shm: memory@0 {
+				reg = <0x0 DT_SIZE_K(2)>;
+			};
+
+			cpuapp_cpusec_ipc_shm: memory@800 {
+				reg = <0x800 DT_SIZE_K(2)>;
+			};
+
 			cpuapp_data: memory@1000 {
 				reg = <0x1000 DT_SIZE_K(256)>;
 			};
@@ -29,6 +37,14 @@
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges = <0x0 0x2f051000 0x1000>;
+
+			cpusec_cpurad_ipc_shm: memory@0 {
+				reg = <0x0 DT_SIZE_K(2)>;
+			};
+
+			cpurad_cpusec_ipc_shm: memory@800 {
+				reg = <0x800 DT_SIZE_K(2)>;
+			};
 		};
 
 		etr_buf_ram0x_region: memory@2f0be000 {
@@ -65,44 +81,20 @@
 			};
 		};
 
-		cpuapp_cpusys_ipc_shm: memory@2f88f600 {
-			reg = <0x2f88f600 0x80>;
-		};
-
-		cpusys_cpuapp_ipc_shm: memory@2f88f680 {
-			reg = <0x2f88f680 0x80>;
-		};
-
-		cpurad_cpusys_ipc_shm: memory@2f88f700 {
-			reg = <0x2f88f700 0x80>;
+		cpuapp_cpusys_ipc_shm: memory@2f88fce0 {
+			reg = <0x2f88fce0 0x80>;
 		};
 
-		cpusys_cpurad_ipc_shm: memory@2f88f780 {
-			reg = <0x2f88f780 0x80>;
+		cpusys_cpuapp_ipc_shm: memory@2f88fd60 {
+			reg = <0x2f88fd60 0x80>;
 		};
 
-		cpusec_cpurad_ipc_shm: memory@2f88f800 {
-			reg = <0x2f88f800 0x80>;
+		cpurad_cpusys_ipc_shm: memory@2f88fe00 {
+			reg = <0x2f88fe00 0x80>;
 		};
 
-		cpurad_ironside_se_event_report: memory@2f88f880 {
-			reg = <0x2f88f880 0x100>;
-		};
-
-		cpurad_ironside_se_boot_report: memory@2f88f980 {
-			reg = <0x2f88f980 0x200>;
-		};
-
-		cpusec_cpuapp_ipc_shm: memory@2f88fb80 {
-			reg = <0x2f88fb80 0x80>;
-		};
-
-		cpuapp_ironside_se_event_report: memory@2f88fc00 {
-			reg = <0x2f88fc00 0x100>;
-		};
-
-		cpuapp_ironside_se_boot_report: memory@2f88fd00 {
-			reg = <0x2f88fd00 0x200>;
+		cpusys_cpurad_ipc_shm: memory@2f88fe80 {
+			reg = <0x2f88fe80 0x80>;
 		};
 
 		/*
@@ -195,21 +187,27 @@
 };
 
 &mram1x {
-	partitions {
-		compatible = "fixed-partitions";
+	cpurad_rx_partitions: cpurad-rx-partitions {
+		compatible = "nordic,owned-partitions", "fixed-partitions";
+		status = "disabled";
+		nordic,access = <NRF_OWNER_ID_RADIOCORE NRF_PERM_RXS>;
 		#address-cells = <1>;
 		#size-cells = <1>;
 
-		cpuapp_boot_partition: partition@2c000 {
-			reg = <0x2c000 DT_SIZE_K(64)>;
+		cpurad_slot0_partition: partition@54000 {
+			reg = <0x54000 DT_SIZE_K(256)>;
 		};
+	};
 
-		cpuapp_slot0_partition: partition@3c000 {
-			reg = <0x3c000 DT_SIZE_K(336)>;
-		};
+	cpuapp_rx_partitions: cpuapp-rx-partitions {
+		compatible = "nordic,owned-partitions", "fixed-partitions";
+		status = "disabled";
+		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RXS>;
+		#address-cells = <1>;
+		#size-cells = <1>;
 
-		cpurad_slot0_partition: partition@90000 {
-			reg = <0x90000 DT_SIZE_K(336)>;
+		cpuapp_slot0_partition: partition@94000 {
+			reg = <0x94000 DT_SIZE_K(320)>;
 		};
 
 		cpuppr_code_partition: partition@e4000 {
@@ -219,17 +217,21 @@
 		cpuflpr_code_partition: partition@f4000 {
 			reg = <0xf4000 DT_SIZE_K(48)>;
 		};
+	};
 
-		cpuapp_slot1_partition: partition@100000 {
-			reg = <0x100000 DT_SIZE_K(336)>;
-		};
+	cpuapp_rw_partitions: cpuapp-rw-partitions {
+		compatible = "nordic,owned-partitions", "fixed-partitions";
+		status = "disabled";
+		nordic,access = <NRF_OWNER_ID_APPLICATION NRF_PERM_RWS>;
+		#address-cells = <1>;
+		#size-cells = <1>;
 
-		cpurad_slot1_partition: partition@154000 {
-			reg = <0x154000 DT_SIZE_K(336)>;
+		dfu_partition: partition@100000 {
+			reg = < 0x100000 DT_SIZE_K(908) >;
 		};
 
-		storage_partition: partition@1a8000 {
-			reg = <0x1a8000 DT_SIZE_K(40)>;
+		storage_partition: partition@1e3000 {
+			reg = < 0x1e3000 DT_SIZE_K(40) >;
 		};
 	};
 };

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20-memory_map_iron.dtsi

@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* This file is to be merged with the original memory_map.dtsi in the future.
+ * The following nodes will be replaced:
+ */
+/delete-node/ &cpuapp_cpusec_ipc_shm;
+/delete-node/ &cpuapp_cpusys_ipc_shm;
+/delete-node/ &cpurad_cpusec_ipc_shm;
+/delete-node/ &cpurad_cpusys_ipc_shm;
+/delete-node/ &cpusec_cpuapp_ipc_shm;
+/delete-node/ &cpusec_cpurad_ipc_shm;
+/delete-node/ &cpusys_cpuapp_ipc_shm;
+/delete-node/ &cpusys_cpurad_ipc_shm;
+/delete-node/ &cpuapp_rw_partitions;
+/delete-node/ &cpuapp_rx_partitions;
+/delete-node/ &cpurad_rx_partitions;
+
+/ {
+	reserved-memory {
+		cpuapp_cpusys_ipc_shm: memory@2f88f600 {
+			reg = <0x2f88f600 0x80>;
+		};
+
+		cpusys_cpuapp_ipc_shm: memory@2f88f680 {
+			reg = <0x2f88f680 0x80>;
+		};
+
+		cpurad_cpusys_ipc_shm: memory@2f88f700 {
+			reg = <0x2f88f700 0x80>;
+		};
+
+		cpusys_cpurad_ipc_shm: memory@2f88f780 {
+			reg = <0x2f88f780 0x80>;
+		};
+
+		cpusec_cpurad_ipc_shm: memory@2f88f800 {
+			reg = <0x2f88f800 0x80>;
+		};
+
+		cpurad_ironside_se_event_report: memory@2f88f880 {
+			reg = <0x2f88f880 0x100>;
+		};
+
+		cpurad_ironside_se_boot_report: memory@2f88f980 {
+			reg = <0x2f88f980 0x200>;
+		};
+
+		cpusec_cpuapp_ipc_shm: memory@2f88fb80 {
+			reg = <0x2f88fb80 0x80>;
+		};
+
+		cpuapp_ironside_se_event_report: memory@2f88fc00 {
+			reg = <0x2f88fc00 0x100>;
+		};
+
+		cpuapp_ironside_se_boot_report: memory@2f88fd00 {
+			reg = <0x2f88fd00 0x200>;
+		};
+	};
+};
+
+&mram1x {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		cpuapp_boot_partition: partition@2c000 {
+			reg = <0x2c000 DT_SIZE_K(64)>;
+		};
+
+		cpuapp_slot0_partition: partition@3c000 {
+			reg = <0x3c000 DT_SIZE_K(336)>;
+		};
+
+		cpurad_slot0_partition: partition@90000 {
+			reg = <0x90000 DT_SIZE_K(336)>;
+		};
+
+		cpuppr_code_partition: partition@e4000 {
+			reg = <0xe4000 DT_SIZE_K(64)>;
+		};
+
+		cpuflpr_code_partition: partition@f4000 {
+			reg = <0xf4000 DT_SIZE_K(48)>;
+		};
+
+		cpuapp_slot1_partition: partition@100000 {
+			reg = <0x100000 DT_SIZE_K(336)>;
+		};
+
+		cpurad_slot1_partition: partition@154000 {
+			reg = <0x154000 DT_SIZE_K(336)>;
+		};
+
+		storage_partition: partition@1a8000 {
+			reg = <0x1a8000 DT_SIZE_K(40)>;
+		};
+	};
+};