[nrf fromlist] drivers: pinctrl: nrf: Add support for TDM peripheral

Add support for configuring pins of the nRF TDM peripheral.

Upstream PR #: 82144

Signed-off-by: Adam Kondraciuk <[email protected]>

Author: adamkondraciuk

drivers/pinctrl/pinctrl_nrf.c

@@ -94,9 +94,8 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
 #define NRF_PSEL_QSPI(reg, line) ((NRF_QSPI_Type *)reg)->PSEL.line
 #endif
 
-#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_twis) || defined(CONFIG_NRFX_TWIS)
-#include <hal/nrf_twis.h>
-#define NRF_PSEL_TWIS(reg, line) ((NRF_TWIS_Type *)reg)->PSEL.line
+#if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_tdm)
+#define NRF_PSEL_TDM(reg, line) ((NRF_TDM_Type *)reg)->PSEL.line
 #endif
 
 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_grtc) || defined(CONFIG_NRFX_GRTC)
@@ -118,10 +117,6 @@ static const nrf_gpio_pin_drive_t drive_modes[NRF_DRIVE_COUNT] = {
 int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			   uintptr_t reg)
 {
-#ifdef CONFIG_SOC_NRF54H20_GPD
-	bool gpd_requested = false;
-#endif
-
 	for (uint8_t i = 0U; i < pin_cnt; i++) {
 		nrf_gpio_pin_drive_t drive;
 		uint8_t drive_idx = NRF_GET_DRIVE(pins[i]);
@@ -361,6 +356,47 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
 			break;
 #endif /* defined(NRF_PSEL_QSPI) */
+#if defined(NRF_PSEL_TDM)
+		case NRF_FUN_TDM_SCK_M:
+			NRF_PSEL_TDM(reg, SCK) = psel;
+			write = 0U;
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
+			break;
+		case NRF_FUN_TDM_SCK_S:
+			NRF_PSEL_TDM(reg, SCK) = psel;
+			dir = NRF_GPIO_PIN_DIR_INPUT;
+			input = NRF_GPIO_PIN_INPUT_CONNECT;
+			break;
+		case NRF_FUN_TDM_FSYNC_M:
+			NRF_PSEL_TDM(reg, FSYNC) = psel;
+			write = 0U;
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
+			break;
+		case NRF_FUN_TDM_FSYNC_S:
+			NRF_PSEL_TDM(reg, FSYNC) = psel;
+			dir = NRF_GPIO_PIN_DIR_INPUT;
+			input = NRF_GPIO_PIN_INPUT_CONNECT;
+			break;
+		case NRF_FUN_TDM_SDIN:
+			NRF_PSEL_TDM(reg, SDIN) = psel;
+			dir = NRF_GPIO_PIN_DIR_INPUT;
+			input = NRF_GPIO_PIN_INPUT_CONNECT;
+			break;
+		case NRF_FUN_TDM_SDOUT:
+			NRF_PSEL_TDM(reg, SDOUT) = psel;
+			write = 0U;
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
+			break;
+		case NRF_FUN_TDM_MCK:
+			NRF_PSEL_TDM(reg, MCK) = psel;
+			write = 0U;
+			dir = NRF_GPIO_PIN_DIR_OUTPUT;
+			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
+			break;
+#endif /* defined(NRF_PSEL_TDM) */
 #if defined(NRF_GRTC_CLKOUT_FAST)
 		case NRF_FUN_GRTC_CLKOUT_FAST:
 #if NRF_GPIO_HAS_SEL && defined(GPIO_PIN_CNF_CTRLSEL_GRTC)
@@ -409,24 +445,6 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 			input = NRF_GPIO_PIN_INPUT_DISCONNECT;
 			break;
 #endif /* DT_HAS_COMPAT_STATUS_OKAY(nordic_nrf_exmif) */
-#if defined(NRF_PSEL_TWIS)
-		case NRF_FUN_TWIS_SCL:
-			NRF_PSEL_TWIS(reg, SCL) = psel;
-			if (drive == NRF_GPIO_PIN_S0S1) {
-				drive = NRF_GPIO_PIN_S0D1;
-			}
-			dir = NRF_GPIO_PIN_DIR_INPUT;
-			input = NRF_GPIO_PIN_INPUT_CONNECT;
-			break;
-		case NRF_FUN_TWIS_SDA:
-			NRF_PSEL_TWIS(reg, SDA) = psel;
-			if (drive == NRF_GPIO_PIN_S0S1) {
-				drive = NRF_GPIO_PIN_S0D1;
-			}
-			dir = NRF_GPIO_PIN_DIR_INPUT;
-			input = NRF_GPIO_PIN_INPUT_CONNECT;
-			break;
-#endif /* defined(NRF_PSEL_TWIS) */
 #if defined(CONFIG_SOC_NRF54L15_CPUAPP)
 #if DT_HAS_COMPAT_STATUS_OKAY(nordic_nrfe_mspi_controller)
 		case NRF_FUN_SDP_MSPI_CS0:
@@ -459,17 +477,16 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 
 #ifdef CONFIG_SOC_NRF54H20_GPD
 			if (NRF_GET_GPD_FAST_ACTIVE1(pins[i]) == 1U) {
-				if (!gpd_requested) {
-					int ret;
-
-					ret = nrf_gpd_request(NRF_GPD_SLOW_ACTIVE);
-					if (ret < 0) {
-						return ret;
-					}
-					gpd_requested = true;
+				int ret;
+				uint32_t d_pin = pin;
+				NRF_GPIO_Type *port = nrf_gpio_pin_port_decode(&d_pin);
+
+				ret = nrf_gpd_request(NRF_GPD_SLOW_ACTIVE);
+				if (ret < 0) {
+					return ret;
 				}
 
-				nrf_gpio_pin_retain_disable(pin);
+				port->RETAINCLR = BIT(d_pin);
 			}
 #endif /* CONFIG_SOC_NRF54H20_GPD */
 
@@ -490,22 +507,20 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt,
 #endif
 #ifdef CONFIG_SOC_NRF54H20_GPD
 			if (NRF_GET_GPD_FAST_ACTIVE1(pins[i]) == 1U) {
-				nrf_gpio_pin_retain_enable(pin);
-			}
-#endif /* CONFIG_SOC_NRF54H20_GPD */
-		}
-	}
+				int ret;
+				uint32_t d_pin = pin;
+				NRF_GPIO_Type *port = nrf_gpio_pin_port_decode(&d_pin);
 
-#ifdef CONFIG_SOC_NRF54H20_GPD
-	if (gpd_requested) {
-		int ret;
+				port->RETAINSET = BIT(d_pin);
 
-		ret = nrf_gpd_release(NRF_GPD_SLOW_ACTIVE);
-		if (ret < 0) {
-			return ret;
+				ret = nrf_gpd_release(NRF_GPD_SLOW_ACTIVE);
+				if (ret < 0) {
+					return ret;
+				}
+			}
+#endif /* CONFIG_SOC_NRF54H20_GPD */
 		}
 	}
-#endif
 
 	return 0;
 }

include/zephyr/dt-bindings/pinctrl/nrf-pinctrl.h

@@ -200,6 +200,20 @@
 #define NRF_FUN_SDP_MSPI_CS3 69U
 /** SDP_MSPI CS4 */
 #define NRF_FUN_SDP_MSPI_CS4 70U
+/** TDM SCK in master mode */
+#define NRF_FUN_TDM_SCK_M        71U
+/** TDM SCK in slave mode */
+#define NRF_FUN_TDM_SCK_S        72U
+/** TDM LRCK in master mode */
+#define NRF_FUN_TDM_FSYNC_M      73U
+/** TDM LRCK in slave mode */
+#define NRF_FUN_TDM_FSYNC_S      74U
+/** TDM SDIN */
+#define NRF_FUN_TDM_SDIN         75U
+/** TDM SDOUT */
+#define NRF_FUN_TDM_SDOUT        76U
+/** TDM MCK */
+#define NRF_FUN_TDM_MCK          77U
 
 /** @} */