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boards/nordic/nrf54h20dk/doc/index.rst

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,7 @@ nRF54H20 SoC provides support for the following devices:
3939
* :abbr:`GPIO (General Purpose Input Output)`
4040
* :abbr:`GRTC (Global real-time counter)`
4141
* :abbr:`I2C (Inter-Integrated Circuit)`
42+
* MEMCONF
4243
* MRAM
4344
* :abbr:`PWM (Pulse Width Modulation)`
4445
* RADIO (Bluetooth Low Energy and 802.15.4)
@@ -70,6 +71,8 @@ hardware features:
7071
+-----------+------------+----------------------+
7172
| I2C(M) | on-chip | i2c |
7273
+-----------+------------+----------------------+
74+
| MEMCONF | on-chip | retained_mem |
75+
+-----------+------------+----------------------+
7376
| SPI(M/S) | on-chip | spi |
7477
+-----------+------------+----------------------+
7578
| UART | on-chip | serial |
@@ -89,6 +92,8 @@ hardware features:
8992
+-----------+------------+----------------------+
9093
| I2C(M) | on-chip | i2c |
9194
+-----------+------------+----------------------+
95+
| MEMCONF | on-chip | retained_mem |
96+
+-----------+------------+----------------------+
9297
| SPI(M/S) | on-chip | spi |
9398
+-----------+------------+----------------------+
9499
| UART | on-chip | serial |

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpuapp_0_9_0.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ supported:
1919
- gpio
2020
- i2c
2121
- pwm
22+
- retained_mem
2223
- spi
2324
- watchdog
2425
- usbd

boards/nordic/nrf54h20dk/nrf54h20dk_nrf54h20_cpurad_0_9_0.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,4 +16,5 @@ supported:
1616
- counter
1717
- gpio
1818
- pwm
19+
- retained_mem
1920
- spi

boards/nordic/nrf54l15dk/doc/index.rst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -19,6 +19,7 @@ nRF54L15 Arm Cortex-M33 CPU and the following devices:
1919
* RRAM
2020
* :abbr:`GPIO (General Purpose Input Output)`
2121
* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
22+
* MEMCONF
2223
* :abbr:`MPU (Memory Protection Unit)`
2324
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
2425
* :abbr:`PWM (Pulse Width Modulation)`
@@ -60,6 +61,8 @@ hardware features:
6061
+-----------+------------+----------------------+
6162
| GRTC | on-chip | counter |
6263
+-----------+------------+----------------------+
64+
| MEMCONF | on-chip | retained_mem |
65+
+-----------+------------+----------------------+
6366
| MPU | on-chip | arch/arm |
6467
+-----------+------------+----------------------+
6568
| NVIC | on-chip | arch/arm |

boards/nordic/nrf54l15pdk/doc/index.rst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,7 @@ the following devices:
2020
* RRAM
2121
* :abbr:`GPIO (General Purpose Input Output)`
2222
* :abbr:`TWIM (I2C-compatible two-wire interface master with EasyDMA)`
23+
* MEMCONF
2324
* :abbr:`MPU (Memory Protection Unit)`
2425
* :abbr:`NVIC (Nested Vectored Interrupt Controller)`
2526
* :abbr:`PWM (Pulse Width Modulation)`
@@ -65,6 +66,8 @@ hardware features:
6566
+-----------+------------+----------------------+
6667
| TWIM | on-chip | i2c |
6768
+-----------+------------+----------------------+
69+
| MEMCONF | on-chip | retained_mem |
70+
+-----------+------------+----------------------+
6871
| MPU | on-chip | arch/arm |
6972
+-----------+------------+----------------------+
7073
| NVIC | on-chip | arch/arm |

drivers/adc/adc_nrfx_saadc.c

Lines changed: 18 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,8 @@
77
#define ADC_CONTEXT_USES_KERNEL_TIMER
88
#include "adc_context.h"
99
#include <haly/nrfy_saadc.h>
10-
#include <zephyr/dt-bindings/adc/nrf-adc.h>
10+
#include <zephyr/dt-bindings/adc/nrf-saadc-v3.h>
11+
#include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
1112
#include <zephyr/linker/devicetree_regions.h>
1213

1314
#define LOG_LEVEL CONFIG_ADC_LOG_LEVEL
@@ -31,7 +32,7 @@ static const uint8_t saadc_psels[NRF_SAADC_AIN7 + 1] = {
3132
[NRF_SAADC_AIN7] = NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
3233
};
3334
#elif defined(CONFIG_SOC_NRF54L15)
34-
static const uint8_t saadc_psels[NRF_SAADC_AIN7 + 1] = {
35+
static const uint32_t saadc_psels[NRF_SAADC_DVDD + 1] = {
3536
[NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
3637
[NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
3738
[NRF_SAADC_AIN2] = NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
@@ -40,6 +41,9 @@ static const uint8_t saadc_psels[NRF_SAADC_AIN7 + 1] = {
4041
[NRF_SAADC_AIN5] = NRF_PIN_PORT_TO_PIN_NUMBER(12U, 1),
4142
[NRF_SAADC_AIN6] = NRF_PIN_PORT_TO_PIN_NUMBER(13U, 1),
4243
[NRF_SAADC_AIN7] = NRF_PIN_PORT_TO_PIN_NUMBER(14U, 1),
44+
[NRF_SAADC_VDD] = NRF_SAADC_INPUT_VDD,
45+
[NRF_SAADC_AVDD] = NRF_SAADC_INPUT_AVDD,
46+
[NRF_SAADC_DVDD] = NRF_SAADC_INPUT_DVDD,
4347
};
4448
#endif
4549

@@ -273,13 +277,8 @@ static int adc_nrfx_channel_setup(const struct device *dev,
273277
m_data.single_ended_channels |= BIT(channel_cfg->channel_id);
274278
}
275279

276-
/* Keep the channel disabled in hardware (set positive input to
277-
* NRF_SAADC_INPUT_DISABLED) until it is selected to be included
278-
* in a sampling sequence.
279-
*/
280-
281280
#if (NRF_SAADC_HAS_AIN_AS_PIN)
282-
if ((channel_cfg->input_positive > NRF_SAADC_AIN7) ||
281+
if ((channel_cfg->input_positive >= ARRAY_SIZE(saadc_psels)) ||
283282
(channel_cfg->input_positive < NRF_SAADC_AIN0)) {
284283
return -EINVAL;
285284
}
@@ -294,17 +293,18 @@ static int adc_nrfx_channel_setup(const struct device *dev,
294293
} else {
295294
input_negative = NRF_SAADC_INPUT_DISABLED;
296295
}
297-
296+
#endif
298297
/* Store the positive input selection in a dedicated array,
299298
* to get it later when the channel is selected for a sampling
300299
* and to mark the channel as configured (ready to be selected).
301300
*/
302-
m_data.positive_inputs[channel_id] = saadc_psels[channel_cfg->input_positive];
303-
#else
304301
m_data.positive_inputs[channel_id] = channel_cfg->input_positive;
305-
#endif
306302

307303
nrf_saadc_channel_init(NRF_SAADC, channel_id, &config);
304+
/* Keep the channel disabled in hardware (set positive input to
305+
* NRF_SAADC_INPUT_DISABLED) until it is selected to be included
306+
* in a sampling sequence.
307+
*/
308308
nrf_saadc_channel_input_set(NRF_SAADC,
309309
channel_id,
310310
NRF_SAADC_INPUT_DISABLED,
@@ -531,7 +531,12 @@ static int start_read(const struct device *dev,
531531
nrf_saadc_channel_pos_input_set(
532532
NRF_SAADC,
533533
channel_id,
534-
m_data.positive_inputs[channel_id]);
534+
#if NRF_SAADC_HAS_AIN_AS_PIN
535+
saadc_psels[m_data.positive_inputs[channel_id]]
536+
#else
537+
m_data.positive_inputs[channel_id]
538+
#endif
539+
);
535540
++active_channels;
536541
} else {
537542
nrf_saadc_burst_set(

drivers/dp/swdp_bitbang.c

Lines changed: 83 additions & 61 deletions
Original file line numberDiff line numberDiff line change
@@ -26,15 +26,16 @@
2626
#include <zephyr/logging/log.h>
2727
LOG_MODULE_REGISTER(swdp, CONFIG_DP_DRIVER_LOG_LEVEL);
2828

29-
#define CLOCK_DELAY(swclk_freq, port_write_cycles) \
30-
((CPU_CLOCK / 2 / swclk_freq) - port_write_cycles)
29+
#define MAX_SWJ_CLOCK(delay_cycles, port_write_cycles) \
30+
((CPU_CLOCK / 2U) / (port_write_cycles + delay_cycles))
3131

3232
/*
3333
* Default SWCLK frequency in Hz.
3434
* sw_clock can be used to overwrite this default value.
3535
*/
3636
#define SWDP_DEFAULT_SWCLK_FREQUENCY 1000000U
3737

38+
#define DELAY_FAST_CYCLES 2U
3839
#define DELAY_SLOW_CYCLES 3U
3940

4041
struct sw_config {
@@ -528,14 +529,19 @@ static int sw_set_clock(const struct device *dev, const uint32_t clock)
528529
struct sw_cfg_data *sw_data = dev->data;
529530
uint32_t delay;
530531

531-
sw_data->fast_clock = false;
532-
delay = ((CPU_CLOCK / 2U) + (clock - 1U)) / clock;
533-
534-
if (delay > config->port_write_cycles) {
535-
delay -= config->port_write_cycles;
536-
delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES;
537-
} else {
532+
if (clock >= MAX_SWJ_CLOCK(DELAY_FAST_CYCLES, config->port_write_cycles)) {
533+
sw_data->fast_clock = true;
538534
delay = 1U;
535+
} else {
536+
sw_data->fast_clock = false;
537+
538+
delay = ((CPU_CLOCK / 2U) + (clock - 1U)) / clock;
539+
if (delay > config->port_write_cycles) {
540+
delay -= config->port_write_cycles;
541+
delay = (delay + (DELAY_SLOW_CYCLES - 1U)) / DELAY_SLOW_CYCLES;
542+
} else {
543+
delay = 1U;
544+
}
539545
}
540546

541547
sw_data->clock_delay = delay;
@@ -562,112 +568,128 @@ static int sw_configure(const struct device *dev,
562568
static int sw_port_on(const struct device *dev)
563569
{
564570
const struct sw_config *config = dev->config;
565-
566-
gpio_pin_set_dt(&config->clk, 1);
571+
int ret;
567572

568573
if (config->dnoe.port) {
569-
gpio_pin_set_dt(&config->dnoe, 1);
574+
ret = gpio_pin_configure_dt(&config->dnoe, GPIO_OUTPUT_ACTIVE);
575+
if (ret) {
576+
return ret;
577+
}
570578
}
571579

572580
if (config->dout.port) {
573-
gpio_pin_set_dt(&config->dout, 1);
574-
} else {
575-
int ret;
576-
577-
ret = gpio_pin_configure_dt(&config->dio, GPIO_OUTPUT_ACTIVE);
581+
ret = gpio_pin_configure_dt(&config->dout, GPIO_OUTPUT_ACTIVE);
578582
if (ret) {
579583
return ret;
580584
}
581585
}
582586

583-
if (config->noe.port) {
584-
gpio_pin_set_dt(&config->noe, 1);
585-
}
586-
if (config->reset.port) {
587-
gpio_pin_set_dt(&config->reset, 1);
588-
}
589-
590-
return 0;
591-
}
592-
593-
static int sw_port_off(const struct device *dev)
594-
{
595-
const struct sw_config *config = dev->config;
596-
597-
if (config->dnoe.port) {
598-
gpio_pin_set_dt(&config->dnoe, 0);
587+
ret = gpio_pin_configure_dt(&config->dio, GPIO_INPUT);
588+
if (ret) {
589+
return ret;
599590
}
600591

601-
if (config->dout.port) {
602-
gpio_pin_set_dt(&config->dout, 0);
603-
} else {
604-
int ret;
605-
606-
ret = gpio_pin_configure_dt(&config->dio, GPIO_INPUT);
592+
if (config->noe.port) {
593+
ret = gpio_pin_configure_dt(&config->noe, GPIO_OUTPUT_ACTIVE);
607594
if (ret) {
608595
return ret;
609596
}
610597
}
611598

612-
if (config->noe.port) {
613-
gpio_pin_set_dt(&config->noe, 0);
599+
ret = gpio_pin_configure_dt(&config->clk, GPIO_OUTPUT_ACTIVE);
600+
if (ret) {
601+
return ret;
614602
}
615-
if (config->reset.port) {
616-
gpio_pin_set_dt(&config->reset, 1);
603+
604+
ret = gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_ACTIVE);
605+
if (ret) {
606+
return ret;
617607
}
618608

619609
return 0;
620610
}
621611

622-
static int sw_gpio_init(const struct device *dev)
612+
static int sw_port_off(const struct device *dev)
623613
{
624614
const struct sw_config *config = dev->config;
625-
struct sw_cfg_data *sw_data = dev->data;
626615
int ret;
627616

628-
ret = gpio_pin_configure_dt(&config->clk, GPIO_OUTPUT_ACTIVE);
629-
if (ret) {
630-
return ret;
631-
}
617+
/* If there is a transceiver connected to IO, pins should always be driven. */
618+
if (config->dnoe.port) {
619+
ret = gpio_pin_configure_dt(&config->dnoe, GPIO_OUTPUT_INACTIVE);
620+
if (ret) {
621+
return ret;
622+
}
632623

633-
ret = gpio_pin_configure_dt(&config->dio, GPIO_INPUT);
634-
if (ret) {
635-
return ret;
636-
}
624+
if (config->dout.port) {
625+
ret = gpio_pin_configure_dt(&config->dout, GPIO_OUTPUT_ACTIVE);
626+
if (ret) {
627+
return ret;
628+
}
629+
}
637630

638-
if (config->dout.port) {
639-
ret = gpio_pin_configure_dt(&config->dout, GPIO_OUTPUT_ACTIVE);
631+
ret = gpio_pin_configure_dt(&config->dio, GPIO_INPUT);
640632
if (ret) {
641633
return ret;
642634
}
643-
}
635+
} else {
636+
if (config->dout.port) {
637+
ret = gpio_pin_configure_dt(&config->dout, GPIO_DISCONNECTED);
638+
if (ret) {
639+
return ret;
640+
}
641+
}
644642

645-
if (config->dnoe.port) {
646-
ret = gpio_pin_configure_dt(&config->dnoe, GPIO_OUTPUT_INACTIVE);
643+
ret = gpio_pin_configure_dt(&config->dio, GPIO_DISCONNECTED);
647644
if (ret) {
648645
return ret;
649646
}
650647
}
651648

649+
/* If there is a transceiver connected to CLK, pins should always be driven. */
652650
if (config->noe.port) {
653651
ret = gpio_pin_configure_dt(&config->noe, GPIO_OUTPUT_INACTIVE);
654652
if (ret) {
655653
return ret;
656654
}
655+
656+
ret = gpio_pin_configure_dt(&config->clk, GPIO_OUTPUT_ACTIVE);
657+
if (ret) {
658+
return ret;
659+
}
660+
661+
} else {
662+
ret = gpio_pin_configure_dt(&config->clk, GPIO_DISCONNECTED);
663+
if (ret) {
664+
return ret;
665+
}
657666
}
658667

659668
if (config->reset.port) {
660-
ret = gpio_pin_configure_dt(&config->reset, GPIO_OUTPUT_ACTIVE);
669+
ret = gpio_pin_configure_dt(&config->reset, GPIO_DISCONNECTED);
661670
if (ret) {
662671
return ret;
663672
}
664673
}
665674

675+
return 0;
676+
}
677+
678+
static int sw_gpio_init(const struct device *dev)
679+
{
680+
struct sw_cfg_data *sw_data = dev->data;
681+
int ret;
682+
683+
/* start with the port turned off */
684+
ret = sw_port_off(dev);
685+
if (ret) {
686+
return ret;
687+
}
688+
666689
sw_data->turnaround = 1U;
667690
sw_data->data_phase = false;
668691
sw_data->fast_clock = false;
669-
sw_data->clock_delay = CLOCK_DELAY(SWDP_DEFAULT_SWCLK_FREQUENCY,
670-
config->port_write_cycles);
692+
sw_set_clock(dev, SWDP_DEFAULT_SWCLK_FREQUENCY);
671693

672694
return 0;
673695
}

drivers/dp/swdp_ll_pin.h

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -6,8 +6,9 @@
66

77
#include <zephyr/kernel.h>
88
#include <zephyr/drivers/gpio.h>
9+
#include <soc.h>
910

10-
#if defined(CONFIG_SOC_SERIES_NRF52X)
11+
#if defined(CONFIG_SOC_SERIES_NRF52X) || defined(CONFIG_SOC_SERIES_NRF53X)
1112
#define CPU_CLOCK 64000000U
1213
#else
1314
#define CPU_CLOCK CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC

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